;; Scheduling description for HyperSPARC.
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;; Scheduling description for HyperSPARC.
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;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; The HyperSPARC is a dual-issue processor. It is not all that fancy.
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;; The HyperSPARC is a dual-issue processor. It is not all that fancy.
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;; ??? There are some things not modelled. For example, sethi+or
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;; ??? There are some things not modelled. For example, sethi+or
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;; ??? coming right after each other are specifically identified and
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;; ??? coming right after each other are specifically identified and
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;; ??? dual-issued by the processor. Similarly for sethi+ld[reg+lo].
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;; ??? dual-issued by the processor. Similarly for sethi+ld[reg+lo].
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;; ??? Actually, to be more precise that rule is sort of modelled now.
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;; ??? Actually, to be more precise that rule is sort of modelled now.
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(define_automaton "hypersparc_0,hypersparc_1")
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(define_automaton "hypersparc_0,hypersparc_1")
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;; HyperSPARC/sparclite86x scheduling
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;; HyperSPARC/sparclite86x scheduling
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(define_cpu_unit "hs_memory,hs_branch,hs_shift,hs_fpalu" "hypersparc_0")
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(define_cpu_unit "hs_memory,hs_branch,hs_shift,hs_fpalu" "hypersparc_0")
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(define_cpu_unit "hs_fpmds" "hypersparc_1")
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(define_cpu_unit "hs_fpmds" "hypersparc_1")
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(define_insn_reservation "hs_load" 1
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(define_insn_reservation "hs_load" 1
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(eq_attr "type" "load,sload,fpload"))
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(eq_attr "type" "load,sload,fpload"))
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"hs_memory")
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"hs_memory")
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(define_insn_reservation "hs_store" 2
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(define_insn_reservation "hs_store" 2
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(eq_attr "type" "store,fpstore"))
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(eq_attr "type" "store,fpstore"))
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"hs_memory, nothing")
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"hs_memory, nothing")
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(define_insn_reservation "hs_slbranch" 1
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(define_insn_reservation "hs_slbranch" 1
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(and (eq_attr "cpu" "sparclite86x")
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(and (eq_attr "cpu" "sparclite86x")
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(eq_attr "type" "branch"))
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(eq_attr "type" "branch"))
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"hs_branch")
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"hs_branch")
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(define_insn_reservation "hs_slshift" 1
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(define_insn_reservation "hs_slshift" 1
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(and (eq_attr "cpu" "sparclite86x")
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(and (eq_attr "cpu" "sparclite86x")
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(eq_attr "type" "shift"))
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(eq_attr "type" "shift"))
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"hs_shift")
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"hs_shift")
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(define_insn_reservation "hs_fp_alu" 1
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(define_insn_reservation "hs_fp_alu" 1
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(eq_attr "type" "fp,fpmove,fpcmp"))
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(eq_attr "type" "fp,fpmove,fpcmp"))
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"hs_fpalu")
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"hs_fpalu")
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(define_insn_reservation "hs_fp_mult" 1
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(define_insn_reservation "hs_fp_mult" 1
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(eq_attr "type" "fpmul"))
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(eq_attr "type" "fpmul"))
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"hs_fpmds")
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"hs_fpmds")
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(define_insn_reservation "hs_fp_divs" 8
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(define_insn_reservation "hs_fp_divs" 8
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(eq_attr "type" "fpdivs"))
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(eq_attr "type" "fpdivs"))
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"hs_fpmds*6, nothing*2")
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"hs_fpmds*6, nothing*2")
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(define_insn_reservation "hs_fp_divd" 12
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(define_insn_reservation "hs_fp_divd" 12
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(eq_attr "type" "fpdivd"))
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(eq_attr "type" "fpdivd"))
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"hs_fpmds*10, nothing*2")
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"hs_fpmds*10, nothing*2")
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(define_insn_reservation "hs_fp_sqrt" 17
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(define_insn_reservation "hs_fp_sqrt" 17
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(eq_attr "type" "fpsqrts,fpsqrtd"))
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(eq_attr "type" "fpsqrts,fpsqrtd"))
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"hs_fpmds*15, nothing*2")
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"hs_fpmds*15, nothing*2")
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(define_insn_reservation "hs_imul" 17
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(define_insn_reservation "hs_imul" 17
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(eq_attr "type" "imul"))
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(eq_attr "type" "imul"))
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"hs_fpmds*15, nothing*2")
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"hs_fpmds*15, nothing*2")
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