;; Predicate definitions for NEC V850.
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;; Predicate definitions for NEC V850.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; Return true if OP is either a register or 0.
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;; Return true if OP is either a register or 0.
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(define_predicate "reg_or_0_operand"
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(define_predicate "reg_or_0_operand"
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(match_code "reg,subreg,const_int,const_double")
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(match_code "reg,subreg,const_int,const_double")
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{
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{
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if (GET_CODE (op) == CONST_INT)
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if (GET_CODE (op) == CONST_INT)
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return INTVAL (op) == 0;
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return INTVAL (op) == 0;
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else if (GET_CODE (op) == CONST_DOUBLE)
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else if (GET_CODE (op) == CONST_DOUBLE)
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return CONST_DOUBLE_OK_FOR_G (op);
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return CONST_DOUBLE_OK_FOR_G (op);
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else
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else
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return register_operand (op, mode);
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return register_operand (op, mode);
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})
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})
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;; Return true if OP is either a register or a signed five bit
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;; Return true if OP is either a register or a signed five bit
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;; integer.
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;; integer.
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(define_predicate "reg_or_int5_operand"
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(define_predicate "reg_or_int5_operand"
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(match_code "reg,subreg,const_int")
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(match_code "reg,subreg,const_int")
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{
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{
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if (GET_CODE (op) == CONST_INT)
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if (GET_CODE (op) == CONST_INT)
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return CONST_OK_FOR_J (INTVAL (op));
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return CONST_OK_FOR_J (INTVAL (op));
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else
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else
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return register_operand (op, mode);
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return register_operand (op, mode);
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})
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})
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;; Return true if OP is either a register or a signed nine bit
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;; Return true if OP is either a register or a signed nine bit
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;; integer.
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;; integer.
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(define_predicate "reg_or_int9_operand"
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(define_predicate "reg_or_int9_operand"
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(match_code "reg,subreg,const_int")
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(match_code "reg,subreg,const_int")
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{
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{
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if (GET_CODE (op) == CONST_INT)
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if (GET_CODE (op) == CONST_INT)
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return CONST_OK_FOR_O (INTVAL (op));
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return CONST_OK_FOR_O (INTVAL (op));
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return register_operand (op, mode);
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return register_operand (op, mode);
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})
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})
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;; Return true if OP is either a register or a const integer.
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;; Return true if OP is either a register or a const integer.
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(define_predicate "reg_or_const_operand"
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(define_predicate "reg_or_const_operand"
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(match_code "reg,const_int")
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(match_code "reg,const_int")
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{
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{
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if (GET_CODE (op) == CONST_INT)
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if (GET_CODE (op) == CONST_INT)
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return TRUE;
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return TRUE;
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return register_operand (op, mode);
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return register_operand (op, mode);
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})
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})
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;; Return true if OP is a valid call operand.
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;; Return true if OP is a valid call operand.
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(define_predicate "call_address_operand"
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(define_predicate "call_address_operand"
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(match_code "reg,symbol_ref")
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(match_code "reg,symbol_ref")
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{
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{
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/* Only registers are valid call operands if TARGET_LONG_CALLS. */
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/* Only registers are valid call operands if TARGET_LONG_CALLS. */
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if (TARGET_LONG_CALLS)
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if (TARGET_LONG_CALLS)
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return GET_CODE (op) == REG;
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return GET_CODE (op) == REG;
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return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
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return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "movsi_source_operand"
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(define_predicate "movsi_source_operand"
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(match_code "label_ref,symbol_ref,const_int,const_double,const,high,mem,reg,subreg")
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(match_code "label_ref,symbol_ref,const_int,const_double,const,high,mem,reg,subreg")
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{
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{
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/* Some constants, as well as symbolic operands
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/* Some constants, as well as symbolic operands
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must be done with HIGH & LO_SUM patterns. */
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must be done with HIGH & LO_SUM patterns. */
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if (CONSTANT_P (op)
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if (CONSTANT_P (op)
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&& GET_CODE (op) != HIGH
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&& GET_CODE (op) != HIGH
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&& !(GET_CODE (op) == CONST_INT
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&& !(GET_CODE (op) == CONST_INT
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&& (CONST_OK_FOR_J (INTVAL (op))
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&& (CONST_OK_FOR_J (INTVAL (op))
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|| CONST_OK_FOR_K (INTVAL (op))
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|| CONST_OK_FOR_K (INTVAL (op))
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|| CONST_OK_FOR_L (INTVAL (op)))))
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|| CONST_OK_FOR_L (INTVAL (op)))))
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return special_symbolref_operand (op, mode);
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return special_symbolref_operand (op, mode);
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else
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else
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return general_operand (op, mode);
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return general_operand (op, mode);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "special_symbolref_operand"
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(define_predicate "special_symbolref_operand"
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(match_code "symbol_ref")
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(match_code "symbol_ref")
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{
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{
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if (GET_CODE (op) == CONST
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if (GET_CODE (op) == CONST
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&& GET_CODE (XEXP (op, 0)) == PLUS
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&& GET_CODE (XEXP (op, 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
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&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
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&& CONST_OK_FOR_K (INTVAL (XEXP (XEXP (op, 0), 1))))
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&& CONST_OK_FOR_K (INTVAL (XEXP (XEXP (op, 0), 1))))
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op = XEXP (XEXP (op, 0), 0);
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op = XEXP (XEXP (op, 0), 0);
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if (GET_CODE (op) == SYMBOL_REF)
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if (GET_CODE (op) == SYMBOL_REF)
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return (SYMBOL_REF_FLAGS (op)
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return (SYMBOL_REF_FLAGS (op)
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& (SYMBOL_FLAG_ZDA | SYMBOL_FLAG_TDA | SYMBOL_FLAG_SDA)) != 0;
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& (SYMBOL_FLAG_ZDA | SYMBOL_FLAG_TDA | SYMBOL_FLAG_SDA)) != 0;
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return FALSE;
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return FALSE;
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "power_of_two_operand"
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(define_predicate "power_of_two_operand"
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(match_code "const_int")
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(match_code "const_int")
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{
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{
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if (GET_CODE (op) != CONST_INT)
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if (GET_CODE (op) != CONST_INT)
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return 0;
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return 0;
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if (exact_log2 (INTVAL (op)) == -1)
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if (exact_log2 (INTVAL (op)) == -1)
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return 0;
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return 0;
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return 1;
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return 1;
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})
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})
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;; Return nonzero if the given RTX is suitable for collapsing into a
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;; Return nonzero if the given RTX is suitable for collapsing into a
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;; jump to a function prologue.
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;; jump to a function prologue.
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(define_predicate "pattern_is_ok_for_prologue"
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(define_predicate "pattern_is_ok_for_prologue"
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(match_code "parallel")
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(match_code "parallel")
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{
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{
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int count = XVECLEN (op, 0);
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int count = XVECLEN (op, 0);
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int i;
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int i;
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rtx vector_element;
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rtx vector_element;
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/* If there are no registers to save then the function prologue
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/* If there are no registers to save then the function prologue
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is not suitable. */
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is not suitable. */
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if (count <= 2)
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if (count <= 2)
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return 0;
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return 0;
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/* The pattern matching has already established that we are adjusting the
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/* The pattern matching has already established that we are adjusting the
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stack and pushing at least one register. We must now check that the
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stack and pushing at least one register. We must now check that the
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remaining entries in the vector to make sure that they are also register
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remaining entries in the vector to make sure that they are also register
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pushes, except for the last entry which should be a CLOBBER of r10.
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pushes, except for the last entry which should be a CLOBBER of r10.
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The test below performs the C equivalent of this machine description
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The test below performs the C equivalent of this machine description
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pattern match:
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pattern match:
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(set (mem:SI (plus:SI (reg:SI 3)
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(set (mem:SI (plus:SI (reg:SI 3)
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(match_operand:SI 2 "immediate_operand" "i")))
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(match_operand:SI 2 "immediate_operand" "i")))
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(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
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(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
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*/
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*/
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for (i = 2; i < count - (TARGET_LONG_CALLS ? 2: 1); i++)
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for (i = 2; i < count - (TARGET_LONG_CALLS ? 2: 1); i++)
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{
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{
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rtx dest;
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rtx dest;
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rtx src;
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rtx src;
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rtx plus;
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rtx plus;
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vector_element = XVECEXP (op, 0, i);
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vector_element = XVECEXP (op, 0, i);
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if (GET_CODE (vector_element) != SET)
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if (GET_CODE (vector_element) != SET)
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return 0;
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return 0;
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dest = SET_DEST (vector_element);
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dest = SET_DEST (vector_element);
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src = SET_SRC (vector_element);
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src = SET_SRC (vector_element);
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if (GET_CODE (dest) != MEM
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if (GET_CODE (dest) != MEM
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|| GET_MODE (dest) != SImode
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|| GET_MODE (dest) != SImode
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|| GET_CODE (src) != REG
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|| GET_CODE (src) != REG
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|| GET_MODE (src) != SImode
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|| GET_MODE (src) != SImode
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|| ! register_is_ok_for_epilogue (src, SImode))
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|| ! register_is_ok_for_epilogue (src, SImode))
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return 0;
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return 0;
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plus = XEXP (dest, 0);
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plus = XEXP (dest, 0);
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if ( GET_CODE (plus) != PLUS
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if ( GET_CODE (plus) != PLUS
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|| GET_CODE (XEXP (plus, 0)) != REG
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|| GET_CODE (XEXP (plus, 0)) != REG
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|| GET_MODE (XEXP (plus, 0)) != SImode
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|| GET_MODE (XEXP (plus, 0)) != SImode
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|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
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|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
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|| GET_CODE (XEXP (plus, 1)) != CONST_INT)
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|| GET_CODE (XEXP (plus, 1)) != CONST_INT)
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return 0;
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return 0;
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/* If the register is being pushed somewhere other than the stack
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/* If the register is being pushed somewhere other than the stack
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space just acquired by the first operand then abandon this quest.
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space just acquired by the first operand then abandon this quest.
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Note: the test is <= because both values are negative. */
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Note: the test is <= because both values are negative. */
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if (INTVAL (XEXP (plus, 1))
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if (INTVAL (XEXP (plus, 1))
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<= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
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<= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
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{
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{
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return 0;
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return 0;
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}
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}
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}
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}
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/* Make sure that the last entries in the vector are clobbers. */
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/* Make sure that the last entries in the vector are clobbers. */
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for (; i < count; i++)
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for (; i < count; i++)
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{
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{
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vector_element = XVECEXP (op, 0, i);
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vector_element = XVECEXP (op, 0, i);
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if (GET_CODE (vector_element) != CLOBBER
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if (GET_CODE (vector_element) != CLOBBER
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|| GET_CODE (XEXP (vector_element, 0)) != REG
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|| GET_CODE (XEXP (vector_element, 0)) != REG
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|| !(REGNO (XEXP (vector_element, 0)) == 10
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|| !(REGNO (XEXP (vector_element, 0)) == 10
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|| (TARGET_LONG_CALLS ? (REGNO (XEXP (vector_element, 0)) == 11) : 0 )))
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|| (TARGET_LONG_CALLS ? (REGNO (XEXP (vector_element, 0)) == 11) : 0 )))
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return 0;
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return 0;
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}
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}
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return 1;
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return 1;
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})
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})
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;; Return nonzero if the given RTX is suitable for collapsing into
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;; Return nonzero if the given RTX is suitable for collapsing into
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;; jump to a function epilogue.
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;; jump to a function epilogue.
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(define_predicate "pattern_is_ok_for_epilogue"
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(define_predicate "pattern_is_ok_for_epilogue"
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(match_code "parallel")
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(match_code "parallel")
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{
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{
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int count = XVECLEN (op, 0);
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int count = XVECLEN (op, 0);
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int i;
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int i;
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/* If there are no registers to restore then the function epilogue
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/* If there are no registers to restore then the function epilogue
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is not suitable. */
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is not suitable. */
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if (count <= 2)
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if (count <= 2)
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return 0;
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return 0;
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/* The pattern matching has already established that we are performing a
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/* The pattern matching has already established that we are performing a
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function epilogue and that we are popping at least one register. We must
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function epilogue and that we are popping at least one register. We must
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now check the remaining entries in the vector to make sure that they are
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now check the remaining entries in the vector to make sure that they are
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also register pops. There is no good reason why there should ever be
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also register pops. There is no good reason why there should ever be
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anything else in this vector, but being paranoid always helps...
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anything else in this vector, but being paranoid always helps...
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The test below performs the C equivalent of this machine description
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The test below performs the C equivalent of this machine description
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pattern match:
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pattern match:
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(set (match_operand:SI n "register_is_ok_for_epilogue" "r")
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(set (match_operand:SI n "register_is_ok_for_epilogue" "r")
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(mem:SI (plus:SI (reg:SI 3) (match_operand:SI n "immediate_operand" "i"))))
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(mem:SI (plus:SI (reg:SI 3) (match_operand:SI n "immediate_operand" "i"))))
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*/
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*/
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for (i = 3; i < count; i++)
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for (i = 3; i < count; i++)
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{
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{
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rtx vector_element = XVECEXP (op, 0, i);
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rtx vector_element = XVECEXP (op, 0, i);
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rtx dest;
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rtx dest;
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rtx src;
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rtx src;
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rtx plus;
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rtx plus;
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if (GET_CODE (vector_element) != SET)
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if (GET_CODE (vector_element) != SET)
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return 0;
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return 0;
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dest = SET_DEST (vector_element);
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dest = SET_DEST (vector_element);
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src = SET_SRC (vector_element);
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src = SET_SRC (vector_element);
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if (GET_CODE (dest) != REG
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if (GET_CODE (dest) != REG
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|| GET_MODE (dest) != SImode
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|| GET_MODE (dest) != SImode
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|| ! register_is_ok_for_epilogue (dest, SImode)
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|| ! register_is_ok_for_epilogue (dest, SImode)
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|| GET_CODE (src) != MEM
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|| GET_CODE (src) != MEM
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|| GET_MODE (src) != SImode)
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|| GET_MODE (src) != SImode)
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return 0;
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return 0;
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plus = XEXP (src, 0);
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plus = XEXP (src, 0);
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if (GET_CODE (plus) != PLUS
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if (GET_CODE (plus) != PLUS
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|| GET_CODE (XEXP (plus, 0)) != REG
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|| GET_CODE (XEXP (plus, 0)) != REG
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|| GET_MODE (XEXP (plus, 0)) != SImode
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|| GET_MODE (XEXP (plus, 0)) != SImode
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|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
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|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
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|| GET_CODE (XEXP (plus, 1)) != CONST_INT)
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|| GET_CODE (XEXP (plus, 1)) != CONST_INT)
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return 0;
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return 0;
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}
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}
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return 1;
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return 1;
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})
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})
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;; Return true if the given RTX is a register which can be restored by
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;; Return true if the given RTX is a register which can be restored by
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;; a function epilogue.
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;; a function epilogue.
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(define_predicate "register_is_ok_for_epilogue"
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(define_predicate "register_is_ok_for_epilogue"
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(match_code "reg")
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(match_code "reg")
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{
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{
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/* The save/restore routines can only cope with registers 20 - 31. */
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/* The save/restore routines can only cope with registers 20 - 31. */
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return ((GET_CODE (op) == REG)
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return ((GET_CODE (op) == REG)
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&& (((REGNO (op) >= 20) && REGNO (op) <= 31)));
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&& (((REGNO (op) >= 20) && REGNO (op) <= 31)));
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})
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})
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;; Return nonzero if the given RTX is suitable for collapsing into a
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;; Return nonzero if the given RTX is suitable for collapsing into a
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;; DISPOSE instruction.
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;; DISPOSE instruction.
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(define_predicate "pattern_is_ok_for_dispose"
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(define_predicate "pattern_is_ok_for_dispose"
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(match_code "parallel")
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(match_code "parallel")
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{
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{
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int count = XVECLEN (op, 0);
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int count = XVECLEN (op, 0);
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int i;
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int i;
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|
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/* If there are no registers to restore then
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/* If there are no registers to restore then
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the dispose instruction is not suitable. */
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the dispose instruction is not suitable. */
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if (count <= 2)
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if (count <= 2)
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return 0;
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return 0;
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|
|
/* The pattern matching has already established that we are performing a
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/* The pattern matching has already established that we are performing a
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function epilogue and that we are popping at least one register. We must
|
function epilogue and that we are popping at least one register. We must
|
now check the remaining entries in the vector to make sure that they are
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now check the remaining entries in the vector to make sure that they are
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also register pops. There is no good reason why there should ever be
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also register pops. There is no good reason why there should ever be
|
anything else in this vector, but being paranoid always helps...
|
anything else in this vector, but being paranoid always helps...
|
|
|
The test below performs the C equivalent of this machine description
|
The test below performs the C equivalent of this machine description
|
pattern match:
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pattern match:
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|
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(set (match_operand:SI n "register_is_ok_for_epilogue" "r")
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(set (match_operand:SI n "register_is_ok_for_epilogue" "r")
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(mem:SI (plus:SI (reg:SI 3)
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(mem:SI (plus:SI (reg:SI 3)
|
(match_operand:SI n "immediate_operand" "i"))))
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(match_operand:SI n "immediate_operand" "i"))))
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*/
|
*/
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|
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for (i = 3; i < count; i++)
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for (i = 3; i < count; i++)
|
{
|
{
|
rtx vector_element = XVECEXP (op, 0, i);
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rtx vector_element = XVECEXP (op, 0, i);
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rtx dest;
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rtx dest;
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rtx src;
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rtx src;
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rtx plus;
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rtx plus;
|
|
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if (GET_CODE (vector_element) != SET)
|
if (GET_CODE (vector_element) != SET)
|
return 0;
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return 0;
|
|
|
dest = SET_DEST (vector_element);
|
dest = SET_DEST (vector_element);
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src = SET_SRC (vector_element);
|
src = SET_SRC (vector_element);
|
|
|
if ( GET_CODE (dest) != REG
|
if ( GET_CODE (dest) != REG
|
|| GET_MODE (dest) != SImode
|
|| GET_MODE (dest) != SImode
|
|| ! register_is_ok_for_epilogue (dest, SImode)
|
|| ! register_is_ok_for_epilogue (dest, SImode)
|
|| GET_CODE (src) != MEM
|
|| GET_CODE (src) != MEM
|
|| GET_MODE (src) != SImode)
|
|| GET_MODE (src) != SImode)
|
return 0;
|
return 0;
|
|
|
plus = XEXP (src, 0);
|
plus = XEXP (src, 0);
|
|
|
if ( GET_CODE (plus) != PLUS
|
if ( GET_CODE (plus) != PLUS
|
|| GET_CODE (XEXP (plus, 0)) != REG
|
|| GET_CODE (XEXP (plus, 0)) != REG
|
|| GET_MODE (XEXP (plus, 0)) != SImode
|
|| GET_MODE (XEXP (plus, 0)) != SImode
|
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|
|| GET_CODE (XEXP (plus, 1)) != CONST_INT)
|
|| GET_CODE (XEXP (plus, 1)) != CONST_INT)
|
return 0;
|
return 0;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
})
|
})
|
|
|
;; Return nonzero if the given RTX is suitable for collapsing into a
|
;; Return nonzero if the given RTX is suitable for collapsing into a
|
;; PREPARE instruction.
|
;; PREPARE instruction.
|
|
|
(define_predicate "pattern_is_ok_for_prepare"
|
(define_predicate "pattern_is_ok_for_prepare"
|
(match_code "parallel")
|
(match_code "parallel")
|
{
|
{
|
int count = XVECLEN (op, 0);
|
int count = XVECLEN (op, 0);
|
int i;
|
int i;
|
|
|
/* If there are no registers to restore then the prepare instruction
|
/* If there are no registers to restore then the prepare instruction
|
is not suitable. */
|
is not suitable. */
|
if (count <= 1)
|
if (count <= 1)
|
return 0;
|
return 0;
|
|
|
/* The pattern matching has already established that we are adjusting the
|
/* The pattern matching has already established that we are adjusting the
|
stack and pushing at least one register. We must now check that the
|
stack and pushing at least one register. We must now check that the
|
remaining entries in the vector to make sure that they are also register
|
remaining entries in the vector to make sure that they are also register
|
pushes.
|
pushes.
|
|
|
The test below performs the C equivalent of this machine description
|
The test below performs the C equivalent of this machine description
|
pattern match:
|
pattern match:
|
|
|
(set (mem:SI (plus:SI (reg:SI 3)
|
(set (mem:SI (plus:SI (reg:SI 3)
|
(match_operand:SI 2 "immediate_operand" "i")))
|
(match_operand:SI 2 "immediate_operand" "i")))
|
(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
|
(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
|
|
|
*/
|
*/
|
|
|
for (i = 2; i < count; i++)
|
for (i = 2; i < count; i++)
|
{
|
{
|
rtx vector_element = XVECEXP (op, 0, i);
|
rtx vector_element = XVECEXP (op, 0, i);
|
rtx dest;
|
rtx dest;
|
rtx src;
|
rtx src;
|
rtx plus;
|
rtx plus;
|
|
|
if (GET_CODE (vector_element) != SET)
|
if (GET_CODE (vector_element) != SET)
|
return 0;
|
return 0;
|
|
|
dest = SET_DEST (vector_element);
|
dest = SET_DEST (vector_element);
|
src = SET_SRC (vector_element);
|
src = SET_SRC (vector_element);
|
|
|
if ( GET_CODE (dest) != MEM
|
if ( GET_CODE (dest) != MEM
|
|| GET_MODE (dest) != SImode
|
|| GET_MODE (dest) != SImode
|
|| GET_CODE (src) != REG
|
|| GET_CODE (src) != REG
|
|| GET_MODE (src) != SImode
|
|| GET_MODE (src) != SImode
|
|| ! register_is_ok_for_epilogue (src, SImode)
|
|| ! register_is_ok_for_epilogue (src, SImode)
|
)
|
)
|
return 0;
|
return 0;
|
|
|
plus = XEXP (dest, 0);
|
plus = XEXP (dest, 0);
|
|
|
if ( GET_CODE (plus) != PLUS
|
if ( GET_CODE (plus) != PLUS
|
|| GET_CODE (XEXP (plus, 0)) != REG
|
|| GET_CODE (XEXP (plus, 0)) != REG
|
|| GET_MODE (XEXP (plus, 0)) != SImode
|
|| GET_MODE (XEXP (plus, 0)) != SImode
|
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|
|| GET_CODE (XEXP (plus, 1)) != CONST_INT)
|
|| GET_CODE (XEXP (plus, 1)) != CONST_INT)
|
return 0;
|
return 0;
|
|
|
/* If the register is being pushed somewhere other than the stack
|
/* If the register is being pushed somewhere other than the stack
|
space just acquired by the first operand then abandon this quest.
|
space just acquired by the first operand then abandon this quest.
|
Note: the test is <= because both values are negative. */
|
Note: the test is <= because both values are negative. */
|
if (INTVAL (XEXP (plus, 1))
|
if (INTVAL (XEXP (plus, 1))
|
<= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
|
<= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
|
return 0;
|
return 0;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "not_power_of_two_operand"
|
(define_predicate "not_power_of_two_operand"
|
(match_code "const_int")
|
(match_code "const_int")
|
{
|
{
|
unsigned int mask;
|
unsigned int mask;
|
|
|
if (mode == QImode)
|
if (mode == QImode)
|
mask = 0xff;
|
mask = 0xff;
|
else if (mode == HImode)
|
else if (mode == HImode)
|
mask = 0xffff;
|
mask = 0xffff;
|
else if (mode == SImode)
|
else if (mode == SImode)
|
mask = 0xffffffff;
|
mask = 0xffffffff;
|
else
|
else
|
return 0;
|
return 0;
|
|
|
if (GET_CODE (op) != CONST_INT)
|
if (GET_CODE (op) != CONST_INT)
|
return 0;
|
return 0;
|
|
|
if (exact_log2 (~INTVAL (op) & mask) == -1)
|
if (exact_log2 (~INTVAL (op) & mask) == -1)
|
return 0;
|
return 0;
|
return 1;
|
return 1;
|
})
|
})
|
|
|
