URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.dg/] [torture/] [cris-asm-mof-1.c] - Diff between revs 154 and 816

Rev 154	Rev 816
`/* { dg-do compile { target cris-- } } */`	`/* { dg-do compile { target cris-- } } */`
`/* { dg-options "-O2 -march=v10" } */`	`/* { dg-options "-O2 -march=v10" } */`
`/* { dg-final { scan-assembler "in-asm: .mof" } } */`	`/* { dg-final { scan-assembler "in-asm: .mof" } } */`
`/* { dg-final { scan-assembler "out-asm: .mof" } } */`	`/* { dg-final { scan-assembler "out-asm: .mof" } } */`
`/* { dg-final { scan-assembler "in2-asm: .mof" } } */`	`/* { dg-final { scan-assembler "in2-asm: .mof" } } */`
`/* { dg-final { scan-assembler "out2-asm: .mof" } } */`	`/* { dg-final { scan-assembler "out2-asm: .mof" } } */`

`unsigned int`	`unsigned int`
`in (unsigned int i)`	`in (unsigned int i)`
`{`	`{`
`register int i0 asm ("mof") = i;`	`register int i0 asm ("mof") = i;`
`asm ("in-asm: %0" : : "x" (i0));`	`asm ("in-asm: %0" : : "x" (i0));`
`}`	`}`

`unsigned int`	`unsigned int`
`out (void)`	`out (void)`
`{`	`{`
`register int o asm ("mof");`	`register int o asm ("mof");`
`asm ("out-asm: %0" : "=x" (o));`	`asm ("out-asm: %0" : "=x" (o));`
`return o;`	`return o;`
`}`	`}`

`unsigned int`	`unsigned int`
`in2 (unsigned int i)`	`in2 (unsigned int i)`
`{`	`{`
`asm ("in2-asm: %0" : : "h" (i));`	`asm ("in2-asm: %0" : : "h" (i));`
`}`	`}`

`unsigned int`	`unsigned int`
`out2 (void)`	`out2 (void)`
`{`	`{`
`unsigned int o;`	`unsigned int o;`
`asm ("out2-asm: %0" : "=h" (o));`	`asm ("out2-asm: %0" : "=h" (o));`
`return o;`	`return o;`
`}`	`}`