URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [mips/] [mips32-dsp-type.c] - Diff between revs 154 and 816

Rev 154	Rev 816
`/* Test MIPS32 DSP instructions */`	`/* Test MIPS32 DSP instructions */`
`/* { dg-do compile } */`	`/* { dg-do compile } */`
`/* { dg-mips-options "-march=mips32 -mdsp" } */`	`/* { dg-mips-options "-march=mips32 -mdsp" } */`
`/* { dg-final { scan-assembler "addq.ph" } } */`	`/* { dg-final { scan-assembler "addq.ph" } } */`
`/* { dg-final { scan-assembler "addu.qb" } } */`	`/* { dg-final { scan-assembler "addu.qb" } } */`
`/* { dg-final { scan-assembler "subq.ph" } } */`	`/* { dg-final { scan-assembler "subq.ph" } } */`
`/* { dg-final { scan-assembler "subu.qb" } } */`	`/* { dg-final { scan-assembler "subu.qb" } } */`

`typedef char v4qi __attribute__ ((vector_size(4)));`	`typedef char v4qi __attribute__ ((vector_size(4)));`
`typedef short v2hi __attribute__ ((vector_size(4)));`	`typedef short v2hi __attribute__ ((vector_size(4)));`

`v2hi add_v2hi (v2hi a, v2hi b)`	`v2hi add_v2hi (v2hi a, v2hi b)`
`{`	`{`
`return a + b;`	`return a + b;`
`}`	`}`

`v4qi add_v4qi (v4qi a, v4qi b)`	`v4qi add_v4qi (v4qi a, v4qi b)`
`{`	`{`
`return a + b;`	`return a + b;`
`}`	`}`

`v2hi sub_v2hi (v2hi a, v2hi b)`	`v2hi sub_v2hi (v2hi a, v2hi b)`
`{`	`{`
`return a - b;`	`return a - b;`
`}`	`}`

`v4qi sub_v4qi (v4qi a, v4qi b)`	`v4qi sub_v4qi (v4qi a, v4qi b)`
`{`	`{`
`return a - b;`	`return a - b;`
`}`	`}`