/* This file defines the interface between the Arm simulator and GDB.
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/* This file defines the interface between the Arm simulator and GDB.
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Copyright 2002, 2003, 2007, 2008 Free Software Foundation, Inc.
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Copyright 2002, 2003, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Red Hat.
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Contributed by Red Hat.
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This file is part of GDB.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#if !defined (SIM_ARM_H)
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#if !defined (SIM_ARM_H)
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#define SIM_ARM_H
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#define SIM_ARM_H
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#ifdef __cplusplus
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#ifdef __cplusplus
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extern "C" { // }
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extern "C" { // }
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#endif
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#endif
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enum sim_arm_regs
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enum sim_arm_regs
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{
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{
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SIM_ARM_R0_REGNUM,
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SIM_ARM_R0_REGNUM,
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SIM_ARM_R1_REGNUM,
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SIM_ARM_R1_REGNUM,
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SIM_ARM_R2_REGNUM,
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SIM_ARM_R2_REGNUM,
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SIM_ARM_R3_REGNUM,
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SIM_ARM_R3_REGNUM,
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SIM_ARM_R4_REGNUM,
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SIM_ARM_R4_REGNUM,
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SIM_ARM_R5_REGNUM,
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SIM_ARM_R5_REGNUM,
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SIM_ARM_R6_REGNUM,
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SIM_ARM_R6_REGNUM,
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SIM_ARM_R7_REGNUM,
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SIM_ARM_R7_REGNUM,
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SIM_ARM_R8_REGNUM,
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SIM_ARM_R8_REGNUM,
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SIM_ARM_R9_REGNUM,
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SIM_ARM_R9_REGNUM,
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SIM_ARM_R10_REGNUM,
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SIM_ARM_R10_REGNUM,
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SIM_ARM_R11_REGNUM,
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SIM_ARM_R11_REGNUM,
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SIM_ARM_R12_REGNUM,
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SIM_ARM_R12_REGNUM,
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SIM_ARM_R13_REGNUM,
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SIM_ARM_R13_REGNUM,
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SIM_ARM_R14_REGNUM,
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SIM_ARM_R14_REGNUM,
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SIM_ARM_R15_REGNUM, /* PC */
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SIM_ARM_R15_REGNUM, /* PC */
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SIM_ARM_FP0_REGNUM,
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SIM_ARM_FP0_REGNUM,
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SIM_ARM_FP1_REGNUM,
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SIM_ARM_FP1_REGNUM,
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SIM_ARM_FP2_REGNUM,
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SIM_ARM_FP2_REGNUM,
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SIM_ARM_FP3_REGNUM,
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SIM_ARM_FP3_REGNUM,
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SIM_ARM_FP4_REGNUM,
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SIM_ARM_FP4_REGNUM,
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SIM_ARM_FP5_REGNUM,
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SIM_ARM_FP5_REGNUM,
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SIM_ARM_FP6_REGNUM,
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SIM_ARM_FP6_REGNUM,
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SIM_ARM_FP7_REGNUM,
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SIM_ARM_FP7_REGNUM,
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SIM_ARM_FPS_REGNUM,
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SIM_ARM_FPS_REGNUM,
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SIM_ARM_PS_REGNUM,
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SIM_ARM_PS_REGNUM,
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SIM_ARM_MAVERIC_COP0R0_REGNUM,
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SIM_ARM_MAVERIC_COP0R0_REGNUM,
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SIM_ARM_MAVERIC_COP0R1_REGNUM,
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SIM_ARM_MAVERIC_COP0R1_REGNUM,
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SIM_ARM_MAVERIC_COP0R2_REGNUM,
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SIM_ARM_MAVERIC_COP0R2_REGNUM,
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SIM_ARM_MAVERIC_COP0R3_REGNUM,
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SIM_ARM_MAVERIC_COP0R3_REGNUM,
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SIM_ARM_MAVERIC_COP0R4_REGNUM,
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SIM_ARM_MAVERIC_COP0R4_REGNUM,
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SIM_ARM_MAVERIC_COP0R5_REGNUM,
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SIM_ARM_MAVERIC_COP0R5_REGNUM,
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SIM_ARM_MAVERIC_COP0R6_REGNUM,
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SIM_ARM_MAVERIC_COP0R6_REGNUM,
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SIM_ARM_MAVERIC_COP0R7_REGNUM,
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SIM_ARM_MAVERIC_COP0R7_REGNUM,
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SIM_ARM_MAVERIC_COP0R8_REGNUM,
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SIM_ARM_MAVERIC_COP0R8_REGNUM,
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SIM_ARM_MAVERIC_COP0R9_REGNUM,
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SIM_ARM_MAVERIC_COP0R9_REGNUM,
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SIM_ARM_MAVERIC_COP0R10_REGNUM,
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SIM_ARM_MAVERIC_COP0R10_REGNUM,
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SIM_ARM_MAVERIC_COP0R11_REGNUM,
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SIM_ARM_MAVERIC_COP0R11_REGNUM,
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SIM_ARM_MAVERIC_COP0R12_REGNUM,
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SIM_ARM_MAVERIC_COP0R12_REGNUM,
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SIM_ARM_MAVERIC_COP0R13_REGNUM,
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SIM_ARM_MAVERIC_COP0R13_REGNUM,
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SIM_ARM_MAVERIC_COP0R14_REGNUM,
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SIM_ARM_MAVERIC_COP0R14_REGNUM,
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SIM_ARM_MAVERIC_COP0R15_REGNUM,
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SIM_ARM_MAVERIC_COP0R15_REGNUM,
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SIM_ARM_MAVERIC_DSPSC_REGNUM,
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SIM_ARM_MAVERIC_DSPSC_REGNUM,
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SIM_ARM_IWMMXT_COP0R0_REGNUM,
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SIM_ARM_IWMMXT_COP0R0_REGNUM,
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SIM_ARM_IWMMXT_COP0R1_REGNUM,
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SIM_ARM_IWMMXT_COP0R1_REGNUM,
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SIM_ARM_IWMMXT_COP0R2_REGNUM,
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SIM_ARM_IWMMXT_COP0R2_REGNUM,
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SIM_ARM_IWMMXT_COP0R3_REGNUM,
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SIM_ARM_IWMMXT_COP0R3_REGNUM,
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SIM_ARM_IWMMXT_COP0R4_REGNUM,
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SIM_ARM_IWMMXT_COP0R4_REGNUM,
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SIM_ARM_IWMMXT_COP0R5_REGNUM,
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SIM_ARM_IWMMXT_COP0R5_REGNUM,
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SIM_ARM_IWMMXT_COP0R6_REGNUM,
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SIM_ARM_IWMMXT_COP0R6_REGNUM,
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SIM_ARM_IWMMXT_COP0R7_REGNUM,
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SIM_ARM_IWMMXT_COP0R7_REGNUM,
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SIM_ARM_IWMMXT_COP0R8_REGNUM,
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SIM_ARM_IWMMXT_COP0R8_REGNUM,
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SIM_ARM_IWMMXT_COP0R9_REGNUM,
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SIM_ARM_IWMMXT_COP0R9_REGNUM,
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SIM_ARM_IWMMXT_COP0R10_REGNUM,
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SIM_ARM_IWMMXT_COP0R10_REGNUM,
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SIM_ARM_IWMMXT_COP0R11_REGNUM,
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SIM_ARM_IWMMXT_COP0R11_REGNUM,
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SIM_ARM_IWMMXT_COP0R12_REGNUM,
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SIM_ARM_IWMMXT_COP0R12_REGNUM,
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SIM_ARM_IWMMXT_COP0R13_REGNUM,
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SIM_ARM_IWMMXT_COP0R13_REGNUM,
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SIM_ARM_IWMMXT_COP0R14_REGNUM,
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SIM_ARM_IWMMXT_COP0R14_REGNUM,
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SIM_ARM_IWMMXT_COP0R15_REGNUM,
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SIM_ARM_IWMMXT_COP0R15_REGNUM,
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SIM_ARM_IWMMXT_COP1R0_REGNUM,
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SIM_ARM_IWMMXT_COP1R0_REGNUM,
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SIM_ARM_IWMMXT_COP1R1_REGNUM,
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SIM_ARM_IWMMXT_COP1R1_REGNUM,
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SIM_ARM_IWMMXT_COP1R2_REGNUM,
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SIM_ARM_IWMMXT_COP1R2_REGNUM,
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SIM_ARM_IWMMXT_COP1R3_REGNUM,
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SIM_ARM_IWMMXT_COP1R3_REGNUM,
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SIM_ARM_IWMMXT_COP1R4_REGNUM,
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SIM_ARM_IWMMXT_COP1R4_REGNUM,
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SIM_ARM_IWMMXT_COP1R5_REGNUM,
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SIM_ARM_IWMMXT_COP1R5_REGNUM,
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SIM_ARM_IWMMXT_COP1R6_REGNUM,
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SIM_ARM_IWMMXT_COP1R6_REGNUM,
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SIM_ARM_IWMMXT_COP1R7_REGNUM,
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SIM_ARM_IWMMXT_COP1R7_REGNUM,
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SIM_ARM_IWMMXT_COP1R8_REGNUM,
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SIM_ARM_IWMMXT_COP1R8_REGNUM,
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SIM_ARM_IWMMXT_COP1R9_REGNUM,
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SIM_ARM_IWMMXT_COP1R9_REGNUM,
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SIM_ARM_IWMMXT_COP1R10_REGNUM,
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SIM_ARM_IWMMXT_COP1R10_REGNUM,
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SIM_ARM_IWMMXT_COP1R11_REGNUM,
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SIM_ARM_IWMMXT_COP1R11_REGNUM,
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SIM_ARM_IWMMXT_COP1R12_REGNUM,
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SIM_ARM_IWMMXT_COP1R12_REGNUM,
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SIM_ARM_IWMMXT_COP1R13_REGNUM,
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SIM_ARM_IWMMXT_COP1R13_REGNUM,
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SIM_ARM_IWMMXT_COP1R14_REGNUM,
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SIM_ARM_IWMMXT_COP1R14_REGNUM,
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SIM_ARM_IWMMXT_COP1R15_REGNUM
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SIM_ARM_IWMMXT_COP1R15_REGNUM
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};
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};
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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#endif
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#endif
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