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/* Table of opcodes for the PA-RISC.

/* Table of opcodes for the PA-RISC.

   Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,

   Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,

   2001, 2002, 2003, 2004, 2005, 2006, 2009

   2001, 2002, 2003, 2004, 2005, 2006, 2009

   Free Software Foundation, Inc.

   Free Software Foundation, Inc.

   Contributed by the Center for Software Science at the

   Contributed by the Center for Software Science at the

   University of Utah (pa-gdb-bugs@cs.utah.edu).

   University of Utah (pa-gdb-bugs@cs.utah.edu).

This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.

This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.

GAS/GDB is free software; you can redistribute it and/or modify

GAS/GDB is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 1, or (at your option)

the Free Software Foundation; either version 1, or (at your option)

any later version.

any later version.

GAS/GDB is distributed in the hope that it will be useful,

GAS/GDB is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

You should have received a copy of the GNU General Public License

along with GAS or GDB; see the file COPYING.  If not, write to

along with GAS or GDB; see the file COPYING.  If not, write to

the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#if !defined(__STDC__) && !defined(const)

#if !defined(__STDC__) && !defined(const)

#define const

#define const

#endif

#endif

/*

/*

 * Structure of an opcode table entry.

 * Structure of an opcode table entry.

 */

 */

/* There are two kinds of delay slot nullification: normal which is

/* There are two kinds of delay slot nullification: normal which is

 * controled by the nullification bit, and conditional, which depends

 * controled by the nullification bit, and conditional, which depends

 * on the direction of the branch and its success or failure.

 * on the direction of the branch and its success or failure.

 *

 *

 * NONE is unfortunately #defined in the hiux system include files.

 * NONE is unfortunately #defined in the hiux system include files.

 * #undef it away.

 * #undef it away.

 */

 */

#undef NONE

#undef NONE

struct pa_opcode

struct pa_opcode

{

{

    const char *name;

    const char *name;

    unsigned long int match;    /* Bits that must be set...  */

    unsigned long int match;    /* Bits that must be set...  */

    unsigned long int mask;     /* ... in these bits. */

    unsigned long int mask;     /* ... in these bits. */

    char *args;

    char *args;

    enum pa_arch arch;

    enum pa_arch arch;

    char flags;

    char flags;

};

};

/* Enables strict matching.  Opcodes with match errors are skipped

/* Enables strict matching.  Opcodes with match errors are skipped

   when this bit is set.  */

   when this bit is set.  */

#define FLAG_STRICT 0x1

#define FLAG_STRICT 0x1

/*

/*

   All hppa opcodes are 32 bits.

   All hppa opcodes are 32 bits.

   The match component is a mask saying which bits must match a

   The match component is a mask saying which bits must match a

   particular opcode in order for an instruction to be an instance

   particular opcode in order for an instruction to be an instance

   of that opcode.

   of that opcode.

   The args component is a string containing one character for each operand of

   The args component is a string containing one character for each operand of

   the instruction.  Characters used as a prefix allow any second character to

   the instruction.  Characters used as a prefix allow any second character to

   be used without conflicting with the main operand characters.

   be used without conflicting with the main operand characters.

   Bit positions in this description follow HP usage of lsb = 31,

   Bit positions in this description follow HP usage of lsb = 31,

   "at" is lsb of field.

   "at" is lsb of field.

   In the args field, the following characters must match exactly:

   In the args field, the following characters must match exactly:

        '+,() '

        '+,() '

   In the args field, the following characters are unused:

   In the args field, the following characters are unused:

        '  "         -  /   34 6789:;    '

        '  "         -  /   34 6789:;    '

        '@  C         M             [\]  '

        '@  C         M             [\]  '

        '`    e g                     }  '

        '`    e g                     }  '

   Here are all the characters:

   Here are all the characters:

        ' !"#$%&'()*+-,./0123456789:;<=>?'

        ' !"#$%&'()*+-,./0123456789:;<=>?'

        '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'

        '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'

        '`abcdefghijklmnopqrstuvwxyz{|}~ '

        '`abcdefghijklmnopqrstuvwxyz{|}~ '

Kinds of operands:

Kinds of operands:

   x    integer register field at 15.

   x    integer register field at 15.

   b    integer register field at 10.

   b    integer register field at 10.

   t    integer register field at 31.

   t    integer register field at 31.

   a    integer register field at 10 and 15 (for PERMH)

   a    integer register field at 10 and 15 (for PERMH)

   5    5 bit immediate at 15.

   5    5 bit immediate at 15.

   s    2 bit space specifier at 17.

   s    2 bit space specifier at 17.

   S    3 bit space specifier at 18.

   S    3 bit space specifier at 18.

   V    5 bit immediate value at 31

   V    5 bit immediate value at 31

   i    11 bit immediate value at 31

   i    11 bit immediate value at 31

   j    14 bit immediate value at 31

   j    14 bit immediate value at 31

   k    21 bit immediate value at 31

   k    21 bit immediate value at 31

   l    16 bit immediate value at 31 (wide mode only, unusual encoding).

   l    16 bit immediate value at 31 (wide mode only, unusual encoding).

   n    nullification for branch instructions

   n    nullification for branch instructions

   N    nullification for spop and copr instructions

   N    nullification for spop and copr instructions

   w    12 bit branch displacement

   w    12 bit branch displacement

   W    17 bit branch displacement (PC relative)

   W    17 bit branch displacement (PC relative)

   X    22 bit branch displacement (PC relative)

   X    22 bit branch displacement (PC relative)

   z    17 bit branch displacement (just a number, not an address)

   z    17 bit branch displacement (just a number, not an address)

Also these:

Also these:

   .    2 bit shift amount at 25

   .    2 bit shift amount at 25

   *    4 bit shift amount at 25

   *    4 bit shift amount at 25

   p    5 bit shift count at 26 (to support the SHD instruction) encoded as

   p    5 bit shift count at 26 (to support the SHD instruction) encoded as

        31-p

        31-p

   ~    6 bit shift count at 20,22:26 encoded as 63-~.

   ~    6 bit shift count at 20,22:26 encoded as 63-~.

   P    5 bit bit position at 26

   P    5 bit bit position at 26

   q    6 bit bit position at 20,22:26

   q    6 bit bit position at 20,22:26

   T    5 bit field length at 31 (encoded as 32-T)

   T    5 bit field length at 31 (encoded as 32-T)

   %    6 bit field length at 23,27:31 (variable extract/deposit)

   %    6 bit field length at 23,27:31 (variable extract/deposit)

   |    6 bit field length at 19,27:31 (fixed extract/deposit)

   |    6 bit field length at 19,27:31 (fixed extract/deposit)

   A    13 bit immediate at 18 (to support the BREAK instruction)

   A    13 bit immediate at 18 (to support the BREAK instruction)

   ^    like b, but describes a control register

   ^    like b, but describes a control register

   !    sar (cr11) register

   !    sar (cr11) register

   D    26 bit immediate at 31 (to support the DIAG instruction)

   D    26 bit immediate at 31 (to support the DIAG instruction)

   $    9 bit immediate at 28 (to support POPBTS)

   $    9 bit immediate at 28 (to support POPBTS)

   v    3 bit Special Function Unit identifier at 25

   v    3 bit Special Function Unit identifier at 25

   O    20 bit Special Function Unit operation split between 15 bits at 20

   O    20 bit Special Function Unit operation split between 15 bits at 20

        and 5 bits at 31

        and 5 bits at 31

   o    15 bit Special Function Unit operation at 20

   o    15 bit Special Function Unit operation at 20

   2    22 bit Special Function Unit operation split between 17 bits at 20

   2    22 bit Special Function Unit operation split between 17 bits at 20

        and 5 bits at 31

        and 5 bits at 31

   1    15 bit Special Function Unit operation split between 10 bits at 20

   1    15 bit Special Function Unit operation split between 10 bits at 20

        and 5 bits at 31

        and 5 bits at 31

   0    10 bit Special Function Unit operation split between 5 bits at 20

   0    10 bit Special Function Unit operation split between 5 bits at 20

        and 5 bits at 31

        and 5 bits at 31

   u    3 bit coprocessor unit identifier at 25

   u    3 bit coprocessor unit identifier at 25

   F    Source Floating Point Operand Format Completer encoded 2 bits at 20

   F    Source Floating Point Operand Format Completer encoded 2 bits at 20

   I    Source Floating Point Operand Format Completer encoded 1 bits at 20

   I    Source Floating Point Operand Format Completer encoded 1 bits at 20

        (for 0xe format FP instructions)

        (for 0xe format FP instructions)

   G    Destination Floating Point Operand Format Completer encoded 2 bits at 18

   G    Destination Floating Point Operand Format Completer encoded 2 bits at 18

   H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'

   H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'

        (very similar to 'F')

        (very similar to 'F')

   r    5 bit immediate value at 31 (for the break instruction)

   r    5 bit immediate value at 31 (for the break instruction)

        (very similar to V above, except the value is unsigned instead of

        (very similar to V above, except the value is unsigned instead of

        low_sign_ext)

        low_sign_ext)

   R    5 bit immediate value at 15 (for the ssm, rsm, probei instructions)

   R    5 bit immediate value at 15 (for the ssm, rsm, probei instructions)

        (same as r above, except the value is in a different location)

        (same as r above, except the value is in a different location)

   U    10 bit immediate value at 15 (for SSM, RSM on pa2.0)

   U    10 bit immediate value at 15 (for SSM, RSM on pa2.0)

   Q    5 bit immediate value at 10 (a bit position specified in

   Q    5 bit immediate value at 10 (a bit position specified in

        the bb instruction. It's the same as r above, except the

        the bb instruction. It's the same as r above, except the

        value is in a different location)

        value is in a different location)

   B    5 bit immediate value at 10 (a bit position specified in

   B    5 bit immediate value at 10 (a bit position specified in

        the bb instruction. Similar to Q, but 64 bit handling is

        the bb instruction. Similar to Q, but 64 bit handling is

        different.

        different.

   Z    %r1 -- implicit target of addil instruction.

   Z    %r1 -- implicit target of addil instruction.

   L    ,%r2 completer for new syntax branch

   L    ,%r2 completer for new syntax branch

   {    Source format completer for fcnv

   {    Source format completer for fcnv

   _    Destination format completer for fcnv

   _    Destination format completer for fcnv

   h    cbit for fcmp

   h    cbit for fcmp

   =    gfx tests for ftest

   =    gfx tests for ftest

   d    14 bit offset for single precision FP long load/store.

   d    14 bit offset for single precision FP long load/store.

   #    14 bit offset for double precision FP load long/store.

   #    14 bit offset for double precision FP load long/store.

   J    Yet another 14 bit offset for load/store with ma,mb completers.

   J    Yet another 14 bit offset for load/store with ma,mb completers.

   K    Yet another 14 bit offset for load/store with ma,mb completers.

   K    Yet another 14 bit offset for load/store with ma,mb completers.

   y    16 bit offset for word aligned load/store (PA2.0 wide).

   y    16 bit offset for word aligned load/store (PA2.0 wide).

   &    16 bit offset for dword aligned load/store (PA2.0 wide).

   &    16 bit offset for dword aligned load/store (PA2.0 wide).

   <    16 bit offset for load/store with ma,mb completers (PA2.0 wide).

   <    16 bit offset for load/store with ma,mb completers (PA2.0 wide).

   >    16 bit offset for load/store with ma,mb completers (PA2.0 wide).

   >    16 bit offset for load/store with ma,mb completers (PA2.0 wide).

   Y    %sr0,%r31 -- implicit target of be,l instruction.

   Y    %sr0,%r31 -- implicit target of be,l instruction.

   @    implicit immediate value of 0

   @    implicit immediate value of 0

Completer operands all have 'c' as the prefix:

Completer operands all have 'c' as the prefix:

   cx   indexed load and store completer.

   cx   indexed load and store completer.

   cX   indexed load and store completer.  Like cx, but emits a space

   cX   indexed load and store completer.  Like cx, but emits a space

        after in disassembler.

        after in disassembler.

   cm   short load and store completer.

   cm   short load and store completer.

   cM   short load and store completer.  Like cm, but emits a space

   cM   short load and store completer.  Like cm, but emits a space

        after in disassembler.

        after in disassembler.

   cq   long load and store completer (like cm, but inserted into a

   cq   long load and store completer (like cm, but inserted into a

        different location in the target instruction).

        different location in the target instruction).

   cs   store bytes short completer.

   cs   store bytes short completer.

   cA   store bytes short completer.  Like cs, but emits a space

   cA   store bytes short completer.  Like cs, but emits a space

        after in disassembler.

        after in disassembler.

   ce   long load/store completer for LDW/STW with a different encoding

   ce   long load/store completer for LDW/STW with a different encoding

        than the others

        than the others

   cc   load cache control hint

   cc   load cache control hint

   cd   load and clear cache control hint

   cd   load and clear cache control hint

   cC   store cache control hint

   cC   store cache control hint

   co   ordered access

   co   ordered access

   cp   branch link and push completer

   cp   branch link and push completer

   cP   branch pop completer

   cP   branch pop completer

   cl   branch link completer

   cl   branch link completer

   cg   branch gate completer

   cg   branch gate completer

   cw   read/write completer for PROBE

   cw   read/write completer for PROBE

   cW   wide completer for MFCTL

   cW   wide completer for MFCTL

   cL   local processor completer for cache control

   cL   local processor completer for cache control

   cZ   System Control Completer (to support LPA, LHA, etc.)

   cZ   System Control Completer (to support LPA, LHA, etc.)

   ci   correction completer for DCOR

   ci   correction completer for DCOR

   ca   add completer

   ca   add completer

   cy   32 bit add carry completer

   cy   32 bit add carry completer

   cY   64 bit add carry completer

   cY   64 bit add carry completer

   cv   signed overflow trap completer

   cv   signed overflow trap completer

   ct   trap on condition completer for ADDI, SUB

   ct   trap on condition completer for ADDI, SUB

   cT   trap on condition completer for UADDCM

   cT   trap on condition completer for UADDCM

   cb   32 bit borrow completer for SUB

   cb   32 bit borrow completer for SUB

   cB   64 bit borrow completer for SUB

   cB   64 bit borrow completer for SUB

   ch   left/right half completer

   ch   left/right half completer

   cH   signed/unsigned saturation completer

   cH   signed/unsigned saturation completer

   cS   signed/unsigned completer at 21

   cS   signed/unsigned completer at 21

   cz   zero/sign extension completer.

   cz   zero/sign extension completer.

   c*   permutation completer

   c*   permutation completer

Condition operands all have '?' as the prefix:

Condition operands all have '?' as the prefix:

   ?f   Floating point compare conditions (encoded as 5 bits at 31)

   ?f   Floating point compare conditions (encoded as 5 bits at 31)

   ?a   add conditions

   ?a   add conditions

   ?A   64 bit add conditions

   ?A   64 bit add conditions

   ?@   add branch conditions followed by nullify

   ?@   add branch conditions followed by nullify

   ?d   non-negated add branch conditions

   ?d   non-negated add branch conditions

   ?D   negated add branch conditions

   ?D   negated add branch conditions

   ?w   wide mode non-negated add branch conditions

   ?w   wide mode non-negated add branch conditions

   ?W   wide mode negated add branch conditions

   ?W   wide mode negated add branch conditions

   ?s   compare/subtract conditions

   ?s   compare/subtract conditions

   ?S   64 bit compare/subtract conditions

   ?S   64 bit compare/subtract conditions

   ?t   non-negated compare and branch conditions

   ?t   non-negated compare and branch conditions

   ?n   32 bit compare and branch conditions followed by nullify

   ?n   32 bit compare and branch conditions followed by nullify

   ?N   64 bit compare and branch conditions followed by nullify

   ?N   64 bit compare and branch conditions followed by nullify

   ?Q   64 bit compare and branch conditions for CMPIB instruction

   ?Q   64 bit compare and branch conditions for CMPIB instruction

   ?l   logical conditions

   ?l   logical conditions

   ?L   64 bit logical conditions

   ?L   64 bit logical conditions

   ?b   branch on bit conditions

   ?b   branch on bit conditions

   ?B   64 bit branch on bit conditions

   ?B   64 bit branch on bit conditions

   ?x   shift/extract/deposit conditions

   ?x   shift/extract/deposit conditions

   ?X   64 bit shift/extract/deposit conditions

   ?X   64 bit shift/extract/deposit conditions

   ?y   shift/extract/deposit conditions followed by nullify for conditional

   ?y   shift/extract/deposit conditions followed by nullify for conditional

        branches

        branches

   ?u   unit conditions

   ?u   unit conditions

   ?U   64 bit unit conditions

   ?U   64 bit unit conditions

Floating point registers all have 'f' as a prefix:

Floating point registers all have 'f' as a prefix:

   ft   target register at 31

   ft   target register at 31

   fT   target register with L/R halves at 31

   fT   target register with L/R halves at 31

   fa   operand 1 register at 10

   fa   operand 1 register at 10

   fA   operand 1 register with L/R halves at 10

   fA   operand 1 register with L/R halves at 10

   fX   Same as fA, except prints a space before register during disasm

   fX   Same as fA, except prints a space before register during disasm

   fb   operand 2 register at 15

   fb   operand 2 register at 15

   fB   operand 2 register with L/R halves at 15

   fB   operand 2 register with L/R halves at 15

   fC   operand 3 register with L/R halves at 16:18,21:23

   fC   operand 3 register with L/R halves at 16:18,21:23

   fe   Like fT, but encoding is different.

   fe   Like fT, but encoding is different.

   fE   Same as fe, except prints a space before register during disasm.

   fE   Same as fe, except prints a space before register during disasm.

   fx   target register at 15 (only for PA 2.0 long format FLDD/FSTD).

   fx   target register at 15 (only for PA 2.0 long format FLDD/FSTD).

Float registers for fmpyadd and fmpysub:

Float registers for fmpyadd and fmpysub:

   fi   mult operand 1 register at 10

   fi   mult operand 1 register at 10

   fj   mult operand 2 register at 15

   fj   mult operand 2 register at 15

   fk   mult target register at 20

   fk   mult target register at 20

   fl   add/sub operand register at 25

   fl   add/sub operand register at 25

   fm   add/sub target register at 31

   fm   add/sub target register at 31

*/

*/

#if 0

#if 0

/* List of characters not to put a space after.  Note that

/* List of characters not to put a space after.  Note that

   "," is included, as the "spopN" operations use literal

   "," is included, as the "spopN" operations use literal

   commas in their completer sections.  */

   commas in their completer sections.  */

static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";

static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";

#endif

#endif

/* The order of the opcodes in this table is significant:

/* The order of the opcodes in this table is significant:

   * The assembler requires that all instances of the same mnemonic be

   * The assembler requires that all instances of the same mnemonic be

     consecutive.  If they aren't, the assembler will bomb at runtime.

     consecutive.  If they aren't, the assembler will bomb at runtime.

   * Immediate fields use pa_get_absolute_expression to parse the

   * Immediate fields use pa_get_absolute_expression to parse the

     string.  It will generate a "bad expression" error if passed

     string.  It will generate a "bad expression" error if passed

     a register name.  Thus, register index variants of an opcode

     a register name.  Thus, register index variants of an opcode

     need to precede immediate variants.

     need to precede immediate variants.

   * The disassembler does not care about the order of the opcodes

   * The disassembler does not care about the order of the opcodes

     except in cases where implicit addressing is used.

     except in cases where implicit addressing is used.

   Here are the rules for ordering the opcodes of a mnemonic:

   Here are the rules for ordering the opcodes of a mnemonic:

   1) Opcodes with FLAG_STRICT should precede opcodes without

   1) Opcodes with FLAG_STRICT should precede opcodes without

      FLAG_STRICT.

      FLAG_STRICT.

   2) Opcodes with FLAG_STRICT should be ordered as follows:

   2) Opcodes with FLAG_STRICT should be ordered as follows:

      register index opcodes, short immediate opcodes, and finally

      register index opcodes, short immediate opcodes, and finally

      long immediate opcodes.  When both pa10 and pa11 variants

      long immediate opcodes.  When both pa10 and pa11 variants

      of the same opcode are available, the pa10 opcode should

      of the same opcode are available, the pa10 opcode should

      come first for correct architectural promotion.

      come first for correct architectural promotion.

   3) When implicit addressing is available for an opcode, the

   3) When implicit addressing is available for an opcode, the

      implicit opcode should precede the explicit opcode.

      implicit opcode should precede the explicit opcode.

   4) Opcodes without FLAG_STRICT should be ordered as follows:

   4) Opcodes without FLAG_STRICT should be ordered as follows:

      register index opcodes, long immediate opcodes, and finally

      register index opcodes, long immediate opcodes, and finally

      short immediate opcodes.  */

      short immediate opcodes.  */

static const struct pa_opcode pa_opcodes[] =

static const struct pa_opcode pa_opcodes[] =

{

{

/* Pseudo-instructions.  */

/* Pseudo-instructions.  */

{ "ldi",        0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */

{ "ldi",        0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */

{ "ldi",        0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */

{ "ldi",        0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */

{ "cmpib",      0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},

{ "cmpib",      0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},

{ "cmpib",      0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT},

{ "cmpib",      0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT},

{ "comib",      0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/

{ "comib",      0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/

/* This entry is for the disassembler only.  It will never be used by

/* This entry is for the disassembler only.  It will never be used by

   assembler.  */

   assembler.  */

{ "comib",      0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/

{ "comib",      0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/

{ "cmpb",       0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT},

{ "cmpb",       0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT},

{ "cmpb",       0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT},

{ "cmpb",       0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT},

{ "comb",       0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */

{ "comb",       0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */

/* This entry is for the disassembler only.  It will never be used by

/* This entry is for the disassembler only.  It will never be used by

   assembler.  */

   assembler.  */

{ "comb",       0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */

{ "comb",       0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */

{ "addb",       0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT},

{ "addb",       0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT},

{ "addb",       0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */

{ "addb",       0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */

/* This entry is for the disassembler only.  It will never be used by

/* This entry is for the disassembler only.  It will never be used by

   assembler.  */

   assembler.  */

{ "addb",       0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},

{ "addb",       0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},

{ "addib",      0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT},

{ "addib",      0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT},

{ "addib",      0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/

{ "addib",      0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/

/* This entry is for the disassembler only.  It will never be used by

/* This entry is for the disassembler only.  It will never be used by

   assembler.  */

   assembler.  */

{ "addib",      0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/

{ "addib",      0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/

{ "nop",        0x08000240, 0xffffffff, "", pa10, 0},      /* or 0,0,0 */

{ "nop",        0x08000240, 0xffffffff, "", pa10, 0},      /* or 0,0,0 */

{ "copy",       0x08000240, 0xffe0ffe0, "x,t", pa10, 0},   /* or r,0,t */

{ "copy",       0x08000240, 0xffe0ffe0, "x,t", pa10, 0},   /* or r,0,t */

{ "mtsar",      0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */

{ "mtsar",      0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */

/* Loads and Stores for integer registers.  */

/* Loads and Stores for integer registers.  */

{ "ldd",        0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT},

{ "ldd",        0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT},

{ "ldd",        0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT},

{ "ldd",        0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT},

{ "ldd",        0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT},

{ "ldd",        0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},

{ "ldd",        0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldw",        0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldw",        0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldw",        0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldw",        0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT},

{ "ldw",        0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT},

{ "ldw",        0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT},

{ "ldw",        0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT},

{ "ldw",        0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},

{ "ldw",        0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},

{ "ldw",        0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT},

{ "ldw",        0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT},

{ "ldw",        0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT},

{ "ldw",        0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT},

{ "ldw",        0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, FLAG_STRICT},

{ "ldw",        0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, FLAG_STRICT},

{ "ldw",        0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT},

{ "ldw",        0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT},

{ "ldw",        0x48000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldw",        0x48000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "ldh",        0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldh",        0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldh",        0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldh",        0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldh",        0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},

{ "ldh",        0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},

{ "ldh",        0x44000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldh",        0x44000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "ldb",        0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldb",        0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldb",        0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldb",        0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldb",        0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},

{ "ldb",        0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},

{ "ldb",        0x40000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldb",        0x40000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "std",        0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},

{ "std",        0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT},

{ "std",        0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT},

{ "std",        0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT},

{ "std",        0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT},

{ "std",        0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},

{ "std",        0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},

{ "stw",        0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "stw",        0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "stw",        0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "stw",        0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},

{ "stw",        0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT},

{ "stw",        0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT},

{ "stw",        0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT},

{ "stw",        0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT},

{ "stw",        0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},

{ "stw",        0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},

{ "stw",        0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT},

{ "stw",        0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT},

{ "stw",        0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT},

{ "stw",        0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT},

{ "stw",        0x6c000000, 0xfc00c000, "cex,J(b)", pa10, FLAG_STRICT},

{ "stw",        0x6c000000, 0xfc00c000, "cex,J(b)", pa10, FLAG_STRICT},

{ "stw",        0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT},

{ "stw",        0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT},

{ "stw",        0x68000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "stw",        0x68000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "sth",        0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "sth",        0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "sth",        0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "sth",        0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},

{ "sth",        0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},

{ "sth",        0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},

{ "sth",        0x64000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "sth",        0x64000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "stb",        0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "stb",        0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "stb",        0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "stb",        0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},

{ "stb",        0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},

{ "stb",        0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},

{ "stb",        0x60000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "stb",        0x60000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "ldwm",       0x4c000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldwm",       0x4c000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "stwm",       0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "stwm",       0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "ldwx",       0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldwx",       0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldwx",       0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldwx",       0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldwx",       0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldwx",       0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldwx",       0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldwx",       0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldwx",       0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0},

{ "ldwx",       0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0},

{ "ldwx",       0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},

{ "ldwx",       0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},

{ "ldhx",       0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldhx",       0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldhx",       0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldhx",       0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldhx",       0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldhx",       0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldhx",       0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldhx",       0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldhx",       0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0},

{ "ldhx",       0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0},

{ "ldhx",       0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},

{ "ldhx",       0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},

{ "ldbx",       0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldbx",       0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldbx",       0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldbx",       0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldbx",       0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},