/* Opcode table for TI TMS320C80 (MVP).
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/* Opcode table for TI TMS320C80 (MVP).
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Copyright 1996, 1997, 2000, 2005, 2007 Free Software Foundation, Inc.
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Copyright 1996, 1997, 2000, 2005, 2007 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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MA 02110-1301, USA. */
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#include <stdio.h>
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#include <stdio.h>
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#include "sysdep.h"
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#include "sysdep.h"
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#include "opcode/tic80.h"
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#include "opcode/tic80.h"
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/* This file holds various tables for the TMS320C80 (MVP).
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/* This file holds various tables for the TMS320C80 (MVP).
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The opcode table is strictly constant data, so the compiler should
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The opcode table is strictly constant data, so the compiler should
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be able to put it in the .text section.
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be able to put it in the .text section.
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This file also holds the operand table. All knowledge about
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This file also holds the operand table. All knowledge about
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inserting operands into instructions and vice-versa is kept in this
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inserting operands into instructions and vice-versa is kept in this
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file.
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file.
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The predefined register table maps from register names to register
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The predefined register table maps from register names to register
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values. */
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values. */
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/* Table of predefined symbol names, such as general purpose registers,
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/* Table of predefined symbol names, such as general purpose registers,
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floating point registers, condition codes, control registers, and bit
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floating point registers, condition codes, control registers, and bit
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numbers.
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numbers.
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The table is sorted case independently by name so that it is suitable for
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The table is sorted case independently by name so that it is suitable for
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searching via a binary search using a case independent comparison
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searching via a binary search using a case independent comparison
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function.
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function.
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Note that the type of the symbol is stored in the upper bits of the value
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Note that the type of the symbol is stored in the upper bits of the value
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field, which allows the value and type to be passed around as a unit in a
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field, which allows the value and type to be passed around as a unit in a
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single int. The types have to be masked off before using the numeric
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single int. The types have to be masked off before using the numeric
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value as a number.
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value as a number.
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*/
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*/
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const struct predefined_symbol tic80_predefined_symbols[] =
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const struct predefined_symbol tic80_predefined_symbols[] =
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{
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{
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{ "a0", TIC80_OPERAND_FPA | 0 },
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{ "a0", TIC80_OPERAND_FPA | 0 },
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{ "a1", TIC80_OPERAND_FPA | 1 },
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{ "a1", TIC80_OPERAND_FPA | 1 },
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{ "alw.b", TIC80_OPERAND_CC | 7 },
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{ "alw.b", TIC80_OPERAND_CC | 7 },
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{ "alw.h", TIC80_OPERAND_CC | 15 },
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{ "alw.h", TIC80_OPERAND_CC | 15 },
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{ "alw.w", TIC80_OPERAND_CC | 23 },
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{ "alw.w", TIC80_OPERAND_CC | 23 },
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{ "ANASTAT", TIC80_OPERAND_CR | 0x34 },
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{ "ANASTAT", TIC80_OPERAND_CR | 0x34 },
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{ "BRK1", TIC80_OPERAND_CR | 0x39 },
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{ "BRK1", TIC80_OPERAND_CR | 0x39 },
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{ "BRK2", TIC80_OPERAND_CR | 0x3A },
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{ "BRK2", TIC80_OPERAND_CR | 0x3A },
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{ "CONFIG", TIC80_OPERAND_CR | 2 },
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{ "CONFIG", TIC80_OPERAND_CR | 2 },
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{ "DLRU", TIC80_OPERAND_CR | 0x500 },
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{ "DLRU", TIC80_OPERAND_CR | 0x500 },
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{ "DTAG0", TIC80_OPERAND_CR | 0x400 },
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{ "DTAG0", TIC80_OPERAND_CR | 0x400 },
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{ "DTAG1", TIC80_OPERAND_CR | 0x401 },
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{ "DTAG1", TIC80_OPERAND_CR | 0x401 },
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{ "DTAG10", TIC80_OPERAND_CR | 0x40A },
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{ "DTAG10", TIC80_OPERAND_CR | 0x40A },
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{ "DTAG11", TIC80_OPERAND_CR | 0x40B },
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{ "DTAG11", TIC80_OPERAND_CR | 0x40B },
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{ "DTAG12", TIC80_OPERAND_CR | 0x40C },
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{ "DTAG12", TIC80_OPERAND_CR | 0x40C },
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{ "DTAG13", TIC80_OPERAND_CR | 0x40D },
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{ "DTAG13", TIC80_OPERAND_CR | 0x40D },
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{ "DTAG14", TIC80_OPERAND_CR | 0x40E },
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{ "DTAG14", TIC80_OPERAND_CR | 0x40E },
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{ "DTAG15", TIC80_OPERAND_CR | 0x40F },
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{ "DTAG15", TIC80_OPERAND_CR | 0x40F },
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{ "DTAG2", TIC80_OPERAND_CR | 0x402 },
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{ "DTAG2", TIC80_OPERAND_CR | 0x402 },
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{ "DTAG3", TIC80_OPERAND_CR | 0x403 },
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{ "DTAG3", TIC80_OPERAND_CR | 0x403 },
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{ "DTAG4", TIC80_OPERAND_CR | 0x404 },
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{ "DTAG4", TIC80_OPERAND_CR | 0x404 },
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{ "DTAG5", TIC80_OPERAND_CR | 0x405 },
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{ "DTAG5", TIC80_OPERAND_CR | 0x405 },
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{ "DTAG6", TIC80_OPERAND_CR | 0x406 },
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{ "DTAG6", TIC80_OPERAND_CR | 0x406 },
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{ "DTAG7", TIC80_OPERAND_CR | 0x407 },
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{ "DTAG7", TIC80_OPERAND_CR | 0x407 },
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{ "DTAG8", TIC80_OPERAND_CR | 0x408 },
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{ "DTAG8", TIC80_OPERAND_CR | 0x408 },
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{ "DTAG9", TIC80_OPERAND_CR | 0x409 },
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{ "DTAG9", TIC80_OPERAND_CR | 0x409 },
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{ "ECOMCNTL", TIC80_OPERAND_CR | 0x33 },
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{ "ECOMCNTL", TIC80_OPERAND_CR | 0x33 },
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{ "EIP", TIC80_OPERAND_CR | 1 },
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{ "EIP", TIC80_OPERAND_CR | 1 },
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{ "EPC", TIC80_OPERAND_CR | 0 },
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{ "EPC", TIC80_OPERAND_CR | 0 },
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{ "eq.b", TIC80_OPERAND_BITNUM | 0 },
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{ "eq.b", TIC80_OPERAND_BITNUM | 0 },
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{ "eq.f", TIC80_OPERAND_BITNUM | 20 },
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{ "eq.f", TIC80_OPERAND_BITNUM | 20 },
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{ "eq.h", TIC80_OPERAND_BITNUM | 10 },
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{ "eq.h", TIC80_OPERAND_BITNUM | 10 },
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{ "eq.w", TIC80_OPERAND_BITNUM | 20 },
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{ "eq.w", TIC80_OPERAND_BITNUM | 20 },
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{ "eq0.b", TIC80_OPERAND_CC | 2 },
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{ "eq0.b", TIC80_OPERAND_CC | 2 },
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{ "eq0.h", TIC80_OPERAND_CC | 10 },
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{ "eq0.h", TIC80_OPERAND_CC | 10 },
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{ "eq0.w", TIC80_OPERAND_CC | 18 },
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{ "eq0.w", TIC80_OPERAND_CC | 18 },
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{ "FLTADR", TIC80_OPERAND_CR | 0x11 },
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{ "FLTADR", TIC80_OPERAND_CR | 0x11 },
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{ "FLTDTH", TIC80_OPERAND_CR | 0x14 },
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{ "FLTDTH", TIC80_OPERAND_CR | 0x14 },
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{ "FLTDTL", TIC80_OPERAND_CR | 0x13 },
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{ "FLTDTL", TIC80_OPERAND_CR | 0x13 },
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{ "FLTOP", TIC80_OPERAND_CR | 0x10 },
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{ "FLTOP", TIC80_OPERAND_CR | 0x10 },
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{ "FLTTAG", TIC80_OPERAND_CR | 0x12 },
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{ "FLTTAG", TIC80_OPERAND_CR | 0x12 },
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{ "FPST", TIC80_OPERAND_CR | 8 },
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{ "FPST", TIC80_OPERAND_CR | 8 },
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{ "ge.b", TIC80_OPERAND_BITNUM | 5 },
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{ "ge.b", TIC80_OPERAND_BITNUM | 5 },
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{ "ge.f", TIC80_OPERAND_BITNUM | 25 },
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{ "ge.f", TIC80_OPERAND_BITNUM | 25 },
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{ "ge.h", TIC80_OPERAND_BITNUM | 15 },
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{ "ge.h", TIC80_OPERAND_BITNUM | 15 },
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{ "ge.w", TIC80_OPERAND_BITNUM | 25 },
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{ "ge.w", TIC80_OPERAND_BITNUM | 25 },
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{ "ge0.b", TIC80_OPERAND_CC | 3 },
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{ "ge0.b", TIC80_OPERAND_CC | 3 },
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{ "ge0.h", TIC80_OPERAND_CC | 11 },
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{ "ge0.h", TIC80_OPERAND_CC | 11 },
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{ "ge0.w", TIC80_OPERAND_CC | 19 },
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{ "ge0.w", TIC80_OPERAND_CC | 19 },
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{ "gt.b", TIC80_OPERAND_BITNUM | 2 },
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{ "gt.b", TIC80_OPERAND_BITNUM | 2 },
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{ "gt.f", TIC80_OPERAND_BITNUM | 22 },
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{ "gt.f", TIC80_OPERAND_BITNUM | 22 },
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{ "gt.h", TIC80_OPERAND_BITNUM | 12 },
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{ "gt.h", TIC80_OPERAND_BITNUM | 12 },
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{ "gt.w", TIC80_OPERAND_BITNUM | 22 },
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{ "gt.w", TIC80_OPERAND_BITNUM | 22 },
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{ "gt0.b", TIC80_OPERAND_CC | 1 },
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{ "gt0.b", TIC80_OPERAND_CC | 1 },
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{ "gt0.h", TIC80_OPERAND_CC | 9 },
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{ "gt0.h", TIC80_OPERAND_CC | 9 },
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{ "gt0.w", TIC80_OPERAND_CC | 17 },
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{ "gt0.w", TIC80_OPERAND_CC | 17 },
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{ "hi.b", TIC80_OPERAND_BITNUM | 6 },
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{ "hi.b", TIC80_OPERAND_BITNUM | 6 },
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{ "hi.h", TIC80_OPERAND_BITNUM | 16 },
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{ "hi.h", TIC80_OPERAND_BITNUM | 16 },
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{ "hi.w", TIC80_OPERAND_BITNUM | 26 },
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{ "hi.w", TIC80_OPERAND_BITNUM | 26 },
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{ "hs.b", TIC80_OPERAND_BITNUM | 9 },
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{ "hs.b", TIC80_OPERAND_BITNUM | 9 },
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{ "hs.h", TIC80_OPERAND_BITNUM | 19 },
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{ "hs.h", TIC80_OPERAND_BITNUM | 19 },
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{ "hs.w", TIC80_OPERAND_BITNUM | 29 },
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{ "hs.w", TIC80_OPERAND_BITNUM | 29 },
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{ "ib.f", TIC80_OPERAND_BITNUM | 28 },
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{ "ib.f", TIC80_OPERAND_BITNUM | 28 },
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{ "IE", TIC80_OPERAND_CR | 6 },
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{ "IE", TIC80_OPERAND_CR | 6 },
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{ "ILRU", TIC80_OPERAND_CR | 0x300 },
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{ "ILRU", TIC80_OPERAND_CR | 0x300 },
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{ "in.f", TIC80_OPERAND_BITNUM | 27 },
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{ "in.f", TIC80_OPERAND_BITNUM | 27 },
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{ "IN0P", TIC80_OPERAND_CR | 0x4000 },
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{ "IN0P", TIC80_OPERAND_CR | 0x4000 },
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{ "IN1P", TIC80_OPERAND_CR | 0x4001 },
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{ "IN1P", TIC80_OPERAND_CR | 0x4001 },
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{ "INTPEN", TIC80_OPERAND_CR | 4 },
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{ "INTPEN", TIC80_OPERAND_CR | 4 },
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{ "ITAG0", TIC80_OPERAND_CR | 0x200 },
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{ "ITAG0", TIC80_OPERAND_CR | 0x200 },
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{ "ITAG1", TIC80_OPERAND_CR | 0x201 },
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{ "ITAG1", TIC80_OPERAND_CR | 0x201 },
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{ "ITAG10", TIC80_OPERAND_CR | 0x20A },
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{ "ITAG10", TIC80_OPERAND_CR | 0x20A },
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{ "ITAG11", TIC80_OPERAND_CR | 0x20B },
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{ "ITAG11", TIC80_OPERAND_CR | 0x20B },
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{ "ITAG12", TIC80_OPERAND_CR | 0x20C },
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{ "ITAG12", TIC80_OPERAND_CR | 0x20C },
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{ "ITAG13", TIC80_OPERAND_CR | 0x20D },
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{ "ITAG13", TIC80_OPERAND_CR | 0x20D },
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{ "ITAG14", TIC80_OPERAND_CR | 0x20E },
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{ "ITAG14", TIC80_OPERAND_CR | 0x20E },
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{ "ITAG15", TIC80_OPERAND_CR | 0x20F },
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{ "ITAG15", TIC80_OPERAND_CR | 0x20F },
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{ "ITAG2", TIC80_OPERAND_CR | 0x202 },
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{ "ITAG2", TIC80_OPERAND_CR | 0x202 },
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{ "ITAG3", TIC80_OPERAND_CR | 0x203 },
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{ "ITAG3", TIC80_OPERAND_CR | 0x203 },
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{ "ITAG4", TIC80_OPERAND_CR | 0x204 },
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{ "ITAG4", TIC80_OPERAND_CR | 0x204 },
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{ "ITAG5", TIC80_OPERAND_CR | 0x205 },
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{ "ITAG5", TIC80_OPERAND_CR | 0x205 },
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{ "ITAG6", TIC80_OPERAND_CR | 0x206 },
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{ "ITAG6", TIC80_OPERAND_CR | 0x206 },
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{ "ITAG7", TIC80_OPERAND_CR | 0x207 },
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{ "ITAG7", TIC80_OPERAND_CR | 0x207 },
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{ "ITAG8", TIC80_OPERAND_CR | 0x208 },
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{ "ITAG8", TIC80_OPERAND_CR | 0x208 },
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{ "ITAG9", TIC80_OPERAND_CR | 0x209 },
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{ "ITAG9", TIC80_OPERAND_CR | 0x209 },
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{ "le.b", TIC80_OPERAND_BITNUM | 3 },
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{ "le.b", TIC80_OPERAND_BITNUM | 3 },
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{ "le.f", TIC80_OPERAND_BITNUM | 23 },
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{ "le.f", TIC80_OPERAND_BITNUM | 23 },
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{ "le.h", TIC80_OPERAND_BITNUM | 13 },
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{ "le.h", TIC80_OPERAND_BITNUM | 13 },
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{ "le.w", TIC80_OPERAND_BITNUM | 23 },
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{ "le.w", TIC80_OPERAND_BITNUM | 23 },
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{ "le0.b", TIC80_OPERAND_CC | 6 },
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{ "le0.b", TIC80_OPERAND_CC | 6 },
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{ "le0.h", TIC80_OPERAND_CC | 14 },
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{ "le0.h", TIC80_OPERAND_CC | 14 },
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{ "le0.w", TIC80_OPERAND_CC | 22 },
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{ "le0.w", TIC80_OPERAND_CC | 22 },
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{ "lo.b", TIC80_OPERAND_BITNUM | 8 },
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{ "lo.b", TIC80_OPERAND_BITNUM | 8 },
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{ "lo.h", TIC80_OPERAND_BITNUM | 18 },
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{ "lo.h", TIC80_OPERAND_BITNUM | 18 },
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{ "lo.w", TIC80_OPERAND_BITNUM | 28 },
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{ "lo.w", TIC80_OPERAND_BITNUM | 28 },
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{ "ls.b", TIC80_OPERAND_BITNUM | 7 },
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{ "ls.b", TIC80_OPERAND_BITNUM | 7 },
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{ "ls.h", TIC80_OPERAND_BITNUM | 17 },
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{ "ls.h", TIC80_OPERAND_BITNUM | 17 },
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{ "ls.w", TIC80_OPERAND_BITNUM | 27 },
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{ "ls.w", TIC80_OPERAND_BITNUM | 27 },
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{ "lt.b", TIC80_OPERAND_BITNUM | 4 },
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{ "lt.b", TIC80_OPERAND_BITNUM | 4 },
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{ "lt.f", TIC80_OPERAND_BITNUM | 24 },
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{ "lt.f", TIC80_OPERAND_BITNUM | 24 },
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{ "lt.h", TIC80_OPERAND_BITNUM | 14 },
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{ "lt.h", TIC80_OPERAND_BITNUM | 14 },
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{ "lt.w", TIC80_OPERAND_BITNUM | 24 },
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{ "lt.w", TIC80_OPERAND_BITNUM | 24 },
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{ "lt0.b", TIC80_OPERAND_CC | 4 },
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{ "lt0.b", TIC80_OPERAND_CC | 4 },
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{ "lt0.h", TIC80_OPERAND_CC | 12 },
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{ "lt0.h", TIC80_OPERAND_CC | 12 },
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{ "lt0.w", TIC80_OPERAND_CC | 20 },
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{ "lt0.w", TIC80_OPERAND_CC | 20 },
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{ "MIP", TIC80_OPERAND_CR | 0x31 },
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{ "MIP", TIC80_OPERAND_CR | 0x31 },
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{ "MPC", TIC80_OPERAND_CR | 0x30 },
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{ "MPC", TIC80_OPERAND_CR | 0x30 },
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{ "ne.b", TIC80_OPERAND_BITNUM | 1 },
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{ "ne.b", TIC80_OPERAND_BITNUM | 1 },
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{ "ne.f", TIC80_OPERAND_BITNUM | 21 },
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{ "ne.f", TIC80_OPERAND_BITNUM | 21 },
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{ "ne.h", TIC80_OPERAND_BITNUM | 11 },
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{ "ne.h", TIC80_OPERAND_BITNUM | 11 },
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{ "ne.w", TIC80_OPERAND_BITNUM | 21 },
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{ "ne.w", TIC80_OPERAND_BITNUM | 21 },
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{ "ne0.b", TIC80_OPERAND_CC | 5 },
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{ "ne0.b", TIC80_OPERAND_CC | 5 },
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{ "ne0.h", TIC80_OPERAND_CC | 13 },
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{ "ne0.h", TIC80_OPERAND_CC | 13 },
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{ "ne0.w", TIC80_OPERAND_CC | 21 },
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{ "ne0.w", TIC80_OPERAND_CC | 21 },
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{ "nev.b", TIC80_OPERAND_CC | 0 },
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{ "nev.b", TIC80_OPERAND_CC | 0 },
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{ "nev.h", TIC80_OPERAND_CC | 8 },
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{ "nev.h", TIC80_OPERAND_CC | 8 },
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{ "nev.w", TIC80_OPERAND_CC | 16 },
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{ "nev.w", TIC80_OPERAND_CC | 16 },
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{ "ob.f", TIC80_OPERAND_BITNUM | 29 },
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{ "ob.f", TIC80_OPERAND_BITNUM | 29 },
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{ "or.f", TIC80_OPERAND_BITNUM | 31 },
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{ "or.f", TIC80_OPERAND_BITNUM | 31 },
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{ "ou.f", TIC80_OPERAND_BITNUM | 26 },
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{ "ou.f", TIC80_OPERAND_BITNUM | 26 },
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{ "OUTP", TIC80_OPERAND_CR | 0x4002 },
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{ "OUTP", TIC80_OPERAND_CR | 0x4002 },
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{ "PKTREQ", TIC80_OPERAND_CR | 0xD },
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{ "PKTREQ", TIC80_OPERAND_CR | 0xD },
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{ "PPERROR", TIC80_OPERAND_CR | 0xA },
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{ "PPERROR", TIC80_OPERAND_CR | 0xA },
|
{ "r0", TIC80_OPERAND_GPR | 0 },
|
{ "r0", TIC80_OPERAND_GPR | 0 },
|
{ "r1", TIC80_OPERAND_GPR | 1 },
|
{ "r1", TIC80_OPERAND_GPR | 1 },
|
{ "r10", TIC80_OPERAND_GPR | 10 },
|
{ "r10", TIC80_OPERAND_GPR | 10 },
|
{ "r11", TIC80_OPERAND_GPR | 11 },
|
{ "r11", TIC80_OPERAND_GPR | 11 },
|
{ "r12", TIC80_OPERAND_GPR | 12 },
|
{ "r12", TIC80_OPERAND_GPR | 12 },
|
{ "r13", TIC80_OPERAND_GPR | 13 },
|
{ "r13", TIC80_OPERAND_GPR | 13 },
|
{ "r14", TIC80_OPERAND_GPR | 14 },
|
{ "r14", TIC80_OPERAND_GPR | 14 },
|
{ "r15", TIC80_OPERAND_GPR | 15 },
|
{ "r15", TIC80_OPERAND_GPR | 15 },
|
{ "r16", TIC80_OPERAND_GPR | 16 },
|
{ "r16", TIC80_OPERAND_GPR | 16 },
|
{ "r17", TIC80_OPERAND_GPR | 17 },
|
{ "r17", TIC80_OPERAND_GPR | 17 },
|
{ "r18", TIC80_OPERAND_GPR | 18 },
|
{ "r18", TIC80_OPERAND_GPR | 18 },
|
{ "r19", TIC80_OPERAND_GPR | 19 },
|
{ "r19", TIC80_OPERAND_GPR | 19 },
|
{ "r2", TIC80_OPERAND_GPR | 2 },
|
{ "r2", TIC80_OPERAND_GPR | 2 },
|
{ "r20", TIC80_OPERAND_GPR | 20 },
|
{ "r20", TIC80_OPERAND_GPR | 20 },
|
{ "r21", TIC80_OPERAND_GPR | 21 },
|
{ "r21", TIC80_OPERAND_GPR | 21 },
|
{ "r22", TIC80_OPERAND_GPR | 22 },
|
{ "r22", TIC80_OPERAND_GPR | 22 },
|
{ "r23", TIC80_OPERAND_GPR | 23 },
|
{ "r23", TIC80_OPERAND_GPR | 23 },
|
{ "r24", TIC80_OPERAND_GPR | 24 },
|
{ "r24", TIC80_OPERAND_GPR | 24 },
|
{ "r25", TIC80_OPERAND_GPR | 25 },
|
{ "r25", TIC80_OPERAND_GPR | 25 },
|
{ "r26", TIC80_OPERAND_GPR | 26 },
|
{ "r26", TIC80_OPERAND_GPR | 26 },
|
{ "r27", TIC80_OPERAND_GPR | 27 },
|
{ "r27", TIC80_OPERAND_GPR | 27 },
|
{ "r28", TIC80_OPERAND_GPR | 28 },
|
{ "r28", TIC80_OPERAND_GPR | 28 },
|
{ "r29", TIC80_OPERAND_GPR | 29 },
|
{ "r29", TIC80_OPERAND_GPR | 29 },
|
{ "r3", TIC80_OPERAND_GPR | 3 },
|
{ "r3", TIC80_OPERAND_GPR | 3 },
|
{ "r30", TIC80_OPERAND_GPR | 30 },
|
{ "r30", TIC80_OPERAND_GPR | 30 },
|
{ "r31", TIC80_OPERAND_GPR | 31 },
|
{ "r31", TIC80_OPERAND_GPR | 31 },
|
{ "r4", TIC80_OPERAND_GPR | 4 },
|
{ "r4", TIC80_OPERAND_GPR | 4 },
|
{ "r5", TIC80_OPERAND_GPR | 5 },
|
{ "r5", TIC80_OPERAND_GPR | 5 },
|
{ "r6", TIC80_OPERAND_GPR | 6 },
|
{ "r6", TIC80_OPERAND_GPR | 6 },
|
{ "r7", TIC80_OPERAND_GPR | 7 },
|
{ "r7", TIC80_OPERAND_GPR | 7 },
|
{ "r8", TIC80_OPERAND_GPR | 8 },
|
{ "r8", TIC80_OPERAND_GPR | 8 },
|
{ "r9", TIC80_OPERAND_GPR | 9 },
|
{ "r9", TIC80_OPERAND_GPR | 9 },
|
{ "SYSSTK", TIC80_OPERAND_CR | 0x20 },
|
{ "SYSSTK", TIC80_OPERAND_CR | 0x20 },
|
{ "SYSTMP", TIC80_OPERAND_CR | 0x21 },
|
{ "SYSTMP", TIC80_OPERAND_CR | 0x21 },
|
{ "TCOUNT", TIC80_OPERAND_CR | 0xE },
|
{ "TCOUNT", TIC80_OPERAND_CR | 0xE },
|
{ "TSCALE", TIC80_OPERAND_CR | 0xF },
|
{ "TSCALE", TIC80_OPERAND_CR | 0xF },
|
{ "uo.f", TIC80_OPERAND_BITNUM | 30 },
|
{ "uo.f", TIC80_OPERAND_BITNUM | 30 },
|
};
|
};
|
|
|
const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol);
|
const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol);
|
|
|
/* This function takes a predefined symbol name in NAME, symbol class
|
/* This function takes a predefined symbol name in NAME, symbol class
|
in CLASS, and translates it to a numeric value, which it returns.
|
in CLASS, and translates it to a numeric value, which it returns.
|
|
|
If CLASS is zero, any symbol that matches NAME is translated. If
|
If CLASS is zero, any symbol that matches NAME is translated. If
|
CLASS is non-zero, then only a symbol that has symbol_class CLASS is
|
CLASS is non-zero, then only a symbol that has symbol_class CLASS is
|
matched.
|
matched.
|
|
|
If no translation is possible, it returns -1, a value not used by
|
If no translation is possible, it returns -1, a value not used by
|
any predefined symbol. Note that the predefined symbol array is
|
any predefined symbol. Note that the predefined symbol array is
|
presorted case independently by name.
|
presorted case independently by name.
|
|
|
This function is implemented with the assumption that there are no
|
This function is implemented with the assumption that there are no
|
duplicate names in the predefined symbol array, which happens to be
|
duplicate names in the predefined symbol array, which happens to be
|
true at the moment.
|
true at the moment.
|
|
|
*/
|
*/
|
|
|
int
|
int
|
tic80_symbol_to_value (name, symbol_class)
|
tic80_symbol_to_value (name, symbol_class)
|
char *name;
|
char *name;
|
int symbol_class;
|
int symbol_class;
|
{
|
{
|
const struct predefined_symbol *pdsp;
|
const struct predefined_symbol *pdsp;
|
int low = 0;
|
int low = 0;
|
int middle;
|
int middle;
|
int high = tic80_num_predefined_symbols - 1;
|
int high = tic80_num_predefined_symbols - 1;
|
int cmp;
|
int cmp;
|
int rtnval = -1;
|
int rtnval = -1;
|
|
|
while (low <= high)
|
while (low <= high)
|
{
|
{
|
middle = (low + high) / 2;
|
middle = (low + high) / 2;
|
cmp = strcasecmp (name, tic80_predefined_symbols[middle].name);
|
cmp = strcasecmp (name, tic80_predefined_symbols[middle].name);
|
if (cmp < 0)
|
if (cmp < 0)
|
{
|
{
|
high = middle - 1;
|
high = middle - 1;
|
}
|
}
|
else if (cmp > 0)
|
else if (cmp > 0)
|
{
|
{
|
low = middle + 1;
|
low = middle + 1;
|
}
|
}
|
else
|
else
|
{
|
{
|
pdsp = &tic80_predefined_symbols[middle];
|
pdsp = &tic80_predefined_symbols[middle];
|
if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp)))
|
if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp)))
|
{
|
{
|
rtnval = PDS_VALUE (pdsp);
|
rtnval = PDS_VALUE (pdsp);
|
}
|
}
|
/* For now we assume that there are no duplicate names */
|
/* For now we assume that there are no duplicate names */
|
break;
|
break;
|
}
|
}
|
}
|
}
|
return (rtnval);
|
return (rtnval);
|
}
|
}
|
|
|
/* This function takes a value VAL and finds a matching predefined
|
/* This function takes a value VAL and finds a matching predefined
|
symbol that is in the operand symbol_class specified by CLASS. If CLASS
|
symbol that is in the operand symbol_class specified by CLASS. If CLASS
|
is zero, the first matching symbol is returned. */
|
is zero, the first matching symbol is returned. */
|
|
|
const char *
|
const char *
|
tic80_value_to_symbol (val, symbol_class)
|
tic80_value_to_symbol (val, symbol_class)
|
int val;
|
int val;
|
int symbol_class;
|
int symbol_class;
|
{
|
{
|
const struct predefined_symbol *pdsp;
|
const struct predefined_symbol *pdsp;
|
int ival;
|
int ival;
|
char *name;
|
char *name;
|
|
|
name = NULL;
|
name = NULL;
|
for (pdsp = tic80_predefined_symbols;
|
for (pdsp = tic80_predefined_symbols;
|
pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols;
|
pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols;
|
pdsp++)
|
pdsp++)
|
{
|
{
|
ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK;
|
ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK;
|
if (ival == val)
|
if (ival == val)
|
{
|
{
|
if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp)))
|
if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp)))
|
{
|
{
|
/* Found the desired match */
|
/* Found the desired match */
|
name = PDS_NAME (pdsp);
|
name = PDS_NAME (pdsp);
|
break;
|
break;
|
}
|
}
|
}
|
}
|
}
|
}
|
return (name);
|
return (name);
|
}
|
}
|
|
|
/* This function returns a pointer to the next symbol in the predefined
|
/* This function returns a pointer to the next symbol in the predefined
|
symbol table after PDSP, or NULL if PDSP points to the last symbol. If
|
symbol table after PDSP, or NULL if PDSP points to the last symbol. If
|
PDSP is NULL, it returns the first symbol in the table. Thus it can be
|
PDSP is NULL, it returns the first symbol in the table. Thus it can be
|
used to walk through the table by first calling it with NULL and then
|
used to walk through the table by first calling it with NULL and then
|
calling it with each value it returned on the previous call, until it
|
calling it with each value it returned on the previous call, until it
|
returns NULL. */
|
returns NULL. */
|
|
|
const struct predefined_symbol *
|
const struct predefined_symbol *
|
tic80_next_predefined_symbol (pdsp)
|
tic80_next_predefined_symbol (pdsp)
|
const struct predefined_symbol *pdsp;
|
const struct predefined_symbol *pdsp;
|
{
|
{
|
if (pdsp == NULL)
|
if (pdsp == NULL)
|
{
|
{
|
pdsp = tic80_predefined_symbols;
|
pdsp = tic80_predefined_symbols;
|
}
|
}
|
else if (pdsp >= tic80_predefined_symbols &&
|
else if (pdsp >= tic80_predefined_symbols &&
|
pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1)
|
pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1)
|
{
|
{
|
pdsp++;
|
pdsp++;
|
}
|
}
|
else
|
else
|
{
|
{
|
pdsp = NULL;
|
pdsp = NULL;
|
}
|
}
|
return (pdsp);
|
return (pdsp);
|
}
|
}
|
|
|
|
|
|
|
/* The operands table. The fields are:
|
/* The operands table. The fields are:
|
|
|
bits, shift, insertion function, extraction function, flags
|
bits, shift, insertion function, extraction function, flags
|
*/
|
*/
|
|
|
const struct tic80_operand tic80_operands[] =
|
const struct tic80_operand tic80_operands[] =
|
{
|
{
|
|
|
/* The zero index is used to indicate the end of the list of operands. */
|
/* The zero index is used to indicate the end of the list of operands. */
|
|
|
#define UNUSED (0)
|
#define UNUSED (0)
|
{ 0, 0, 0, 0, 0 },
|
{ 0, 0, 0, 0, 0 },
|
|
|
/* Short signed immediate value in bits 14-0. */
|
/* Short signed immediate value in bits 14-0. */
|
|
|
#define SSI (UNUSED + 1)
|
#define SSI (UNUSED + 1)
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
|
|
|
/* Short unsigned immediate value in bits 14-0 */
|
/* Short unsigned immediate value in bits 14-0 */
|
|
|
#define SUI (SSI + 1)
|
#define SUI (SSI + 1)
|
{ 15, 0, NULL, NULL, 0 },
|
{ 15, 0, NULL, NULL, 0 },
|
|
|
/* Short unsigned bitfield in bits 14-0. We distinguish this
|
/* Short unsigned bitfield in bits 14-0. We distinguish this
|
from a regular unsigned immediate value only for the convenience
|
from a regular unsigned immediate value only for the convenience
|
of the disassembler and the user. */
|
of the disassembler and the user. */
|
|
|
#define SUBF (SUI + 1)
|
#define SUBF (SUI + 1)
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
|
|
|
/* Long signed immediate in following 32 bit word */
|
/* Long signed immediate in following 32 bit word */
|
|
|
#define LSI (SUBF + 1)
|
#define LSI (SUBF + 1)
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
|
|
|
/* Long unsigned immediate in following 32 bit word */
|
/* Long unsigned immediate in following 32 bit word */
|
|
|
#define LUI (LSI + 1)
|
#define LUI (LSI + 1)
|
{ 32, 0, NULL, NULL, 0 },
|
{ 32, 0, NULL, NULL, 0 },
|
|
|
/* Long unsigned bitfield in following 32 bit word. We distinguish
|
/* Long unsigned bitfield in following 32 bit word. We distinguish
|
this from a regular unsigned immediate value only for the
|
this from a regular unsigned immediate value only for the
|
convenience of the disassembler and the user. */
|
convenience of the disassembler and the user. */
|
|
|
#define LUBF (LUI + 1)
|
#define LUBF (LUI + 1)
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
|
|
|
/* Single precision floating point immediate in following 32 bit
|
/* Single precision floating point immediate in following 32 bit
|
word. */
|
word. */
|
|
|
#define SPFI (LUBF + 1)
|
#define SPFI (LUBF + 1)
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
|
|
|
/* Register in bits 4-0 */
|
/* Register in bits 4-0 */
|
|
|
#define REG_0 (SPFI + 1)
|
#define REG_0 (SPFI + 1)
|
{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
|
{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
|
|
|
/* Even register in bits 4-0 */
|
/* Even register in bits 4-0 */
|
|
|
#define REG_0_E (REG_0 + 1)
|
#define REG_0_E (REG_0 + 1)
|
{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
|
{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
|
|
|
/* Register in bits 26-22 */
|
/* Register in bits 26-22 */
|
|
|
#define REG_22 (REG_0_E + 1)
|
#define REG_22 (REG_0_E + 1)
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
|
|
|
/* Even register in bits 26-22 */
|
/* Even register in bits 26-22 */
|
|
|
#define REG_22_E (REG_22 + 1)
|
#define REG_22_E (REG_22 + 1)
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
|
|
|
/* Register in bits 31-27 */
|
/* Register in bits 31-27 */
|
|
|
#define REG_DEST (REG_22_E + 1)
|
#define REG_DEST (REG_22_E + 1)
|
{ 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
|
{ 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
|
|
|
/* Even register in bits 31-27 */
|
/* Even register in bits 31-27 */
|
|
|
#define REG_DEST_E (REG_DEST + 1)
|
#define REG_DEST_E (REG_DEST + 1)
|
{ 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
|
{ 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
|
|
|
/* Floating point accumulator register (a0-a3) specified by bit 16 (MSB)
|
/* Floating point accumulator register (a0-a3) specified by bit 16 (MSB)
|
and bit 11 (LSB) */
|
and bit 11 (LSB) */
|
/* FIXME! Needs to use functions to insert and extract the register
|
/* FIXME! Needs to use functions to insert and extract the register
|
number in bits 16 and 11. */
|
number in bits 16 and 11. */
|
|
|
#define REG_FPA (REG_DEST_E + 1)
|
#define REG_FPA (REG_DEST_E + 1)
|
{ 0, 0, NULL, NULL, TIC80_OPERAND_FPA },
|
{ 0, 0, NULL, NULL, TIC80_OPERAND_FPA },
|
|
|
/* Short signed PC word offset in bits 14-0 */
|
/* Short signed PC word offset in bits 14-0 */
|
|
|
#define OFF_SS_PC (REG_FPA + 1)
|
#define OFF_SS_PC (REG_FPA + 1)
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
|
|
|
/* Long signed PC word offset in following 32 bit word */
|
/* Long signed PC word offset in following 32 bit word */
|
|
|
#define OFF_SL_PC (OFF_SS_PC + 1)
|
#define OFF_SL_PC (OFF_SS_PC + 1)
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
|
|
|
/* Short signed base relative byte offset in bits 14-0 */
|
/* Short signed base relative byte offset in bits 14-0 */
|
|
|
#define OFF_SS_BR (OFF_SL_PC + 1)
|
#define OFF_SS_BR (OFF_SL_PC + 1)
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
|
|
|
/* Long signed base relative byte offset in following 32 bit word */
|
/* Long signed base relative byte offset in following 32 bit word */
|
|
|
#define OFF_SL_BR (OFF_SS_BR + 1)
|
#define OFF_SL_BR (OFF_SS_BR + 1)
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
|
|
|
/* Long signed base relative byte offset in following 32 bit word
|
/* Long signed base relative byte offset in following 32 bit word
|
with optional ":s" modifier flag in bit 11 */
|
with optional ":s" modifier flag in bit 11 */
|
|
|
#define OFF_SL_BR_SCALED (OFF_SL_BR + 1)
|
#define OFF_SL_BR_SCALED (OFF_SL_BR + 1)
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
|
|
|
/* BITNUM in bits 31-27 */
|
/* BITNUM in bits 31-27 */
|
|
|
#define BITNUM (OFF_SL_BR_SCALED + 1)
|
#define BITNUM (OFF_SL_BR_SCALED + 1)
|
{ 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
|
{ 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
|
|
|
/* Condition code in bits 31-27 */
|
/* Condition code in bits 31-27 */
|
|
|
#define CC (BITNUM + 1)
|
#define CC (BITNUM + 1)
|
{ 5, 27, NULL, NULL, TIC80_OPERAND_CC },
|
{ 5, 27, NULL, NULL, TIC80_OPERAND_CC },
|
|
|
/* Control register number in bits 14-0 */
|
/* Control register number in bits 14-0 */
|
|
|
#define CR_SI (CC + 1)
|
#define CR_SI (CC + 1)
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_CR },
|
{ 15, 0, NULL, NULL, TIC80_OPERAND_CR },
|
|
|
/* Control register number in next 32 bit word */
|
/* Control register number in next 32 bit word */
|
|
|
#define CR_LI (CR_SI + 1)
|
#define CR_LI (CR_SI + 1)
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_CR },
|
{ 32, 0, NULL, NULL, TIC80_OPERAND_CR },
|
|
|
/* A base register in bits 26-22, enclosed in parens */
|
/* A base register in bits 26-22, enclosed in parens */
|
|
|
#define REG_BASE (CR_LI + 1)
|
#define REG_BASE (CR_LI + 1)
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },
|
|
|
/* A base register in bits 26-22, enclosed in parens, with optional ":m"
|
/* A base register in bits 26-22, enclosed in parens, with optional ":m"
|
flag in bit 17 (short immediate instructions only) */
|
flag in bit 17 (short immediate instructions only) */
|
|
|
#define REG_BASE_M_SI (REG_BASE + 1)
|
#define REG_BASE_M_SI (REG_BASE + 1)
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
|
|
|
/* A base register in bits 26-22, enclosed in parens, with optional ":m"
|
/* A base register in bits 26-22, enclosed in parens, with optional ":m"
|
flag in bit 15 (long immediate and register instructions only) */
|
flag in bit 15 (long immediate and register instructions only) */
|
|
|
#define REG_BASE_M_LI (REG_BASE_M_SI + 1)
|
#define REG_BASE_M_LI (REG_BASE_M_SI + 1)
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
|
{ 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
|
|
|
/* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
|
/* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
|
|
|
#define REG_SCALED (REG_BASE_M_LI + 1)
|
#define REG_SCALED (REG_BASE_M_LI + 1)
|
{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
|
{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
|
|
|
/* Unsigned immediate in bits 4-0, used only for shift instructions */
|
/* Unsigned immediate in bits 4-0, used only for shift instructions */
|
|
|
#define ROTATE (REG_SCALED + 1)
|
#define ROTATE (REG_SCALED + 1)
|
{ 5, 0, NULL, NULL, 0 },
|
{ 5, 0, NULL, NULL, 0 },
|
|
|
/* Unsigned immediate in bits 9-5, used only for shift instructions */
|
/* Unsigned immediate in bits 9-5, used only for shift instructions */
|
#define ENDMASK (ROTATE + 1)
|
#define ENDMASK (ROTATE + 1)
|
{ 5, 5, NULL, NULL, TIC80_OPERAND_ENDMASK },
|
{ 5, 5, NULL, NULL, TIC80_OPERAND_ENDMASK },
|
|
|
};
|
};
|
|
|
const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
|
const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
|
|
|
|
|
/* Macros used to generate entries for the opcodes table. */
|
/* Macros used to generate entries for the opcodes table. */
|
|
|
#define FIXME 0
|
#define FIXME 0
|
|
|
/* Short-Immediate Format Instructions - basic opcode */
|
/* Short-Immediate Format Instructions - basic opcode */
|
#define OP_SI(x) (((x) & 0x7F) << 15)
|
#define OP_SI(x) (((x) & 0x7F) << 15)
|
#define MASK_SI OP_SI(0x7F)
|
#define MASK_SI OP_SI(0x7F)
|
|
|
/* Long-Immediate Format Instructions - basic opcode */
|
/* Long-Immediate Format Instructions - basic opcode */
|
#define OP_LI(x) (((x) & 0x3FF) << 12)
|
#define OP_LI(x) (((x) & 0x3FF) << 12)
|
#define MASK_LI OP_LI(0x3FF)
|
#define MASK_LI OP_LI(0x3FF)
|
|
|
/* Register Format Instructions - basic opcode */
|
/* Register Format Instructions - basic opcode */
|
#define OP_REG(x) OP_LI(x) /* For readability */
|
#define OP_REG(x) OP_LI(x) /* For readability */
|
#define MASK_REG MASK_LI /* For readability */
|
#define MASK_REG MASK_LI /* For readability */
|
|
|
/* The 'n' bit at bit 10 */
|
/* The 'n' bit at bit 10 */
|
#define n(x) ((x) << 10)
|
#define n(x) ((x) << 10)
|
|
|
/* The 'i' bit at bit 11 */
|
/* The 'i' bit at bit 11 */
|
#define i(x) ((x) << 11)
|
#define i(x) ((x) << 11)
|
|
|
/* The 'F' bit at bit 27 */
|
/* The 'F' bit at bit 27 */
|
#define F(x) ((x) << 27)
|
#define F(x) ((x) << 27)
|
|
|
/* The 'E' bit at bit 27 */
|
/* The 'E' bit at bit 27 */
|
#define E(x) ((x) << 27)
|
#define E(x) ((x) << 27)
|
|
|
/* The 'M' bit at bit 15 in register and long immediate opcodes */
|
/* The 'M' bit at bit 15 in register and long immediate opcodes */
|
#define M_REG(x) ((x) << 15)
|
#define M_REG(x) ((x) << 15)
|
#define M_LI(x) ((x) << 15)
|
#define M_LI(x) ((x) << 15)
|
|
|
/* The 'M' bit at bit 17 in short immediate opcodes */
|
/* The 'M' bit at bit 17 in short immediate opcodes */
|
#define M_SI(x) ((x) << 17)
|
#define M_SI(x) ((x) << 17)
|
|
|
/* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
|
/* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
|
#define SZ_REG(x) ((x) << 13)
|
#define SZ_REG(x) ((x) << 13)
|
#define SZ_LI(x) ((x) << 13)
|
#define SZ_LI(x) ((x) << 13)
|
|
|
/* The 'SZ' field at bits 16-15 in short immediate opcodes */
|
/* The 'SZ' field at bits 16-15 in short immediate opcodes */
|
#define SZ_SI(x) ((x) << 15)
|
#define SZ_SI(x) ((x) << 15)
|
|
|
/* The 'D' (direct external memory access) bit at bit 10 in long immediate
|
/* The 'D' (direct external memory access) bit at bit 10 in long immediate
|
and register opcodes. */
|
and register opcodes. */
|
#define D(x) ((x) << 10)
|
#define D(x) ((x) << 10)
|
|
|
/* The 'S' (scale offset by data size) bit at bit 11 in long immediate
|
/* The 'S' (scale offset by data size) bit at bit 11 in long immediate
|
and register opcodes. */
|
and register opcodes. */
|
#define S(x) ((x) << 11)
|
#define S(x) ((x) << 11)
|
|
|
/* The 'PD' field at bits 10-9 in floating point instructions */
|
/* The 'PD' field at bits 10-9 in floating point instructions */
|
#define PD(x) ((x) << 9)
|
#define PD(x) ((x) << 9)
|
|
|
/* The 'P2' field at bits 8-7 in floating point instructions */
|
/* The 'P2' field at bits 8-7 in floating point instructions */
|
#define P2(x) ((x) << 7)
|
#define P2(x) ((x) << 7)
|
|
|
/* The 'P1' field at bits 6-5 in floating point instructions */
|
/* The 'P1' field at bits 6-5 in floating point instructions */
|
#define P1(x) ((x) << 5)
|
#define P1(x) ((x) << 5)
|
|
|
/* The 'a' field at bit 16 in vector instructions */
|
/* The 'a' field at bit 16 in vector instructions */
|
#define V_a1(x) ((x) << 16)
|
#define V_a1(x) ((x) << 16)
|
|
|
/* The 'a' field at bit 11 in vector instructions */
|
/* The 'a' field at bit 11 in vector instructions */
|
#define V_a0(x) ((x) << 11)
|
#define V_a0(x) ((x) << 11)
|
|
|
/* The 'm' field at bit 10 in vector instructions */
|
/* The 'm' field at bit 10 in vector instructions */
|
#define V_m(x) ((x) << 10)
|
#define V_m(x) ((x) << 10)
|
|
|
/* The 'S' field at bit 9 in vector instructions */
|
/* The 'S' field at bit 9 in vector instructions */
|
#define V_S(x) ((x) << 9)
|
#define V_S(x) ((x) << 9)
|
|
|
/* The 'Z' field at bit 8 in vector instructions */
|
/* The 'Z' field at bit 8 in vector instructions */
|
#define V_Z(x) ((x) << 8)
|
#define V_Z(x) ((x) << 8)
|
|
|
/* The 'p' field at bit 6 in vector instructions */
|
/* The 'p' field at bit 6 in vector instructions */
|
#define V_p(x) ((x) << 6)
|
#define V_p(x) ((x) << 6)
|
|
|
/* The opcode field at bits 21-17 for vector instructions */
|
/* The opcode field at bits 21-17 for vector instructions */
|
#define OP_V(x) ((x) << 17)
|
#define OP_V(x) ((x) << 17)
|
#define MASK_V OP_V(0x1F)
|
#define MASK_V OP_V(0x1F)
|
|
|
|
|
/* The opcode table. Formatted for better readability on a wide screen. Also, all
|
/* The opcode table. Formatted for better readability on a wide screen. Also, all
|
entries with the same mnemonic are sorted so that they are adjacent in the table,
|
entries with the same mnemonic are sorted so that they are adjacent in the table,
|
allowing the use of a hash table to locate the first of a sequence of opcodes that have
|
allowing the use of a hash table to locate the first of a sequence of opcodes that have
|
a particular name. The short immediate forms also come before the long immediate forms
|
a particular name. The short immediate forms also come before the long immediate forms
|
so that the assembler will pick the "best fit" for the size of the operand, except for
|
so that the assembler will pick the "best fit" for the size of the operand, except for
|
the case of the PC relative forms, where the long forms come first and are the default
|
the case of the PC relative forms, where the long forms come first and are the default
|
forms. */
|
forms. */
|
|
|
const struct tic80_opcode tic80_opcodes[] = {
|
const struct tic80_opcode tic80_opcodes[] = {
|
|
|
/* The "nop" instruction is really "rdcr 0,r0". We put it first so that this
|
/* The "nop" instruction is really "rdcr 0,r0". We put it first so that this
|
specific bit pattern will get disassembled as a nop rather than an rdcr. The
|
specific bit pattern will get disassembled as a nop rather than an rdcr. The
|
mask of all ones ensures that this will happen. */
|
mask of all ones ensures that this will happen. */
|
|
|
{"nop", OP_SI(0x4), ~0, 0, {0} },
|
{"nop", OP_SI(0x4), ~0, 0, {0} },
|
|
|
/* The "br" instruction is really "bbz target,r0,31". We put it first so that
|
/* The "br" instruction is really "bbz target,r0,31". We put it first so that
|
this specific bit pattern will get disassembled as a br rather than bbz. */
|
this specific bit pattern will get disassembled as a br rather than bbz. */
|
|
|
{"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} },
|
{"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} },
|
{"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} },
|
{"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} },
|
{"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} },
|
{"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} },
|
{"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} },
|
{"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} },
|
{"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} },
|
{"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} },
|
{"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} },
|
{"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} },
|
|
|
/* Signed integer ADD */
|
/* Signed integer ADD */
|
|
|
{"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"add", OP_LI(0x3B1), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"add", OP_LI(0x3B1), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"add", OP_REG(0x3B0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"add", OP_REG(0x3B0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Unsigned integer ADD */
|
/* Unsigned integer ADD */
|
|
|
{"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"addu", OP_LI(0x3B3), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"addu", OP_LI(0x3B3), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"addu", OP_REG(0x3B2), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"addu", OP_REG(0x3B2), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Bitwise AND */
|
/* Bitwise AND */
|
|
|
{"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"and", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and.tt", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and.tt", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and.tt", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"and.tt", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Bitwise AND with ones complement of both sources */
|
/* Bitwise AND with ones complement of both sources */
|
|
|
{"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and.ff", OP_LI(0x331), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and.ff", OP_LI(0x331), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and.ff", OP_REG(0x330), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"and.ff", OP_REG(0x330), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Bitwise AND with ones complement of source 1 */
|
/* Bitwise AND with ones complement of source 1 */
|
|
|
{"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and.ft", OP_LI(0x329), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and.ft", OP_LI(0x329), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and.ft", OP_REG(0x328), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"and.ft", OP_REG(0x328), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Bitwise AND with ones complement of source 2 */
|
/* Bitwise AND with ones complement of source 2 */
|
|
|
{"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"and.tf", OP_LI(0x325), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and.tf", OP_LI(0x325), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"and.tf", OP_REG(0x324), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"and.tf", OP_REG(0x324), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Branch Bit One - nonannulled */
|
/* Branch Bit One - nonannulled */
|
|
|
{"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
|
{"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
|
{"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
|
{"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
|
{"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
|
{"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
|
|
|
/* Branch Bit One - annulled */
|
/* Branch Bit One - annulled */
|
|
|
{"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
|
{"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
|
{"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
|
{"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
|
{"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
|
{"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
|
|
|
/* Branch Bit Zero - nonannulled */
|
/* Branch Bit Zero - nonannulled */
|
|
|
{"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
|
{"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
|
{"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
|
{"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
|
{"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
|
{"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
|
|
|
/* Branch Bit Zero - annulled */
|
/* Branch Bit Zero - annulled */
|
|
|
{"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
|
{"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
|
{"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
|
{"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
|
{"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
|
{"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
|
|
|
/* Branch Conditional - nonannulled */
|
/* Branch Conditional - nonannulled */
|
|
|
{"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} },
|
{"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} },
|
{"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} },
|
{"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} },
|
{"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} },
|
{"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} },
|
|
|
/* Branch Conditional - annulled */
|
/* Branch Conditional - annulled */
|
|
|
{"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} },
|
{"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} },
|
{"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} },
|
{"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} },
|
{"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} },
|
{"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} },
|
|
|
/* Branch Control Register */
|
/* Branch Control Register */
|
|
|
{"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} },
|
{"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} },
|
{"brcr", OP_LI(0x30D), MASK_LI, 0, {CR_LI} },
|
{"brcr", OP_LI(0x30D), MASK_LI, 0, {CR_LI} },
|
{"brcr", OP_REG(0x30C), MASK_REG, 0, {REG_0} },
|
{"brcr", OP_REG(0x30C), MASK_REG, 0, {REG_0} },
|
|
|
/* Branch and save return - nonannulled */
|
/* Branch and save return - nonannulled */
|
|
|
{"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} },
|
{"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} },
|
{"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} },
|
{"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} },
|
{"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} },
|
{"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} },
|
|
|
/* Branch and save return - annulled */
|
/* Branch and save return - annulled */
|
|
|
{"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} },
|
{"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} },
|
{"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} },
|
{"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} },
|
{"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} },
|
{"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} },
|
|
|
/* Send command */
|
/* Send command */
|
|
|
{"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} },
|
{"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} },
|
{"cmnd", OP_LI(0x305), MASK_LI, 0, {LUI} },
|
{"cmnd", OP_LI(0x305), MASK_LI, 0, {LUI} },
|
{"cmnd", OP_REG(0x304), MASK_REG, 0, {REG_0} },
|
{"cmnd", OP_REG(0x304), MASK_REG, 0, {REG_0} },
|
|
|
/* Integer compare */
|
/* Integer compare */
|
|
|
{"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"cmp", OP_LI(0x3A1), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"cmp", OP_LI(0x3A1), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"cmp", OP_REG(0x3A0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"cmp", OP_REG(0x3A0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Flush data cache subblock - don't clear subblock preset flag */
|
/* Flush data cache subblock - don't clear subblock preset flag */
|
|
|
{"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} },
|
{"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} },
|
{"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} },
|
{"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} },
|
{"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} },
|
{"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} },
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|
|
/* Flush data cache subblock - clear subblock preset flag */
|
/* Flush data cache subblock - clear subblock preset flag */
|
|
|
{"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} },
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{"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} },
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{"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} },
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{"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} },
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{"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} },
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{"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} },
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|
|
/* Direct load signed data into register */
|
/* Direct load signed data into register */
|
|
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{"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
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{"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
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{"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
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{"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
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{"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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|
|
/* Direct load unsigned data into register */
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/* Direct load unsigned data into register */
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{"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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|
|
/* Direct store data into memory */
|
/* Direct store data into memory */
|
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{"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
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{"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
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{"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
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{"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
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{"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
|
|
/* Emulation stop */
|
/* Emulation stop */
|
|
|
{"estop", OP_LI(0x3FC), MASK_LI, 0, {0} },
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{"estop", OP_LI(0x3FC), MASK_LI, 0, {0} },
|
|
|
/* Emulation trap */
|
/* Emulation trap */
|
|
|
{"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} },
|
{"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} },
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{"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), 0, {LUI} },
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{"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), 0, {LUI} },
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{"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), 0, {REG_0} },
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{"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), 0, {REG_0} },
|
|
|
/* Floating-point addition */
|
/* Floating-point addition */
|
|
|
{"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
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{"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
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{"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
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{"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
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{"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
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{"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
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{"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
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{"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
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{"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
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{"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
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{"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
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{"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
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{"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
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{"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
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{"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
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{"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Floating point compare */
|
/* Floating point compare */
|
|
|
{"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST} },
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{"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST} },
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{"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST} },
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{"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST} },
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{"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST} },
|
{"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST} },
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{"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST} },
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{"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST} },
|
{"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
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{"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
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{"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
|
{"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Floating point divide */
|
/* Floating point divide */
|
|
|
{"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
|
{"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
|
{"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
|
{"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
|
{"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
|
{"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
|
{"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
|
{"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
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{"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
|
{"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
|
{"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
|
{"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
|
{"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
|
{"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
|
{"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
|
{"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Floating point multiply */
|
/* Floating point multiply */
|
|
|
{"fmpy.ddd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
|
{"fmpy.ddd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
|
{"fmpy.dsd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
|
{"fmpy.dsd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
|
{"fmpy.iii", OP_LI(0x3E5) | PD(2) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_22, REG_DEST} },
|
{"fmpy.iii", OP_LI(0x3E5) | PD(2) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_22, REG_DEST} },
|
{"fmpy.iii", OP_REG(0x3E4) | PD(2) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
|
{"fmpy.iii", OP_REG(0x3E4) | PD(2) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
|
{"fmpy.sdd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
|
{"fmpy.sdd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
|
{"fmpy.sdd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
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{"fmpy.sdd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
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{"fmpy.ssd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
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{"fmpy.ssd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
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{"fmpy.ssd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
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{"fmpy.ssd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
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{"fmpy.sss", OP_LI(0x3E5) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
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{"fmpy.sss", OP_LI(0x3E5) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
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{"fmpy.sss", OP_REG(0x3E4) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
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{"fmpy.sss", OP_REG(0x3E4) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
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{"fmpy.uuu", OP_LI(0x3E5) | PD(3) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LUI, REG_22, REG_DEST} },
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{"fmpy.uuu", OP_LI(0x3E5) | PD(3) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LUI, REG_22, REG_DEST} },
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{"fmpy.uuu", OP_REG(0x3E4) | PD(3) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
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{"fmpy.uuu", OP_REG(0x3E4) | PD(3) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
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|
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/* Convert/Round to Minus Infinity */
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/* Convert/Round to Minus Infinity */
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{"frndm.dd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
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{"frndm.dd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
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{"frndm.di", OP_REG(0x3E8) | PD(2) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndm.di", OP_REG(0x3E8) | PD(2) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndm.ds", OP_REG(0x3E8) | PD(0) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndm.ds", OP_REG(0x3E8) | PD(0) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndm.du", OP_REG(0x3E8) | PD(3) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndm.du", OP_REG(0x3E8) | PD(3) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndm.id", OP_LI(0x3E9) | PD(1) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndm.id", OP_LI(0x3E9) | PD(1) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndm.id", OP_REG(0x3E8) | PD(1) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndm.id", OP_REG(0x3E8) | PD(1) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndm.is", OP_LI(0x3E9) | PD(0) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
|
{"frndm.is", OP_LI(0x3E9) | PD(0) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
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{"frndm.is", OP_REG(0x3E8) | PD(0) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndm.is", OP_REG(0x3E8) | PD(0) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndm.sd", OP_LI(0x3E9) | PD(1) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
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{"frndm.sd", OP_LI(0x3E9) | PD(1) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
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{"frndm.sd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndm.sd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndm.si", OP_LI(0x3E9) | PD(2) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndm.si", OP_LI(0x3E9) | PD(2) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndm.si", OP_REG(0x3E8) | PD(2) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndm.si", OP_REG(0x3E8) | PD(2) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndm.ss", OP_LI(0x3E9) | PD(0) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
|
{"frndm.ss", OP_LI(0x3E9) | PD(0) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
|
{"frndm.ss", OP_REG(0x3E8) | PD(0) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
|
{"frndm.ss", OP_REG(0x3E8) | PD(0) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
|
{"frndm.su", OP_LI(0x3E9) | PD(3) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
|
{"frndm.su", OP_LI(0x3E9) | PD(3) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndm.su", OP_REG(0x3E8) | PD(3) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndm.su", OP_REG(0x3E8) | PD(3) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
|
{"frndm.ud", OP_LI(0x3E9) | PD(1) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
|
{"frndm.ud", OP_LI(0x3E9) | PD(1) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
|
{"frndm.ud", OP_REG(0x3E8) | PD(1) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
|
{"frndm.ud", OP_REG(0x3E8) | PD(1) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndm.us", OP_LI(0x3E9) | PD(0) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
|
{"frndm.us", OP_LI(0x3E9) | PD(0) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
|
{"frndm.us", OP_REG(0x3E8) | PD(0) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
|
{"frndm.us", OP_REG(0x3E8) | PD(0) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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|
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/* Convert/Round to Nearest */
|
/* Convert/Round to Nearest */
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|
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{"frndn.dd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
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{"frndn.dd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
|
{"frndn.di", OP_REG(0x3E8) | PD(2) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndn.di", OP_REG(0x3E8) | PD(2) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndn.ds", OP_REG(0x3E8) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndn.ds", OP_REG(0x3E8) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndn.du", OP_REG(0x3E8) | PD(3) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndn.du", OP_REG(0x3E8) | PD(3) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndn.id", OP_LI(0x3E9) | PD(1) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndn.id", OP_LI(0x3E9) | PD(1) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndn.id", OP_REG(0x3E8) | PD(1) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndn.id", OP_REG(0x3E8) | PD(1) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndn.is", OP_LI(0x3E9) | PD(0) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
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{"frndn.is", OP_LI(0x3E9) | PD(0) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
|
{"frndn.is", OP_REG(0x3E8) | PD(0) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndn.is", OP_REG(0x3E8) | PD(0) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndn.sd", OP_LI(0x3E9) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
|
{"frndn.sd", OP_LI(0x3E9) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
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{"frndn.sd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
|
{"frndn.sd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndn.si", OP_LI(0x3E9) | PD(2) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndn.si", OP_LI(0x3E9) | PD(2) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndn.si", OP_REG(0x3E8) | PD(2) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndn.si", OP_REG(0x3E8) | PD(2) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndn.ss", OP_LI(0x3E9) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndn.ss", OP_LI(0x3E9) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndn.ss", OP_REG(0x3E8) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndn.ss", OP_REG(0x3E8) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndn.su", OP_LI(0x3E9) | PD(3) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndn.su", OP_LI(0x3E9) | PD(3) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndn.su", OP_REG(0x3E8) | PD(3) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndn.su", OP_REG(0x3E8) | PD(3) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
|
{"frndn.ud", OP_LI(0x3E9) | PD(1) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
|
{"frndn.ud", OP_LI(0x3E9) | PD(1) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndn.ud", OP_REG(0x3E8) | PD(1) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndn.ud", OP_REG(0x3E8) | PD(1) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndn.us", OP_LI(0x3E9) | PD(0) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
|
{"frndn.us", OP_LI(0x3E9) | PD(0) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
|
{"frndn.us", OP_REG(0x3E8) | PD(0) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
|
{"frndn.us", OP_REG(0x3E8) | PD(0) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
|
|
|
/* Convert/Round to Positive Infinity */
|
/* Convert/Round to Positive Infinity */
|
|
|
{"frndp.dd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
|
{"frndp.dd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
|
{"frndp.di", OP_REG(0x3E8) | PD(2) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
|
{"frndp.di", OP_REG(0x3E8) | PD(2) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
|
{"frndp.ds", OP_REG(0x3E8) | PD(0) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
|
{"frndp.ds", OP_REG(0x3E8) | PD(0) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
|
{"frndp.du", OP_REG(0x3E8) | PD(3) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
|
{"frndp.du", OP_REG(0x3E8) | PD(3) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
|
{"frndp.id", OP_LI(0x3E9) | PD(1) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
|
{"frndp.id", OP_LI(0x3E9) | PD(1) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndp.id", OP_REG(0x3E8) | PD(1) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
|
{"frndp.id", OP_REG(0x3E8) | PD(1) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndp.is", OP_LI(0x3E9) | PD(0) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
|
{"frndp.is", OP_LI(0x3E9) | PD(0) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
|
{"frndp.is", OP_REG(0x3E8) | PD(0) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
|
{"frndp.is", OP_REG(0x3E8) | PD(0) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndp.sd", OP_LI(0x3E9) | PD(1) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
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{"frndp.sd", OP_LI(0x3E9) | PD(1) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
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{"frndp.sd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndp.sd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndp.si", OP_LI(0x3E9) | PD(2) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndp.si", OP_LI(0x3E9) | PD(2) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndp.si", OP_REG(0x3E8) | PD(2) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndp.si", OP_REG(0x3E8) | PD(2) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndp.ss", OP_LI(0x3E9) | PD(0) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndp.ss", OP_LI(0x3E9) | PD(0) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndp.ss", OP_REG(0x3E8) | PD(0) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndp.ss", OP_REG(0x3E8) | PD(0) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndp.su", OP_LI(0x3E9) | PD(3) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndp.su", OP_LI(0x3E9) | PD(3) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndp.su", OP_REG(0x3E8) | PD(3) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndp.su", OP_REG(0x3E8) | PD(3) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndp.ud", OP_LI(0x3E9) | PD(1) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndp.ud", OP_LI(0x3E9) | PD(1) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndp.ud", OP_REG(0x3E8) | PD(1) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndp.ud", OP_REG(0x3E8) | PD(1) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndp.us", OP_LI(0x3E9) | PD(0) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
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{"frndp.us", OP_LI(0x3E9) | PD(0) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
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{"frndp.us", OP_REG(0x3E8) | PD(0) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndp.us", OP_REG(0x3E8) | PD(0) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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|
|
/* Convert/Round to Zero */
|
/* Convert/Round to Zero */
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|
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{"frndz.dd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
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{"frndz.dd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
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{"frndz.di", OP_REG(0x3E8) | PD(2) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndz.di", OP_REG(0x3E8) | PD(2) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndz.ds", OP_REG(0x3E8) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndz.ds", OP_REG(0x3E8) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndz.du", OP_REG(0x3E8) | PD(3) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndz.du", OP_REG(0x3E8) | PD(3) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
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{"frndz.id", OP_LI(0x3E9) | PD(1) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndz.id", OP_LI(0x3E9) | PD(1) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndz.id", OP_REG(0x3E8) | PD(1) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndz.id", OP_REG(0x3E8) | PD(1) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndz.is", OP_LI(0x3E9) | PD(0) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
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{"frndz.is", OP_LI(0x3E9) | PD(0) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
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{"frndz.is", OP_REG(0x3E8) | PD(0) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndz.is", OP_REG(0x3E8) | PD(0) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndz.sd", OP_LI(0x3E9) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
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{"frndz.sd", OP_LI(0x3E9) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
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{"frndz.sd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndz.sd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndz.si", OP_LI(0x3E9) | PD(2) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndz.si", OP_LI(0x3E9) | PD(2) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndz.si", OP_REG(0x3E8) | PD(2) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndz.si", OP_REG(0x3E8) | PD(2) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndz.ss", OP_LI(0x3E9) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndz.ss", OP_LI(0x3E9) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndz.ss", OP_REG(0x3E8) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndz.ss", OP_REG(0x3E8) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndz.su", OP_LI(0x3E9) | PD(3) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndz.su", OP_LI(0x3E9) | PD(3) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"frndz.su", OP_REG(0x3E8) | PD(3) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndz.su", OP_REG(0x3E8) | PD(3) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndz.ud", OP_LI(0x3E9) | PD(1) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndz.ud", OP_LI(0x3E9) | PD(1) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
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{"frndz.ud", OP_REG(0x3E8) | PD(1) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndz.ud", OP_REG(0x3E8) | PD(1) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"frndz.us", OP_LI(0x3E9) | PD(0) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
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{"frndz.us", OP_LI(0x3E9) | PD(0) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
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{"frndz.us", OP_REG(0x3E8) | PD(0) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"frndz.us", OP_REG(0x3E8) | PD(0) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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/* Floating point square root */
|
/* Floating point square root */
|
|
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{"fsqrt.dd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
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{"fsqrt.dd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
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{"fsqrt.sd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
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{"fsqrt.sd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
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{"fsqrt.sd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"fsqrt.sd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
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{"fsqrt.ss", OP_LI(0x3EF) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"fsqrt.ss", OP_LI(0x3EF) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
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{"fsqrt.ss", OP_REG(0x3EE) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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{"fsqrt.ss", OP_REG(0x3EE) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
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|
|
/* Floating point subtraction */
|
/* Floating point subtraction */
|
|
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{ "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
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{ "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
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{ "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
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{ "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
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{ "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
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{ "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
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{ "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
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{ "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
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{ "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
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{ "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
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{ "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
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{ "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
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{ "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
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{ "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
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{ "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
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{ "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
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/* Illegal instructions */
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/* Illegal instructions */
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{"illop0", OP_SI(0x0), MASK_SI, 0, {0} },
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{"illop0", OP_SI(0x0), MASK_SI, 0, {0} },
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{"illopF", 0x1FF << 13, 0x1FF << 13, 0, {0} },
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{"illopF", 0x1FF << 13, 0x1FF << 13, 0, {0} },
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/* Jump and save return */
|
/* Jump and save return */
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{"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} },
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{"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} },
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{"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} },
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{"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} },
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{"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} },
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{"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} },
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{"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} },
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{"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} },
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{"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} },
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{"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} },
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{"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} },
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{"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} },
|
|
|
/* Load Signed Data Into Register */
|
/* Load Signed Data Into Register */
|
|
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{"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
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{"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
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{"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
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{"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
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{"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} },
|
{"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} },
|
{"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
|
{"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
|
{"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
|
{"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
|
{"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
|
|
/* Load Unsigned Data Into Register */
|
/* Load Unsigned Data Into Register */
|
|
|
{"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
|
|
/* Leftmost one */
|
/* Leftmost one */
|
|
|
{"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} },
|
{"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} },
|
|
|
/* Bitwise logical OR. Note that "or.tt" and "or" are the same instructions. */
|
/* Bitwise logical OR. Note that "or.tt" and "or" are the same instructions. */
|
|
|
{"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or.ff", OP_LI(0x33D), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or.ff", OP_LI(0x33D), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or.ff", OP_REG(0x33C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"or.ff", OP_REG(0x33C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or.ft", OP_LI(0x33B), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or.ft", OP_LI(0x33B), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or.ft", OP_REG(0x33A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"or.ft", OP_REG(0x33A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or.tf", OP_LI(0x337), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or.tf", OP_LI(0x337), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or.tf", OP_REG(0x336), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"or.tf", OP_REG(0x336), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or.tt", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or.tt", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or.tt", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"or.tt", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"or", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
|
{"or", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
|
{"or", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"or", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Read Control Register */
|
/* Read Control Register */
|
|
|
{"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} },
|
{"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} },
|
{"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), 0, {CR_LI, REG_DEST} },
|
{"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), 0, {CR_LI, REG_DEST} },
|
{"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), 0, {REG_0, REG_DEST} },
|
{"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), 0, {REG_0, REG_DEST} },
|
|
|
/* Rightmost one */
|
/* Rightmost one */
|
|
|
{"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} },
|
{"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} },
|
|
|
/* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions.
|
/* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions.
|
They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */
|
They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */
|
|
|
|
|
{"ins", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"ins", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"ins", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"ins", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"rotl", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"rotl", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"rotl", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"rotl", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"shl", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"shl", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"shl", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"shl", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.dm", OP_REG(0x312) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.dm", OP_REG(0x312) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.dm", OP_SI(0x9) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.dm", OP_SI(0x9) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.ds", OP_REG(0x314) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.ds", OP_REG(0x314) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.ds", OP_SI(0xA) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.ds", OP_SI(0xA) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.dz", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.dz", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.dz", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.dz", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.em", OP_REG(0x318) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.em", OP_REG(0x318) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.em", OP_SI(0xC) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.em", OP_SI(0xC) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.es", OP_REG(0x31A) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.es", OP_REG(0x31A) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.es", OP_SI(0xD) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.es", OP_SI(0xD) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.ez", OP_REG(0x316) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.ez", OP_REG(0x316) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.ez", OP_SI(0xB) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.ez", OP_SI(0xB) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.im", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.im", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.im", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.im", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.iz", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.iz", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sl.iz", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sl.iz", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
|
|
/* Shift Register Left With Inverted Endmask */
|
/* Shift Register Left With Inverted Endmask */
|
|
|
{"sli.dm", OP_REG(0x312) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.dm", OP_REG(0x312) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.dm", OP_SI(0x9) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.dm", OP_SI(0x9) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.ds", OP_REG(0x314) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.ds", OP_REG(0x314) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.ds", OP_SI(0xA) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.ds", OP_SI(0xA) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.dz", OP_REG(0x310) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.dz", OP_REG(0x310) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.dz", OP_SI(0x8) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.dz", OP_SI(0x8) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.em", OP_REG(0x318) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.em", OP_REG(0x318) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.em", OP_SI(0xC) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.em", OP_SI(0xC) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.es", OP_REG(0x31A) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.es", OP_REG(0x31A) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.es", OP_SI(0xD) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.es", OP_SI(0xD) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.ez", OP_REG(0x316) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.ez", OP_REG(0x316) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.ez", OP_SI(0xB) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.ez", OP_SI(0xB) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.im", OP_REG(0x31E) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.im", OP_REG(0x31E) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.im", OP_SI(0xF) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.im", OP_SI(0xF) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.iz", OP_REG(0x31C) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.iz", OP_REG(0x31C) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sli.iz", OP_SI(0xE) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sli.iz", OP_SI(0xE) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
|
|
/* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions.
|
/* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions.
|
They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */
|
They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */
|
|
|
{"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
|
|
/* Shift Register Right With Inverted Endmask */
|
/* Shift Register Right With Inverted Endmask */
|
|
|
{"sri.dm", OP_REG(0x312) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.dm", OP_REG(0x312) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.dm", OP_SI(0x9) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.dm", OP_SI(0x9) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.ds", OP_REG(0x314) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.ds", OP_REG(0x314) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.ds", OP_SI(0xA) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.ds", OP_SI(0xA) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.dz", OP_REG(0x310) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.dz", OP_REG(0x310) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.dz", OP_SI(0x8) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.dz", OP_SI(0x8) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.em", OP_REG(0x318) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.em", OP_REG(0x318) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.em", OP_SI(0xC) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.em", OP_SI(0xC) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.es", OP_REG(0x31A) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.es", OP_REG(0x31A) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.es", OP_SI(0xD) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.es", OP_SI(0xD) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.ez", OP_REG(0x316) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.ez", OP_REG(0x316) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.ez", OP_SI(0xB) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.ez", OP_SI(0xB) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.im", OP_REG(0x31E) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.im", OP_REG(0x31E) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.im", OP_SI(0xF) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.im", OP_SI(0xF) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.iz", OP_REG(0x31C) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.iz", OP_REG(0x31C) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
|
{"sri.iz", OP_SI(0xE) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
{"sri.iz", OP_SI(0xE) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
|
|
|
/* Store Data into Memory */
|
/* Store Data into Memory */
|
|
|
{"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} },
|
{"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} },
|
{"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
|
{"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
|
{"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
|
{"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
|
{"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
|
{"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
{"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
|
|
|
/* Signed Integer Subtract */
|
/* Signed Integer Subtract */
|
|
|
{"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"sub", OP_LI(0x3B5), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"sub", OP_LI(0x3B5), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"sub", OP_REG(0x3B4), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"sub", OP_REG(0x3B4), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Unsigned Integer Subtract */
|
/* Unsigned Integer Subtract */
|
|
|
{"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
|
{"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
|
{"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
/* Write Control Register
|
/* Write Control Register
|
Is a special form of the "swcr" instruction so comes before it in the table. */
|
Is a special form of the "swcr" instruction so comes before it in the table. */
|
|
|
{"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} },
|
{"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} },
|
{"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} },
|
{"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} },
|
{"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} },
|
{"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} },
|
|
|
/* Swap Control Register */
|
/* Swap Control Register */
|
|
|
{"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} },
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{"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} },
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{"swcr", OP_LI(0x30B), MASK_LI, 0, {CR_LI, REG_22, REG_DEST} },
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{"swcr", OP_LI(0x30B), MASK_LI, 0, {CR_LI, REG_22, REG_DEST} },
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{"swcr", OP_REG(0x30A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
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{"swcr", OP_REG(0x30A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
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|
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/* Trap */
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/* Trap */
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|
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{"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} },
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{"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} },
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{"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), 0, {LUI} },
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{"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), 0, {LUI} },
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{"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), 0, {REG_0} },
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{"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), 0, {REG_0} },
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|
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/* Vector Floating-Point Add */
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/* Vector Floating-Point Add */
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{"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} },
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{"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} },
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{"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} },
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{"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} },
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{"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} },
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{"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} },
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{"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
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{"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
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{"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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|
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/* Vector Floating-Point Multiply and Add to Accumulator FIXME! This is not yet fully implemented.
|
/* Vector Floating-Point Multiply and Add to Accumulator FIXME! This is not yet fully implemented.
|
From the documentation there appears to be no way to tell the difference between the opcodes for
|
From the documentation there appears to be no way to tell the difference between the opcodes for
|
instructions that have register destinations and instructions that have accumulator destinations.
|
instructions that have register destinations and instructions that have accumulator destinations.
|
Further investigation is necessary. Since this isn't critical to getting a TIC80 toolchain up
|
Further investigation is necessary. Since this isn't critical to getting a TIC80 toolchain up
|
and running, it is defered until later. */
|
and running, it is defered until later. */
|
|
|
/* Vector Floating-Point Multiply
|
/* Vector Floating-Point Multiply
|
Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */
|
Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */
|
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{"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0_E, REG_22_E, REG_22_E} },
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{"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0_E, REG_22_E, REG_22_E} },
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{"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22_E, REG_22_E} },
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{"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22_E, REG_22_E} },
|
{"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22_E, REG_22_E} },
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{"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22_E, REG_22_E} },
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{"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
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{"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
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{"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
|
{"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
|
|
|
/* Vector Floating-Point Multiply and Subtract from Accumulator
|
/* Vector Floating-Point Multiply and Subtract from Accumulator
|
FIXME: See note above for vmac instruction */
|
FIXME: See note above for vmac instruction */
|
|
|
/* Vector Floating-Point Subtract Accumulator From Source
|
/* Vector Floating-Point Subtract Accumulator From Source
|
FIXME: See note above for vmac instruction */
|
FIXME: See note above for vmac instruction */
|
|
|
/* Vector Round With Floating-Point Input
|
/* Vector Round With Floating-Point Input
|
FIXME: See note above for vmac instruction */
|
FIXME: See note above for vmac instruction */
|
|
|
/* Vector Round with Integer Input */
|
/* Vector Round with Integer Input */
|
|
|
{"vrnd.id", OP_LI (0x3CB) | P2(1) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22_E}},
|
{"vrnd.id", OP_LI (0x3CB) | P2(1) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22_E}},
|
{"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}},
|
{"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}},
|
{"vrnd.is", OP_LI (0x3CB) | P2(0) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}},
|
{"vrnd.is", OP_LI (0x3CB) | P2(0) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}},
|
{"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
|
{"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
|
{"vrnd.ud", OP_LI (0x3CB) | P2(1) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22_E}},
|
{"vrnd.ud", OP_LI (0x3CB) | P2(1) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22_E}},
|
{"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}},
|
{"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}},
|
{"vrnd.us", OP_LI (0x3CB) | P2(0) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}},
|
{"vrnd.us", OP_LI (0x3CB) | P2(0) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}},
|
{"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
|
{"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
|
|
|
/* Vector Floating-Point Subtract */
|
/* Vector Floating-Point Subtract */
|
|
|
{"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} },
|
{"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} },
|
{"vsub.sd", OP_LI(0x3C3) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} },
|
{"vsub.sd", OP_LI(0x3C3) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} },
|
{"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} },
|
{"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} },
|
{"vsub.ss", OP_LI(0x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
|
{"vsub.ss", OP_LI(0x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
|
{"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
|
{"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
|
|
|
/* Vector Load Data Into Register - Note that the vector load/store instructions come after the other
|
/* Vector Load Data Into Register - Note that the vector load/store instructions come after the other
|
vector instructions so that the disassembler will always print the load/store instruction second for
|
vector instructions so that the disassembler will always print the load/store instruction second for
|
vector instructions that have two instructions in the same opcode. */
|
vector instructions that have two instructions in the same opcode. */
|
|
|
{"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
|
{"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
|
{"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
|
{"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
|
{"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
|
{"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
|
{"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
|
{"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
|
|
|
/* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other
|
/* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other
|
vector instructions so that the disassembler will always print the load/store instruction second for
|
vector instructions so that the disassembler will always print the load/store instruction second for
|
vector instructions that have two instructions in the same opcode. */
|
vector instructions that have two instructions in the same opcode. */
|
|
|
{"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
|
{"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
|
{"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
|
{"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
|
|
|
{"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
{"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
|
{"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
|
{"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
{"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
|
|
|
};
|
};
|
|
|
const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
|
const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
|
|
|
