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/* Simulator instruction semantics for iq2000bf.

/* Simulator instruction semantics for iq2000bf.

THIS FILE IS MACHINE GENERATED WITH CGEN.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.

Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.

This file is part of the GNU simulators.

This file is part of the GNU simulators.

This program is free software; you can redistribute it and/or modify

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 3 of the License, or

the Free Software Foundation; either version 3 of the License, or

(at your option) any later version.

(at your option) any later version.

This program is distributed in the hope that it will be useful,

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

You should have received a copy of the GNU General Public License

along with this program.  If not, see <http://www.gnu.org/licenses/>.

along with this program.  If not, see <http://www.gnu.org/licenses/>.

*/

*/

#define WANT_CPU iq2000bf

#define WANT_CPU iq2000bf

#define WANT_CPU_IQ2000BF

#define WANT_CPU_IQ2000BF

#include "sim-main.h"

#include "sim-main.h"

#include "cgen-mem.h"

#include "cgen-mem.h"

#include "cgen-ops.h"

#include "cgen-ops.h"

#undef GET_ATTR

#undef GET_ATTR

#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)

#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)

#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)

#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)

#else

#else

#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)

#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)

#endif

#endif

/* This is used so that we can compile two copies of the semantic code,

/* This is used so that we can compile two copies of the semantic code,

   one with full feature support and one without that runs fast(er).

   one with full feature support and one without that runs fast(er).

   FAST_P, when desired, is defined on the command line, -DFAST_P=1.  */

   FAST_P, when desired, is defined on the command line, -DFAST_P=1.  */

#if FAST_P

#if FAST_P

#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)

#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)

#undef TRACE_RESULT

#undef TRACE_RESULT

#define TRACE_RESULT(cpu, abuf, name, type, val)

#define TRACE_RESULT(cpu, abuf, name, type, val)

#else

#else

#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)

#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)

#endif

#endif

/* x-invalid: --invalid-- */

/* x-invalid: --invalid-- */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.fmt_empty.f

#define FLD(f) abuf->fields.fmt_empty.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

  {

    /* Update the recorded pc in the cpu state struct.

    /* Update the recorded pc in the cpu state struct.

       Only necessary for WITH_SCACHE case, but to avoid the

       Only necessary for WITH_SCACHE case, but to avoid the

       conditional compilation ....  */

       conditional compilation ....  */

    SET_H_PC (pc);

    SET_H_PC (pc);

    /* Virtual insns have zero size.  Overwrite vpc with address of next insn

    /* Virtual insns have zero size.  Overwrite vpc with address of next insn

       using the default-insn-bitsize spec.  When executing insns in parallel

       using the default-insn-bitsize spec.  When executing insns in parallel

       we may want to queue the fault and continue execution.  */

       we may want to queue the fault and continue execution.  */

    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);

    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* x-after: --after-- */

/* x-after: --after-- */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.fmt_empty.f

#define FLD(f) abuf->fields.fmt_empty.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

  {

#if WITH_SCACHE_PBB_IQ2000BF

#if WITH_SCACHE_PBB_IQ2000BF

    iq2000bf_pbb_after (current_cpu, sem_arg);

    iq2000bf_pbb_after (current_cpu, sem_arg);

#endif

#endif

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* x-before: --before-- */

/* x-before: --before-- */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.fmt_empty.f

#define FLD(f) abuf->fields.fmt_empty.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

  {

#if WITH_SCACHE_PBB_IQ2000BF

#if WITH_SCACHE_PBB_IQ2000BF

    iq2000bf_pbb_before (current_cpu, sem_arg);

    iq2000bf_pbb_before (current_cpu, sem_arg);

#endif

#endif

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* x-cti-chain: --cti-chain-- */

/* x-cti-chain: --cti-chain-- */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.fmt_empty.f

#define FLD(f) abuf->fields.fmt_empty.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

  {

#if WITH_SCACHE_PBB_IQ2000BF

#if WITH_SCACHE_PBB_IQ2000BF

#ifdef DEFINE_SWITCH

#ifdef DEFINE_SWITCH

    vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg,

    vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg,

                               pbb_br_type, pbb_br_npc);

                               pbb_br_type, pbb_br_npc);

    BREAK (sem);

    BREAK (sem);

#else

#else

    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */

    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */

    vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg,

    vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg,

                               CPU_PBB_BR_TYPE (current_cpu),

                               CPU_PBB_BR_TYPE (current_cpu),

                               CPU_PBB_BR_NPC (current_cpu));

                               CPU_PBB_BR_NPC (current_cpu));

#endif

#endif

#endif

#endif

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* x-chain: --chain-- */

/* x-chain: --chain-- */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.fmt_empty.f

#define FLD(f) abuf->fields.fmt_empty.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

  {

#if WITH_SCACHE_PBB_IQ2000BF

#if WITH_SCACHE_PBB_IQ2000BF

    vpc = iq2000bf_pbb_chain (current_cpu, sem_arg);

    vpc = iq2000bf_pbb_chain (current_cpu, sem_arg);

#ifdef DEFINE_SWITCH

#ifdef DEFINE_SWITCH

    BREAK (sem);

    BREAK (sem);

#endif

#endif

#endif

#endif

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* x-begin: --begin-- */

/* x-begin: --begin-- */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.fmt_empty.f

#define FLD(f) abuf->fields.fmt_empty.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

  {

#if WITH_SCACHE_PBB_IQ2000BF

#if WITH_SCACHE_PBB_IQ2000BF

#if defined DEFINE_SWITCH || defined FAST_P

#if defined DEFINE_SWITCH || defined FAST_P

    /* In the switch case FAST_P is a constant, allowing several optimizations

    /* In the switch case FAST_P is a constant, allowing several optimizations

       in any called inline functions.  */

       in any called inline functions.  */

    vpc = iq2000bf_pbb_begin (current_cpu, FAST_P);

    vpc = iq2000bf_pbb_begin (current_cpu, FAST_P);

#else

#else

#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */

#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */

    vpc = iq2000bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));

    vpc = iq2000bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));

#else

#else

    vpc = iq2000bf_pbb_begin (current_cpu, 0);

    vpc = iq2000bf_pbb_begin (current_cpu, 0);

#endif

#endif

#endif

#endif

#endif

#endif

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* add: add $rd,$rs,$rt */

/* add: add $rd,$rs,$rt */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_mrgb.f

#define FLD(f) abuf->fields.sfmt_mrgb.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));

    SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* addi: addi $rt,$rs,$lo16 */

/* addi: addi $rt,$rs,$lo16 */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_addi.f

#define FLD(f) abuf->fields.sfmt_addi.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))));

    SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))));

    SET_H_GR (FLD (f_rt), opval);

    SET_H_GR (FLD (f_rt), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* addiu: addiu $rt,$rs,$lo16 */

/* addiu: addiu $rt,$rs,$lo16 */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,addiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,addiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_addi.f

#define FLD(f) abuf->fields.sfmt_addi.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))));

    SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))));

    SET_H_GR (FLD (f_rt), opval);

    SET_H_GR (FLD (f_rt), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* addu: addu $rd,$rs,$rt */

/* addu: addu $rd,$rs,$rt */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,addu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,addu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_mrgb.f

#define FLD(f) abuf->fields.sfmt_mrgb.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));

    SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* ado16: ado16 $rd,$rs,$rt */

/* ado16: ado16 $rd,$rs,$rt */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,ado16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,ado16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_mrgb.f

#define FLD(f) abuf->fields.sfmt_mrgb.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

{

{

  HI tmp_high;

  HI tmp_high;

  HI tmp_low;

  HI tmp_low;

  tmp_low = ADDHI (ANDHI (GET_H_GR (FLD (f_rs)), 65535), ANDHI (GET_H_GR (FLD (f_rt)), 65535));

  tmp_low = ADDHI (ANDHI (GET_H_GR (FLD (f_rs)), 65535), ANDHI (GET_H_GR (FLD (f_rt)), 65535));

  tmp_high = ADDHI (SRLSI (GET_H_GR (FLD (f_rs)), 16), SRLSI (GET_H_GR (FLD (f_rt)), 16));

  tmp_high = ADDHI (SRLSI (GET_H_GR (FLD (f_rs)), 16), SRLSI (GET_H_GR (FLD (f_rt)), 16));

  {

  {

    SI opval = ORSI (SLLSI (tmp_high, 16), tmp_low);

    SI opval = ORSI (SLLSI (tmp_high, 16), tmp_low);

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

}

}

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* and: and $rd,$rs,$rt */

/* and: and $rd,$rs,$rt */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_mrgb.f

#define FLD(f) abuf->fields.sfmt_mrgb.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ANDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));

    SI opval = ANDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* andi: andi $rt,$rs,$lo16 */

/* andi: andi $rt,$rs,$lo16 */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_addi.f

#define FLD(f) abuf->fields.sfmt_addi.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm)));

    SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm)));

    SET_H_GR (FLD (f_rt), opval);

    SET_H_GR (FLD (f_rt), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* andoi: andoi $rt,$rs,$lo16 */

/* andoi: andoi $rt,$rs,$lo16 */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,andoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,andoi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_addi.f

#define FLD(f) abuf->fields.sfmt_addi.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (0xffff0000, EXTHISI (TRUNCSIHI (FLD (f_imm)))));

    SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (0xffff0000, EXTHISI (TRUNCSIHI (FLD (f_imm)))));

    SET_H_GR (FLD (f_rt), opval);

    SET_H_GR (FLD (f_rt), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* nor: nor $rd,$rs,$rt */

/* nor: nor $rd,$rs,$rt */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,nor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,nor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_mrgb.f

#define FLD(f) abuf->fields.sfmt_mrgb.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = INVSI (ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))));

    SI opval = INVSI (ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* or: or $rd,$rs,$rt */

/* or: or $rd,$rs,$rt */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_mrgb.f

#define FLD(f) abuf->fields.sfmt_mrgb.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));

    SI opval = ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* ori: ori $rt,$rs,$lo16 */

/* ori: ori $rt,$rs,$lo16 */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_addi.f

#define FLD(f) abuf->fields.sfmt_addi.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm)));

    SI opval = ORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm)));

    SET_H_GR (FLD (f_rt), opval);

    SET_H_GR (FLD (f_rt), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* ram: ram $rd,$rt,$shamt,$maskl,$maskr */

/* ram: ram $rd,$rt,$shamt,$maskl,$maskr */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,ram) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,ram) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_ram.f

#define FLD(f) abuf->fields.sfmt_ram.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

{

{

  {

  {

    SI opval = RORSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt));

    SI opval = RORSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  {

  {

    SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SRLSI (0xffffffff, FLD (f_maskl)));

    SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SRLSI (0xffffffff, FLD (f_maskl)));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  {

  {

    SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SLLSI (0xffffffff, FLD (f_rs)));

    SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SLLSI (0xffffffff, FLD (f_rs)));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

}

}

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* sll: sll $rd,$rt,$shamt */

/* sll: sll $rd,$rt,$shamt */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_ram.f

#define FLD(f) abuf->fields.sfmt_ram.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt));

    SI opval = SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* sllv: sllv $rd,$rt,$rs */

/* sllv: sllv $rd,$rt,$rs */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,sllv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,sllv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_mrgb.f

#define FLD(f) abuf->fields.sfmt_mrgb.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = SLLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31));

    SI opval = SLLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD

}

}

/* slmv: slmv $rd,$rt,$rs,$shamt */

/* slmv: slmv $rd,$rt,$rs,$shamt */

static SEM_PC

static SEM_PC

SEM_FN_NAME (iq2000bf,slmv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

SEM_FN_NAME (iq2000bf,slmv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)

{

{

#define FLD(f) abuf->fields.sfmt_ram.f

#define FLD(f) abuf->fields.sfmt_ram.f

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

  int UNUSED written = 0;

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  IADDR UNUSED pc = abuf->addr;

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);

  {

  {

    SI opval = ANDSI (SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SRLSI (0xffffffff, GET_H_GR (FLD (f_rs))));

    SI opval = ANDSI (SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SRLSI (0xffffffff, GET_H_GR (FLD (f_rs))));

    SET_H_GR (FLD (f_rd), opval);

    SET_H_GR (FLD (f_rd), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

  }

  return vpc;

  return vpc;

#undef FLD

#undef FLD