OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [m32r/] [cpu.c] - Diff between revs 827 and 840

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 827 Rev 840
/* Misc. support for CPU family m32rbf.
/* Misc. support for CPU family m32rbf.
 
 
THIS FILE IS MACHINE GENERATED WITH CGEN.
THIS FILE IS MACHINE GENERATED WITH CGEN.
 
 
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
 
 
This file is part of the GNU simulators.
This file is part of the GNU simulators.
 
 
This program is free software; you can redistribute it and/or modify
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
(at your option) any later version.
 
 
This program is distributed in the hope that it will be useful,
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
GNU General Public License for more details.
 
 
You should have received a copy of the GNU General Public License
You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.
along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
 
*/
*/
 
 
#define WANT_CPU m32rbf
#define WANT_CPU m32rbf
#define WANT_CPU_M32RBF
#define WANT_CPU_M32RBF
 
 
#include "sim-main.h"
#include "sim-main.h"
#include "cgen-ops.h"
#include "cgen-ops.h"
 
 
/* Get the value of h-pc.  */
/* Get the value of h-pc.  */
 
 
USI
USI
m32rbf_h_pc_get (SIM_CPU *current_cpu)
m32rbf_h_pc_get (SIM_CPU *current_cpu)
{
{
  return CPU (h_pc);
  return CPU (h_pc);
}
}
 
 
/* Set a value for h-pc.  */
/* Set a value for h-pc.  */
 
 
void
void
m32rbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
m32rbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
{
{
  CPU (h_pc) = newval;
  CPU (h_pc) = newval;
}
}
 
 
/* Get the value of h-gr.  */
/* Get the value of h-gr.  */
 
 
SI
SI
m32rbf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
m32rbf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
{
  return CPU (h_gr[regno]);
  return CPU (h_gr[regno]);
}
}
 
 
/* Set a value for h-gr.  */
/* Set a value for h-gr.  */
 
 
void
void
m32rbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
m32rbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
{
  CPU (h_gr[regno]) = newval;
  CPU (h_gr[regno]) = newval;
}
}
 
 
/* Get the value of h-cr.  */
/* Get the value of h-cr.  */
 
 
USI
USI
m32rbf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
m32rbf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
{
  return GET_H_CR (regno);
  return GET_H_CR (regno);
}
}
 
 
/* Set a value for h-cr.  */
/* Set a value for h-cr.  */
 
 
void
void
m32rbf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
m32rbf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
{
{
  SET_H_CR (regno, newval);
  SET_H_CR (regno, newval);
}
}
 
 
/* Get the value of h-accum.  */
/* Get the value of h-accum.  */
 
 
DI
DI
m32rbf_h_accum_get (SIM_CPU *current_cpu)
m32rbf_h_accum_get (SIM_CPU *current_cpu)
{
{
  return GET_H_ACCUM ();
  return GET_H_ACCUM ();
}
}
 
 
/* Set a value for h-accum.  */
/* Set a value for h-accum.  */
 
 
void
void
m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
{
{
  SET_H_ACCUM (newval);
  SET_H_ACCUM (newval);
}
}
 
 
/* Get the value of h-cond.  */
/* Get the value of h-cond.  */
 
 
BI
BI
m32rbf_h_cond_get (SIM_CPU *current_cpu)
m32rbf_h_cond_get (SIM_CPU *current_cpu)
{
{
  return CPU (h_cond);
  return CPU (h_cond);
}
}
 
 
/* Set a value for h-cond.  */
/* Set a value for h-cond.  */
 
 
void
void
m32rbf_h_cond_set (SIM_CPU *current_cpu, BI newval)
m32rbf_h_cond_set (SIM_CPU *current_cpu, BI newval)
{
{
  CPU (h_cond) = newval;
  CPU (h_cond) = newval;
}
}
 
 
/* Get the value of h-psw.  */
/* Get the value of h-psw.  */
 
 
UQI
UQI
m32rbf_h_psw_get (SIM_CPU *current_cpu)
m32rbf_h_psw_get (SIM_CPU *current_cpu)
{
{
  return GET_H_PSW ();
  return GET_H_PSW ();
}
}
 
 
/* Set a value for h-psw.  */
/* Set a value for h-psw.  */
 
 
void
void
m32rbf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
m32rbf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
{
{
  SET_H_PSW (newval);
  SET_H_PSW (newval);
}
}
 
 
/* Get the value of h-bpsw.  */
/* Get the value of h-bpsw.  */
 
 
UQI
UQI
m32rbf_h_bpsw_get (SIM_CPU *current_cpu)
m32rbf_h_bpsw_get (SIM_CPU *current_cpu)
{
{
  return CPU (h_bpsw);
  return CPU (h_bpsw);
}
}
 
 
/* Set a value for h-bpsw.  */
/* Set a value for h-bpsw.  */
 
 
void
void
m32rbf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
m32rbf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
{
{
  CPU (h_bpsw) = newval;
  CPU (h_bpsw) = newval;
}
}
 
 
/* Get the value of h-bbpsw.  */
/* Get the value of h-bbpsw.  */
 
 
UQI
UQI
m32rbf_h_bbpsw_get (SIM_CPU *current_cpu)
m32rbf_h_bbpsw_get (SIM_CPU *current_cpu)
{
{
  return CPU (h_bbpsw);
  return CPU (h_bbpsw);
}
}
 
 
/* Set a value for h-bbpsw.  */
/* Set a value for h-bbpsw.  */
 
 
void
void
m32rbf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
m32rbf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
{
{
  CPU (h_bbpsw) = newval;
  CPU (h_bbpsw) = newval;
}
}
 
 
/* Get the value of h-lock.  */
/* Get the value of h-lock.  */
 
 
BI
BI
m32rbf_h_lock_get (SIM_CPU *current_cpu)
m32rbf_h_lock_get (SIM_CPU *current_cpu)
{
{
  return CPU (h_lock);
  return CPU (h_lock);
}
}
 
 
/* Set a value for h-lock.  */
/* Set a value for h-lock.  */
 
 
void
void
m32rbf_h_lock_set (SIM_CPU *current_cpu, BI newval)
m32rbf_h_lock_set (SIM_CPU *current_cpu, BI newval)
{
{
  CPU (h_lock) = newval;
  CPU (h_lock) = newval;
}
}
 
 
/* Record trace results for INSN.  */
/* Record trace results for INSN.  */
 
 
void
void
m32rbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
m32rbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
                            int *indices, TRACE_RECORD *tr)
                            int *indices, TRACE_RECORD *tr)
{
{
}
}
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.