// Helper:
|
// Helper:
|
//
|
//
|
// Given an extended register number, translate it into an index into the
|
// Given an extended register number, translate it into an index into the
|
// register array. This is necessary as the upper 8 extended registers are
|
// register array. This is necessary as the upper 8 extended registers are
|
// actually synonyms for the d0-d3/a0-a3 registers.
|
// actually synonyms for the d0-d3/a0-a3 registers.
|
//
|
//
|
//
|
//
|
|
|
:function:::int:translate_rreg:int rreg
|
:function:::int:translate_rreg:int rreg
|
{
|
{
|
|
|
/* The higher register numbers actually correspond to the
|
/* The higher register numbers actually correspond to the
|
basic machine's address and data registers. */
|
basic machine's address and data registers. */
|
if (rreg > 7 && rreg < 12)
|
if (rreg > 7 && rreg < 12)
|
return REG_A0 + rreg - 8;
|
return REG_A0 + rreg - 8;
|
else if (rreg > 11 && rreg < 16)
|
else if (rreg > 11 && rreg < 16)
|
return REG_D0 + rreg - 12;
|
return REG_D0 + rreg - 12;
|
else
|
else
|
return REG_E0 + rreg;
|
return REG_E0 + rreg;
|
}
|
}
|
|
|
:function:::int:translate_xreg:int xreg
|
:function:::int:translate_xreg:int xreg
|
{
|
{
|
switch (xreg)
|
switch (xreg)
|
{
|
{
|
case 0:
|
case 0:
|
return REG_SP;
|
return REG_SP;
|
case 1:
|
case 1:
|
return REG_MDRQ;
|
return REG_MDRQ;
|
case 2:
|
case 2:
|
return REG_MCRH;
|
return REG_MCRH;
|
case 3:
|
case 3:
|
return REG_MCRL;
|
return REG_MCRL;
|
case 4:
|
case 4:
|
return REG_MCVF;
|
return REG_MCVF;
|
default:
|
default:
|
sim_engine_abort (SD, CPU, cia, "%s:%d: bad switch\n", __FILE__, __LINE__);
|
sim_engine_abort (SD, CPU, cia, "%s:%d: bad switch\n", __FILE__, __LINE__);
|
}
|
}
|
}
|
}
|
|
|
// 1111 0000 0010 00An; mov USP,An
|
// 1111 0000 0010 00An; mov USP,An
|
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
|
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
State.regs[REG_A0 + AN0] = State.regs[REG_USP];
|
State.regs[REG_A0 + AN0] = State.regs[REG_USP];
|
}
|
}
|
|
|
|
|
// 1111 0000 0010 01An; mov SSP,An
|
// 1111 0000 0010 01An; mov SSP,An
|
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
|
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
|
State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
|
}
|
}
|
|
|
|
|
// 1111 0000 0010 10An; mov MSP,An
|
// 1111 0000 0010 10An; mov MSP,An
|
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
|
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
|
State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
|
}
|
}
|
|
|
|
|
// 1111 0000 0010 11An; mov PC,An
|
// 1111 0000 0010 11An; mov PC,An
|
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
|
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
State.regs[REG_A0 + AN0] = PC;
|
State.regs[REG_A0 + AN0] = PC;
|
}
|
}
|
|
|
|
|
// 1111 0000 0011 Am00; mov Am,USP
|
// 1111 0000 0011 Am00; mov Am,USP
|
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
|
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
State.regs[REG_USP] = State.regs[REG_A0 + AM1];
|
State.regs[REG_USP] = State.regs[REG_A0 + AM1];
|
}
|
}
|
|
|
// 1111 0000 0011 Am01; mov Am,SSP
|
// 1111 0000 0011 Am01; mov Am,SSP
|
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
|
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
|
State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
|
}
|
}
|
|
|
// 1111 0000 0011 Am10; mov Am,MSP
|
// 1111 0000 0011 Am10; mov Am,MSP
|
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
|
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
|
State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
|
}
|
}
|
|
|
|
|
// 1111 0000 1110 imm4; syscall
|
// 1111 0000 1110 imm4; syscall
|
8.0xf0+4.0xe,IMM4:D0t:::syscall
|
8.0xf0+4.0xe,IMM4:D0t:::syscall
|
"syscall"
|
"syscall"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
unsigned32 sp, next_pc;
|
unsigned32 sp, next_pc;
|
|
|
PC = cia;
|
PC = cia;
|
sp = State.regs[REG_SP];
|
sp = State.regs[REG_SP];
|
next_pc = State.regs[REG_PC] + 2;
|
next_pc = State.regs[REG_PC] + 2;
|
store_word (sp - 4, next_pc);
|
store_word (sp - 4, next_pc);
|
store_word (sp - 8, PSW);
|
store_word (sp - 8, PSW);
|
State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
|
State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
|
|
|
|
// 1111 0010 1110 11Dn; mov EPSW,Dn
|
// 1111 0010 1110 11Dn; mov EPSW,Dn
|
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
|
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
State.regs[REG_D0 + DN0] = PSW;
|
State.regs[REG_D0 + DN0] = PSW;
|
}
|
}
|
|
|
|
|
// 1111 0010 1111 Dm01; mov Dm,EPSW
|
// 1111 0010 1111 Dm01; mov Dm,EPSW
|
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
|
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
PSW = State.regs[REG_D0 + DM1];
|
PSW = State.regs[REG_D0 + DM1];
|
}
|
}
|
|
|
// 1111 0101 00Am Rn; mov Am,Rn
|
// 1111 0101 00Am Rn; mov Am,Rn
|
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
|
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int destreg = translate_rreg (SD_, RN0);
|
int destreg = translate_rreg (SD_, RN0);
|
|
|
PC = cia;
|
PC = cia;
|
State.regs[destreg] = State.regs[REG_A0 + AM1];
|
State.regs[destreg] = State.regs[REG_A0 + AM1];
|
}
|
}
|
|
|
// 1111 0101 01Dm Rn; mov Dm,Rn
|
// 1111 0101 01Dm Rn; mov Dm,Rn
|
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
|
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int destreg = translate_rreg (SD_, RN0);
|
int destreg = translate_rreg (SD_, RN0);
|
|
|
PC = cia;
|
PC = cia;
|
State.regs[destreg] = State.regs[REG_D0 + DM1];
|
State.regs[destreg] = State.regs[REG_D0 + DM1];
|
}
|
}
|
|
|
// 1111 0101 10Rm An; mov Rm,An
|
// 1111 0101 10Rm An; mov Rm,An
|
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
|
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int destreg = translate_rreg (SD_, RM1);
|
int destreg = translate_rreg (SD_, RM1);
|
|
|
PC = cia;
|
PC = cia;
|
State.regs[REG_A0 + AN0] = State.regs[destreg];
|
State.regs[REG_A0 + AN0] = State.regs[destreg];
|
}
|
}
|
|
|
// 1111 0101 11Rm Dn; mov Rm,Dn
|
// 1111 0101 11Rm Dn; mov Rm,Dn
|
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
|
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int destreg = translate_rreg (SD_, RM1);
|
int destreg = translate_rreg (SD_, RM1);
|
|
|
PC = cia;
|
PC = cia;
|
State.regs[REG_D0 + DN0] = State.regs[destreg];
|
State.regs[REG_D0 + DN0] = State.regs[destreg];
|
}
|
}
|
|
|
|
|
// 1111 1000 1100 1110 regs....; movm (USP),regs
|
// 1111 1000 1100 1110 regs....; movm (USP),regs
|
8.0xf8+8.0xce+8.REGS:D1a:::movm
|
8.0xf8+8.0xce+8.REGS:D1a:::movm
|
"movm"
|
"movm"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
unsigned32 usp = State.regs[REG_USP];
|
unsigned32 usp = State.regs[REG_USP];
|
unsigned32 mask;
|
unsigned32 mask;
|
|
|
PC = cia;
|
PC = cia;
|
mask = REGS;
|
mask = REGS;
|
|
|
if (mask & 0x8)
|
if (mask & 0x8)
|
{
|
{
|
usp += 4;
|
usp += 4;
|
State.regs[REG_LAR] = load_word (usp);
|
State.regs[REG_LAR] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_LIR] = load_word (usp);
|
State.regs[REG_LIR] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_MDR] = load_word (usp);
|
State.regs[REG_MDR] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_A0 + 1] = load_word (usp);
|
State.regs[REG_A0 + 1] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_A0] = load_word (usp);
|
State.regs[REG_A0] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_D0 + 1] = load_word (usp);
|
State.regs[REG_D0 + 1] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_D0] = load_word (usp);
|
State.regs[REG_D0] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
}
|
}
|
|
|
if (mask & 0x10)
|
if (mask & 0x10)
|
{
|
{
|
State.regs[REG_A0 + 3] = load_word (usp);
|
State.regs[REG_A0 + 3] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
}
|
}
|
|
|
if (mask & 0x20)
|
if (mask & 0x20)
|
{
|
{
|
State.regs[REG_A0 + 2] = load_word (usp);
|
State.regs[REG_A0 + 2] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
}
|
}
|
|
|
if (mask & 0x40)
|
if (mask & 0x40)
|
{
|
{
|
State.regs[REG_D0 + 3] = load_word (usp);
|
State.regs[REG_D0 + 3] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
}
|
}
|
|
|
if (mask & 0x80)
|
if (mask & 0x80)
|
{
|
{
|
State.regs[REG_D0 + 2] = load_word (usp);
|
State.regs[REG_D0 + 2] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
}
|
}
|
|
|
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
|
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
|
|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
|
|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
|
)
|
)
|
{
|
{
|
if (mask & 0x1)
|
if (mask & 0x1)
|
{
|
{
|
/* Need to restore MDQR, MCRH, MCRL, and MCVF */
|
/* Need to restore MDQR, MCRH, MCRL, and MCVF */
|
usp += 16;
|
usp += 16;
|
State.regs[REG_E0 + 1] = load_word (usp);
|
State.regs[REG_E0 + 1] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_E0 + 0] = load_word (usp);
|
State.regs[REG_E0 + 0] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
}
|
}
|
|
|
if (mask & 0x2)
|
if (mask & 0x2)
|
{
|
{
|
State.regs[REG_E0 + 7] = load_word (usp);
|
State.regs[REG_E0 + 7] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_E0 + 6] = load_word (usp);
|
State.regs[REG_E0 + 6] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_E0 + 5] = load_word (usp);
|
State.regs[REG_E0 + 5] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_E0 + 4] = load_word (usp);
|
State.regs[REG_E0 + 4] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
}
|
}
|
|
|
if (mask & 0x4)
|
if (mask & 0x4)
|
{
|
{
|
State.regs[REG_E0 + 3] = load_word (usp);
|
State.regs[REG_E0 + 3] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
State.regs[REG_E0 + 2] = load_word (usp);
|
State.regs[REG_E0 + 2] = load_word (usp);
|
usp += 4;
|
usp += 4;
|
}
|
}
|
}
|
}
|
|
|
/* And make sure to update the stack pointer. */
|
/* And make sure to update the stack pointer. */
|
State.regs[REG_USP] = usp;
|
State.regs[REG_USP] = usp;
|
}
|
}
|
|
|
// 1111 1000 1100 1111 regs....; movm (USP),regs
|
// 1111 1000 1100 1111 regs....; movm (USP),regs
|
8.0xf8+8.0xcf+8.REGS:D1b:::movm
|
8.0xf8+8.0xcf+8.REGS:D1b:::movm
|
"movm"
|
"movm"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
unsigned32 usp = State.regs[REG_USP];
|
unsigned32 usp = State.regs[REG_USP];
|
unsigned32 mask;
|
unsigned32 mask;
|
|
|
PC = cia;
|
PC = cia;
|
mask = REGS;
|
mask = REGS;
|
|
|
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
|
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
|
|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
|
|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
|
)
|
)
|
{
|
{
|
if (mask & 0x4)
|
if (mask & 0x4)
|
{
|
{
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_E0 + 2]);
|
store_word (usp, State.regs[REG_E0 + 2]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_E0 + 3]);
|
store_word (usp, State.regs[REG_E0 + 3]);
|
}
|
}
|
|
|
if (mask & 0x2)
|
if (mask & 0x2)
|
{
|
{
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_E0 + 4]);
|
store_word (usp, State.regs[REG_E0 + 4]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_E0 + 5]);
|
store_word (usp, State.regs[REG_E0 + 5]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_E0 + 6]);
|
store_word (usp, State.regs[REG_E0 + 6]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_E0 + 7]);
|
store_word (usp, State.regs[REG_E0 + 7]);
|
}
|
}
|
|
|
if (mask & 0x1)
|
if (mask & 0x1)
|
{
|
{
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_E0 + 0]);
|
store_word (usp, State.regs[REG_E0 + 0]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_E0 + 1]);
|
store_word (usp, State.regs[REG_E0 + 1]);
|
usp -= 16;
|
usp -= 16;
|
/* Need to save MDQR, MCRH, MCRL, and MCVF */
|
/* Need to save MDQR, MCRH, MCRL, and MCVF */
|
}
|
}
|
}
|
}
|
|
|
if (mask & 0x80)
|
if (mask & 0x80)
|
{
|
{
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_D0 + 2]);
|
store_word (usp, State.regs[REG_D0 + 2]);
|
}
|
}
|
|
|
if (mask & 0x40)
|
if (mask & 0x40)
|
{
|
{
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_D0 + 3]);
|
store_word (usp, State.regs[REG_D0 + 3]);
|
}
|
}
|
|
|
if (mask & 0x20)
|
if (mask & 0x20)
|
{
|
{
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_A0 + 2]);
|
store_word (usp, State.regs[REG_A0 + 2]);
|
}
|
}
|
|
|
if (mask & 0x10)
|
if (mask & 0x10)
|
{
|
{
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_A0 + 3]);
|
store_word (usp, State.regs[REG_A0 + 3]);
|
}
|
}
|
|
|
if (mask & 0x8)
|
if (mask & 0x8)
|
{
|
{
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_D0]);
|
store_word (usp, State.regs[REG_D0]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_D0 + 1]);
|
store_word (usp, State.regs[REG_D0 + 1]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_A0]);
|
store_word (usp, State.regs[REG_A0]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_A0 + 1]);
|
store_word (usp, State.regs[REG_A0 + 1]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_MDR]);
|
store_word (usp, State.regs[REG_MDR]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_LIR]);
|
store_word (usp, State.regs[REG_LIR]);
|
usp -= 4;
|
usp -= 4;
|
store_word (usp, State.regs[REG_LAR]);
|
store_word (usp, State.regs[REG_LAR]);
|
usp -= 4;
|
usp -= 4;
|
}
|
}
|
|
|
/* And make sure to update the stack pointer. */
|
/* And make sure to update the stack pointer. */
|
State.regs[REG_USP] = usp;
|
State.regs[REG_USP] = usp;
|
}
|
}
|
|
|
// 1111 1100 1111 1100 imm32...; and imm32,EPSW
|
// 1111 1100 1111 1100 imm32...; and imm32,EPSW
|
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
|
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
|
"and"
|
"and"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
}
|
}
|
|
|
// 1111 1100 1111 1101 imm32...; or imm32,EPSW
|
// 1111 1100 1111 1101 imm32...; or imm32,EPSW
|
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
|
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
|
"or"
|
"or"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
PC = cia;
|
PC = cia;
|
PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
}
|
}
|
|
|
// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
|
// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
|
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
|
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
|
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = State.regs[srcreg];
|
State.regs[dstreg] = State.regs[srcreg];
|
}
|
}
|
|
|
// 1111 1001 0001 1000 Rn Rn; ext Rn
|
// 1111 1001 0001 1000 Rn Rn; ext Rn
|
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
|
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
if (State.regs[srcreg] & 0x80000000)
|
if (State.regs[srcreg] & 0x80000000)
|
State.regs[REG_MDR] = -1;
|
State.regs[REG_MDR] = -1;
|
else
|
else
|
State.regs[REG_MDR] = 0;
|
State.regs[REG_MDR] = 0;
|
}
|
}
|
|
|
// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
|
// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
|
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
|
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
|
"extb"
|
"extb"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
|
State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
|
// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
|
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
|
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
|
"extbu"
|
"extbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = State.regs[srcreg] & 0xff;
|
State.regs[dstreg] = State.regs[srcreg] & 0xff;
|
}
|
}
|
|
|
// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
|
// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
|
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
|
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
|
"exth"
|
"exth"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
|
State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
|
// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
|
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
|
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
|
"exthu"
|
"exthu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = State.regs[srcreg] & 0xffff;
|
State.regs[dstreg] = State.regs[srcreg] & 0xffff;
|
}
|
}
|
|
|
// 1111 1001 0110 1000 Rn Rn; clr Rn
|
// 1111 1001 0110 1000 Rn Rn; clr Rn
|
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
|
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
|
"clr"
|
"clr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = 0;
|
State.regs[dstreg] = 0;
|
PSW |= PSW_Z;
|
PSW |= PSW_Z;
|
PSW &= ~(PSW_V | PSW_C | PSW_N);
|
PSW &= ~(PSW_V | PSW_C | PSW_N);
|
}
|
}
|
|
|
// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
|
// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
|
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
|
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
|
"add"
|
"add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
genericAdd (State.regs[srcreg], dstreg);
|
genericAdd (State.regs[srcreg], dstreg);
|
}
|
}
|
|
|
// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
|
// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
|
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
|
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
|
"addc"
|
"addc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int z, c, n, v;
|
int z, c, n, v;
|
unsigned32 reg1, reg2, sum;
|
unsigned32 reg1, reg2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
reg1 = State.regs[srcreg];
|
reg1 = State.regs[srcreg];
|
reg2 = State.regs[dstreg];
|
reg2 = State.regs[dstreg];
|
sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
|
sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
|
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
n = (sum & 0x80000000);
|
n = (sum & 0x80000000);
|
c = (sum < reg1) || (sum < reg2);
|
c = (sum < reg1) || (sum < reg2);
|
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
|
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
|
&& (reg2 & 0x80000000) != (sum & 0x80000000));
|
&& (reg2 & 0x80000000) != (sum & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
|
// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
|
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
|
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
|
"sub"
|
"sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
genericSub (State.regs[srcreg], dstreg);
|
genericSub (State.regs[srcreg], dstreg);
|
}
|
}
|
|
|
// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
|
// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
|
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
|
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
|
"subc"
|
"subc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int z, c, n, v;
|
int z, c, n, v;
|
unsigned32 reg1, reg2, difference;
|
unsigned32 reg1, reg2, difference;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
reg1 = State.regs[srcreg];
|
reg1 = State.regs[srcreg];
|
reg2 = State.regs[dstreg];
|
reg2 = State.regs[dstreg];
|
difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
|
difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = difference;
|
State.regs[dstreg] = difference;
|
|
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
n = (difference & 0x80000000);
|
n = (difference & 0x80000000);
|
c = (reg1 > reg2);
|
c = (reg1 > reg2);
|
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
|
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
|
&& (reg2 & 0x80000000) != (difference & 0x80000000));
|
&& (reg2 & 0x80000000) != (difference & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1001 1011 1000 Rn Rn; inc Rn
|
// 1111 1001 1011 1000 Rn Rn; inc Rn
|
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
|
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
|
"inc"
|
"inc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
genericAdd (1, dstreg);
|
genericAdd (1, dstreg);
|
}
|
}
|
|
|
// 1111 1001 1101 1000 Rn Rn; inc Rn
|
// 1111 1001 1101 1000 Rn Rn; inc Rn
|
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
|
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
|
"inc4"
|
"inc4"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
genericAdd (4, dstreg);
|
genericAdd (4, dstreg);
|
}
|
}
|
|
|
// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
|
// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
|
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
|
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
|
"cmp"
|
"cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2;
|
int srcreg1, srcreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RN0);
|
srcreg1 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
|
genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
|
}
|
}
|
|
|
// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
|
// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
|
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
|
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg, srcreg;
|
int dstreg, srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
srcreg = translate_xreg (SD_, XRM2);
|
srcreg = translate_xreg (SD_, XRM2);
|
|
|
State.regs[dstreg] = State.regs[srcreg];
|
State.regs[dstreg] = State.regs[srcreg];
|
}
|
}
|
|
|
// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
|
// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
|
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
|
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_xreg (SD_, XRN0);
|
dstreg = translate_xreg (SD_, XRN0);
|
|
|
State.regs[dstreg] = State.regs[srcreg];
|
State.regs[dstreg] = State.regs[srcreg];
|
}
|
}
|
|
|
// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
|
// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
|
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
|
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
|
"and"
|
"and"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
|
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] &= State.regs[srcreg];
|
State.regs[dstreg] &= State.regs[srcreg];
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
|
// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
|
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
|
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
|
"or"
|
"or"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] |= State.regs[srcreg];
|
State.regs[dstreg] |= State.regs[srcreg];
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
|
// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
|
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
|
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
|
"xor"
|
"xor"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] ^= State.regs[srcreg];
|
State.regs[dstreg] ^= State.regs[srcreg];
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 0011 1001 Rn Rn; not Rn
|
// 1111 1001 0011 1001 Rn Rn; not Rn
|
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
|
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
|
"not"
|
"not"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] = ~State.regs[dstreg];
|
State.regs[dstreg] = ~State.regs[dstreg];
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
|
// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
|
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
|
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
|
"asr"
|
"asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
signed32 temp;
|
signed32 temp;
|
int c, z, n;
|
int c, z, n;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = State.regs[dstreg];
|
temp = State.regs[dstreg];
|
c = temp & 1;
|
c = temp & 1;
|
temp >>= State.regs[srcreg];
|
temp >>= State.regs[srcreg];
|
State.regs[dstreg] = temp;
|
State.regs[dstreg] = temp;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
|
// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
|
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
|
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
|
"lsr"
|
"lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int z, n, c;
|
int z, n, c;
|
|
|
PC = cia;
|
PC = cia;
|
|
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
c = State.regs[dstreg] & 1;
|
c = State.regs[dstreg] & 1;
|
State.regs[dstreg] >>= State.regs[srcreg];
|
State.regs[dstreg] >>= State.regs[srcreg];
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
|
// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
|
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
|
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
|
"asl"
|
"asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] <<= State.regs[srcreg];
|
State.regs[dstreg] <<= State.regs[srcreg];
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 0111 1001 Rn Rn; asl2 Rn
|
// 1111 1001 0111 1001 Rn Rn; asl2 Rn
|
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
|
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
|
"asl2"
|
"asl2"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int n, z;
|
int n, z;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] <<= 2;
|
State.regs[dstreg] <<= 2;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 1000 1001 Rn Rn; ror Rn
|
// 1111 1001 1000 1001 Rn Rn; ror Rn
|
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
|
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
|
"ror"
|
"ror"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int c, n, z;
|
int c, n, z;
|
unsigned32 value;
|
unsigned32 value;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
value = State.regs[dstreg];
|
value = State.regs[dstreg];
|
c = (value & 0x1);
|
c = (value & 0x1);
|
|
|
value >>= 1;
|
value >>= 1;
|
value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
|
value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
|
State.regs[dstreg] = value;
|
State.regs[dstreg] = value;
|
z = (value == 0);
|
z = (value == 0);
|
n = (value & 0x80000000) != 0;
|
n = (value & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
// 1111 1001 1001 1001 Rn Rn; rol Rn
|
// 1111 1001 1001 1001 Rn Rn; rol Rn
|
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
|
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
|
"rol"
|
"rol"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int c, n, z;
|
int c, n, z;
|
unsigned32 value;
|
unsigned32 value;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
value = State.regs[dstreg];
|
value = State.regs[dstreg];
|
c = (value & 0x80000000) ? 1 : 0;
|
c = (value & 0x80000000) ? 1 : 0;
|
|
|
value <<= 1;
|
value <<= 1;
|
value |= ((PSW & PSW_C) != 0);
|
value |= ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = value;
|
State.regs[dstreg] = value;
|
z = (value == 0);
|
z = (value == 0);
|
n = (value & 0x80000000) != 0;
|
n = (value & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
|
// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
|
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
|
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
|
"mul"
|
"mul"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
unsigned64 temp;
|
unsigned64 temp;
|
int n, z;
|
int n, z;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((signed64)(signed32)State.regs[dstreg]
|
temp = ((signed64)(signed32)State.regs[dstreg]
|
* (signed64)(signed32)State.regs[srcreg]);
|
* (signed64)(signed32)State.regs[srcreg]);
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
|
// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
|
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
|
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
|
"mulu"
|
"mulu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
unsigned64 temp;
|
unsigned64 temp;
|
int n, z;
|
int n, z;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned64)State.regs[dstreg]
|
temp = ((unsigned64)State.regs[dstreg]
|
* (unsigned64)State.regs[srcreg]);
|
* (unsigned64)State.regs[srcreg]);
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
|
// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
|
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
|
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
|
"div"
|
"div"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
signed64 temp;
|
signed64 temp;
|
int n, z;
|
int n, z;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = State.regs[REG_MDR];
|
temp = State.regs[REG_MDR];
|
temp <<= 32;
|
temp <<= 32;
|
temp |= State.regs[dstreg];
|
temp |= State.regs[dstreg];
|
State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
|
State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
|
temp /= (signed32)State.regs[srcreg];
|
temp /= (signed32)State.regs[srcreg];
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
|
// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
|
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
|
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
|
"divu"
|
"divu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
unsigned64 temp;
|
unsigned64 temp;
|
int n, z;
|
int n, z;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = State.regs[REG_MDR];
|
temp = State.regs[REG_MDR];
|
temp <<= 32;
|
temp <<= 32;
|
temp |= State.regs[dstreg];
|
temp |= State.regs[dstreg];
|
State.regs[REG_MDR] = temp % State.regs[srcreg];
|
State.regs[REG_MDR] = temp % State.regs[srcreg];
|
temp /= State.regs[srcreg];
|
temp /= State.regs[srcreg];
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
|
|
// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
|
// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
|
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
|
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
|
// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
|
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
|
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
|
// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
|
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
|
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (State.regs[srcreg]);
|
State.regs[dstreg] = load_byte (State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
|
// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
|
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
|
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_byte (State.regs[dstreg], State.regs[srcreg]);
|
store_byte (State.regs[dstreg], State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
|
// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
|
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
|
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
|
// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
|
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
|
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
|
// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
|
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
|
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += 4;
|
State.regs[srcreg] += 4;
|
}
|
}
|
|
|
// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
|
// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
|
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
|
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
State.regs[dstreg] += 4;
|
State.regs[dstreg] += 4;
|
}
|
}
|
|
|
// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
|
// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
|
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
|
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[REG_SP]);
|
State.regs[dstreg] = load_word (State.regs[REG_SP]);
|
}
|
}
|
|
|
// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
|
// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
|
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
|
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_word (State.regs[REG_SP], State.regs[srcreg]);
|
store_word (State.regs[REG_SP], State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
|
// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
|
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
|
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (State.regs[REG_SP]);
|
State.regs[dstreg] = load_byte (State.regs[REG_SP]);
|
}
|
}
|
|
|
// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
|
// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
|
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
|
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_byte (State.regs[REG_SP], State.regs[srcreg]);
|
store_byte (State.regs[REG_SP], State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
|
// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
|
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
|
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[REG_SP]);
|
State.regs[dstreg] = load_half (State.regs[REG_SP]);
|
}
|
}
|
|
|
// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
|
// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
|
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
|
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_half (State.regs[REG_SP], State.regs[srcreg]);
|
store_half (State.regs[REG_SP], State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
|
// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
|
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
|
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
State.regs[srcreg] += 2;
|
State.regs[srcreg] += 2;
|
}
|
}
|
|
|
// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
|
// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
|
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
|
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
State.regs[dstreg] += 2;
|
State.regs[dstreg] += 2;
|
}
|
}
|
|
|
|
|
// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
|
// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
|
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
|
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
|
"mac"
|
"mac"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2;
|
int srcreg1, srcreg2;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
|
|
temp = ((signed64)(signed32)State.regs[srcreg2]
|
temp = ((signed64)(signed32)State.regs[srcreg2]
|
* (signed64)(signed32)State.regs[srcreg1]);
|
* (signed64)(signed32)State.regs[srcreg1]);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
|
// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
|
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
|
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
|
"macu"
|
"macu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2;
|
int srcreg1, srcreg2;
|
unsigned64 temp, sum;
|
unsigned64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned64)State.regs[srcreg2]
|
temp = ((unsigned64)State.regs[srcreg2]
|
* (unsigned64)State.regs[srcreg1]);
|
* (unsigned64)State.regs[srcreg1]);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
|
// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
|
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
|
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
|
"macb"
|
"macb"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2;
|
int srcreg1, srcreg2;
|
signed32 temp, sum;
|
signed32 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
|
|
temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
|
temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
|
* (signed32)(signed8)(State.regs[srcreg1] & 0xff));
|
* (signed32)(signed8)(State.regs[srcreg1] & 0xff));
|
sum = State.regs[REG_MCRL] + temp;
|
sum = State.regs[REG_MCRL] + temp;
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
|
// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
|
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
|
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
|
"macbu"
|
"macbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2;
|
int srcreg1, srcreg2;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
|
* (unsigned32)(State.regs[srcreg1] & 0xff));
|
* (unsigned32)(State.regs[srcreg1] & 0xff));
|
sum = State.regs[REG_MCRL] + temp;
|
sum = State.regs[REG_MCRL] + temp;
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
|
// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
|
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
|
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
|
"mach"
|
"mach"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2;
|
int srcreg1, srcreg2;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
|
temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
|
* (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
|
// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
|
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
|
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
|
"machu"
|
"machu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2;
|
int srcreg1, srcreg2;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
|
temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
|
* (unsigned64)(State.regs[srcreg1] & 0xffff));
|
* (unsigned64)(State.regs[srcreg1] & 0xffff));
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
|
// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
|
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
|
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
|
"dmach"
|
"dmach"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2;
|
int srcreg1, srcreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
|
|
temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
|
// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
|
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
|
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
|
"dmachu"
|
"dmachu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2;
|
int srcreg1, srcreg2;
|
unsigned32 temp, temp2, sum;
|
unsigned32 temp, temp2, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
|
* (unsigned32)(State.regs[srcreg1] & 0xffff));
|
* (unsigned32)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
|
* (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
|
// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
|
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
|
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
|
"dmulh"
|
"dmulh"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
signed32 temp;
|
signed32 temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg] & 0xffff));
|
State.regs[REG_MDRQ] = temp;
|
State.regs[REG_MDRQ] = temp;
|
temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
|
temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
|
* (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
|
State.regs[dstreg] = temp;
|
State.regs[dstreg] = temp;
|
}
|
}
|
|
|
// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
|
// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
|
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
|
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
|
"dmachu"
|
"dmachu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
unsigned32 temp;
|
unsigned32 temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
|
temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
|
* (unsigned32)(State.regs[srcreg] & 0xffff));
|
* (unsigned32)(State.regs[srcreg] & 0xffff));
|
State.regs[REG_MDRQ] = temp;
|
State.regs[REG_MDRQ] = temp;
|
temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
|
temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
|
* (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
|
* (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
|
State.regs[dstreg] = temp;
|
State.regs[dstreg] = temp;
|
}
|
}
|
|
|
// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
|
// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
|
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
|
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
|
"sat16"
|
"sat16"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int value, z, n;
|
int value, z, n;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
value = State.regs[srcreg];
|
value = State.regs[srcreg];
|
|
|
if (value >= 0x7fff)
|
if (value >= 0x7fff)
|
State.regs[dstreg] = 0x7fff;
|
State.regs[dstreg] = 0x7fff;
|
else if (value <= 0xffff8000)
|
else if (value <= 0xffff8000)
|
State.regs[dstreg] = 0xffff8000;
|
State.regs[dstreg] = 0xffff8000;
|
else
|
else
|
State.regs[dstreg] = value;
|
State.regs[dstreg] = value;
|
|
|
n = (State.regs[dstreg] & 0x8000) != 0;
|
n = (State.regs[dstreg] & 0x8000) != 0;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
|
// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
|
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
|
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
|
"mcste"
|
"mcste"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
PSW &= ~(PSW_V | PSW_C);
|
PSW &= ~(PSW_V | PSW_C);
|
PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
|
PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
|
|
|
/* 32bit saturation. */
|
/* 32bit saturation. */
|
if (State.regs[srcreg] == 0x20)
|
if (State.regs[srcreg] == 0x20)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x7fffffff)
|
if (tmp > 0x7fffffff)
|
State.regs[dstreg] = 0x7fffffff;
|
State.regs[dstreg] = 0x7fffffff;
|
else if (tmp < 0xffffffff80000000LL)
|
else if (tmp < 0xffffffff80000000LL)
|
State.regs[dstreg] = 0x80000000;
|
State.regs[dstreg] = 0x80000000;
|
else
|
else
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
/* 16bit saturation */
|
/* 16bit saturation */
|
else if (State.regs[srcreg] == 0x10)
|
else if (State.regs[srcreg] == 0x10)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x7fff)
|
if (tmp > 0x7fff)
|
State.regs[dstreg] = 0x7fff;
|
State.regs[dstreg] = 0x7fff;
|
else if (tmp < 0xffffffffffff8000LL)
|
else if (tmp < 0xffffffffffff8000LL)
|
State.regs[dstreg] = 0x8000;
|
State.regs[dstreg] = 0x8000;
|
else
|
else
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
/* 8 bit saturation */
|
/* 8 bit saturation */
|
else if (State.regs[srcreg] == 0x8)
|
else if (State.regs[srcreg] == 0x8)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x7f)
|
if (tmp > 0x7f)
|
State.regs[dstreg] = 0x7f;
|
State.regs[dstreg] = 0x7f;
|
else if (tmp < 0xffffffffffffff80LL)
|
else if (tmp < 0xffffffffffffff80LL)
|
State.regs[dstreg] = 0x80;
|
State.regs[dstreg] = 0x80;
|
else
|
else
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
/* 9 bit saturation */
|
/* 9 bit saturation */
|
else if (State.regs[srcreg] == 0x9)
|
else if (State.regs[srcreg] == 0x9)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x80)
|
if (tmp > 0x80)
|
State.regs[dstreg] = 0x80;
|
State.regs[dstreg] = 0x80;
|
else if (tmp < 0xffffffffffffff81LL)
|
else if (tmp < 0xffffffffffffff81LL)
|
State.regs[dstreg] = 0x81;
|
State.regs[dstreg] = 0x81;
|
else
|
else
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
/* 9 bit saturation */
|
/* 9 bit saturation */
|
else if (State.regs[srcreg] == 0x30)
|
else if (State.regs[srcreg] == 0x30)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x7fffffffffffLL)
|
if (tmp > 0x7fffffffffffLL)
|
tmp = 0x7fffffffffffLL;
|
tmp = 0x7fffffffffffLL;
|
else if (tmp < 0xffff800000000000LL)
|
else if (tmp < 0xffff800000000000LL)
|
tmp = 0xffff800000000000LL;
|
tmp = 0xffff800000000000LL;
|
|
|
tmp >>= 16;
|
tmp >>= 16;
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
}
|
}
|
|
|
// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
|
// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
|
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
|
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
|
"swap"
|
"swap"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
|
State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
|
| (((State.regs[srcreg] >> 8) & 0xff) << 16)
|
| (((State.regs[srcreg] >> 8) & 0xff) << 16)
|
| (((State.regs[srcreg] >> 16) & 0xff) << 8)
|
| (((State.regs[srcreg] >> 16) & 0xff) << 8)
|
| ((State.regs[srcreg] >> 24) & 0xff));
|
| ((State.regs[srcreg] >> 24) & 0xff));
|
}
|
}
|
|
|
// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
|
// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
|
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
|
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
|
"swaph"
|
"swaph"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
|
State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
|
| ((State.regs[srcreg] >> 8) & 0xff)
|
| ((State.regs[srcreg] >> 8) & 0xff)
|
| (((State.regs[srcreg] >> 16) & 0xff) << 24)
|
| (((State.regs[srcreg] >> 16) & 0xff) << 24)
|
| (((State.regs[srcreg] >> 24) & 0xff) << 16));
|
| (((State.regs[srcreg] >> 24) & 0xff) << 16));
|
}
|
}
|
|
|
// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
|
// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
|
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
|
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
|
"swhw"
|
"swhw"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
|
State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
|
| ((State.regs[srcreg] >> 16) & 0xffff));
|
| ((State.regs[srcreg] >> 16) & 0xffff));
|
}
|
}
|
|
|
// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
|
// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
|
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
|
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
|
"bsch"
|
"bsch"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int temp, c, i;
|
int temp, c, i;
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int start;
|
int start;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = State.regs[srcreg];
|
temp = State.regs[srcreg];
|
start = (State.regs[dstreg] & 0x1f) - 1;
|
start = (State.regs[dstreg] & 0x1f) - 1;
|
if (start == -1)
|
if (start == -1)
|
start = 31;
|
start = 31;
|
|
|
c = 0;
|
c = 0;
|
for (i = start; i >= 0; i--)
|
for (i = start; i >= 0; i--)
|
{
|
{
|
if (temp & (1 << i))
|
if (temp & (1 << i))
|
{
|
{
|
c = 1;
|
c = 1;
|
State.regs[dstreg] = i;
|
State.regs[dstreg] = i;
|
break;
|
break;
|
}
|
}
|
}
|
}
|
|
|
if (i < 0)
|
if (i < 0)
|
{
|
{
|
c = 0;
|
c = 0;
|
State.regs[dstreg] = 0;
|
State.regs[dstreg] = 0;
|
}
|
}
|
PSW &= ~(PSW_C);
|
PSW &= ~(PSW_C);
|
PSW |= (c ? PSW_C : 0);
|
PSW |= (c ? PSW_C : 0);
|
}
|
}
|
|
|
|
|
// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
|
// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
|
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
|
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = EXTEND8 (IMM8);
|
State.regs[dstreg] = EXTEND8 (IMM8);
|
}
|
}
|
|
|
// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
|
// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
|
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
|
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
|
"movu"
|
"movu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = IMM8 & 0xff;
|
State.regs[dstreg] = IMM8 & 0xff;
|
}
|
}
|
|
|
// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
|
// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
|
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
|
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
|
"add"
|
"add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
genericAdd (EXTEND8 (IMM8), dstreg);
|
genericAdd (EXTEND8 (IMM8), dstreg);
|
}
|
}
|
|
|
// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
|
// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
|
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
|
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
|
"addc"
|
"addc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg, imm;
|
int dstreg, imm;
|
int z, c, n, v;
|
int z, c, n, v;
|
unsigned32 reg2, sum;
|
unsigned32 reg2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
imm = EXTEND8 (IMM8);
|
imm = EXTEND8 (IMM8);
|
reg2 = State.regs[dstreg];
|
reg2 = State.regs[dstreg];
|
sum = imm + reg2 + ((PSW & PSW_C) != 0);
|
sum = imm + reg2 + ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
|
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
n = (sum & 0x80000000);
|
n = (sum & 0x80000000);
|
c = (sum < imm) || (sum < reg2);
|
c = (sum < imm) || (sum < reg2);
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
&& (reg2 & 0x80000000) != (sum & 0x80000000));
|
&& (reg2 & 0x80000000) != (sum & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
|
// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
|
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
|
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
|
"sub"
|
"sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
genericSub (EXTEND8 (IMM8), dstreg);
|
genericSub (EXTEND8 (IMM8), dstreg);
|
}
|
}
|
|
|
// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
|
// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
|
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
|
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
|
"subc"
|
"subc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int imm, dstreg;
|
int imm, dstreg;
|
int z, c, n, v;
|
int z, c, n, v;
|
unsigned32 reg2, difference;
|
unsigned32 reg2, difference;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
imm = EXTEND8 (IMM8);
|
imm = EXTEND8 (IMM8);
|
reg2 = State.regs[dstreg];
|
reg2 = State.regs[dstreg];
|
difference = reg2 - imm - ((PSW & PSW_C) != 0);
|
difference = reg2 - imm - ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = difference;
|
State.regs[dstreg] = difference;
|
|
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
n = (difference & 0x80000000);
|
n = (difference & 0x80000000);
|
c = (imm > reg2);
|
c = (imm > reg2);
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
&& (reg2 & 0x80000000) != (difference & 0x80000000));
|
&& (reg2 & 0x80000000) != (difference & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
|
// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
|
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
|
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
|
"cmp"
|
"cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
|
genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
|
// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
|
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
|
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_xreg (SD_, XRN0);
|
dstreg = translate_xreg (SD_, XRN0);
|
|
|
State.regs[dstreg] = IMM8;
|
State.regs[dstreg] = IMM8;
|
}
|
}
|
|
|
// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
|
// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
|
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
|
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
|
"and"
|
"and"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] &= (IMM8 & 0xff);
|
State.regs[dstreg] &= (IMM8 & 0xff);
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
|
// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
|
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
|
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
|
"or"
|
"or"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] |= (IMM8 & 0xff);
|
State.regs[dstreg] |= (IMM8 & 0xff);
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
|
// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
|
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
|
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
|
"xor"
|
"xor"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] ^= (IMM8 & 0xff);
|
State.regs[dstreg] ^= (IMM8 & 0xff);
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
|
// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
|
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
|
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
|
"asr"
|
"asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
signed32 temp;
|
signed32 temp;
|
int c, z, n;
|
int c, z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = State.regs[dstreg];
|
temp = State.regs[dstreg];
|
c = temp & 1;
|
c = temp & 1;
|
temp >>= (IMM8 & 0xff);
|
temp >>= (IMM8 & 0xff);
|
State.regs[dstreg] = temp;
|
State.regs[dstreg] = temp;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
|
// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
|
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
|
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
|
"lsr"
|
"lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n, c;
|
int z, n, c;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
c = State.regs[dstreg] & 1;
|
c = State.regs[dstreg] & 1;
|
State.regs[dstreg] >>= (IMM8 & 0xff);
|
State.regs[dstreg] >>= (IMM8 & 0xff);
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
|
// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
|
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
|
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
|
"asl"
|
"asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] <<= (IMM8 & 0xff);
|
State.regs[dstreg] <<= (IMM8 & 0xff);
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
|
// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
|
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
|
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
|
"mul"
|
"mul"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
unsigned64 temp;
|
unsigned64 temp;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((signed64)(signed32)State.regs[dstreg]
|
temp = ((signed64)(signed32)State.regs[dstreg]
|
* (signed64)(signed32)EXTEND8 (IMM8));
|
* (signed64)(signed32)EXTEND8 (IMM8));
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
|
// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
|
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
|
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
|
"mulu"
|
"mulu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
unsigned64 temp;
|
unsigned64 temp;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned64)State.regs[dstreg]
|
temp = ((unsigned64)State.regs[dstreg]
|
* (unsigned64)(IMM8 & 0xff));
|
* (unsigned64)(IMM8 & 0xff));
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
|
// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
|
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
|
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
|
"btst"
|
"btst"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
genericBtst(IMM8, State.regs[srcreg]);
|
genericBtst(IMM8, State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
|
// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
|
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
|
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
|
State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
|
}
|
}
|
|
|
// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
|
// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
|
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
|
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
|
store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
|
// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
|
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
|
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
|
State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
|
}
|
}
|
|
|
// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
|
// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
|
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
|
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
|
store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
|
// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
|
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
|
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
|
State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
|
}
|
}
|
|
|
// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
|
// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
|
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
|
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
|
store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
|
// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
|
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
|
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND8 (IMM8);
|
State.regs[srcreg] += EXTEND8 (IMM8);
|
}
|
}
|
|
|
// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
|
// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
|
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
|
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
State.regs[dstreg] += EXTEND8 (IMM8);
|
State.regs[dstreg] += EXTEND8 (IMM8);
|
}
|
}
|
|
|
|
|
// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
|
// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
|
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
|
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
|
State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
|
}
|
}
|
|
|
// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp)
|
// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp)
|
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
|
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
|
store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
|
// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
|
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
|
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
|
State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
|
}
|
}
|
|
|
// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp)
|
// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp)
|
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
|
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
|
store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
|
// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
|
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
|
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
|
State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
|
}
|
}
|
|
|
// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
|
// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
|
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
|
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
|
store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
|
// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
|
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
|
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND8 (IMM8);
|
State.regs[srcreg] += EXTEND8 (IMM8);
|
}
|
}
|
|
|
// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
|
// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
|
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
|
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
State.regs[dstreg] += EXTEND8 (IMM8);
|
State.regs[dstreg] += EXTEND8 (IMM8);
|
}
|
}
|
|
|
|
|
// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
|
// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
|
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
|
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
|
"mac"
|
"mac"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed64)(signed32)EXTEND8 (IMM8)
|
temp = ((signed64)(signed32)EXTEND8 (IMM8)
|
* (signed64)(signed32)State.regs[srcreg]);
|
* (signed64)(signed32)State.regs[srcreg]);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
|
// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
|
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
|
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
|
"macu"
|
"macu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((unsigned64) (IMM8)
|
temp = ((unsigned64) (IMM8)
|
* (unsigned64)State.regs[srcreg]);
|
* (unsigned64)State.regs[srcreg]);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
|
// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
|
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
|
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
|
"macb"
|
"macb"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed64)(signed8)EXTEND8 (IMM8)
|
temp = ((signed64)(signed8)EXTEND8 (IMM8)
|
* (signed64)(signed8)State.regs[srcreg] & 0xff);
|
* (signed64)(signed8)State.regs[srcreg] & 0xff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
|
// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
|
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
|
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
|
"macbu"
|
"macbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((unsigned64) (IMM8)
|
temp = ((unsigned64) (IMM8)
|
* (unsigned64)State.regs[srcreg] & 0xff);
|
* (unsigned64)State.regs[srcreg] & 0xff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
|
// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
|
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
|
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
|
"mach"
|
"mach"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed64)(signed16)EXTEND8 (IMM8)
|
temp = ((signed64)(signed16)EXTEND8 (IMM8)
|
* (signed64)(signed16)State.regs[srcreg] & 0xffff);
|
* (signed64)(signed16)State.regs[srcreg] & 0xffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
|
// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
|
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
|
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
|
"machu"
|
"machu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((unsigned64) (IMM8)
|
temp = ((unsigned64) (IMM8)
|
* (unsigned64)State.regs[srcreg] & 0xffff);
|
* (unsigned64)State.regs[srcreg] & 0xffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
|
// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
|
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
|
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
|
"mcste"
|
"mcste"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
PSW &= ~(PSW_V | PSW_C);
|
PSW &= ~(PSW_V | PSW_C);
|
PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
|
PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
|
|
|
/* 32bit saturation. */
|
/* 32bit saturation. */
|
if (IMM8 == 0x20)
|
if (IMM8 == 0x20)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x7fffffff)
|
if (tmp > 0x7fffffff)
|
State.regs[dstreg] = 0x7fffffff;
|
State.regs[dstreg] = 0x7fffffff;
|
else if (tmp < 0xffffffff80000000LL)
|
else if (tmp < 0xffffffff80000000LL)
|
State.regs[dstreg] = 0x80000000;
|
State.regs[dstreg] = 0x80000000;
|
else
|
else
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
/* 16bit saturation */
|
/* 16bit saturation */
|
else if (IMM8 == 0x10)
|
else if (IMM8 == 0x10)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x7fff)
|
if (tmp > 0x7fff)
|
State.regs[dstreg] = 0x7fff;
|
State.regs[dstreg] = 0x7fff;
|
else if (tmp < 0xffffffffffff8000LL)
|
else if (tmp < 0xffffffffffff8000LL)
|
State.regs[dstreg] = 0x8000;
|
State.regs[dstreg] = 0x8000;
|
else
|
else
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
/* 8 bit saturation */
|
/* 8 bit saturation */
|
else if (IMM8 == 0x8)
|
else if (IMM8 == 0x8)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x7f)
|
if (tmp > 0x7f)
|
State.regs[dstreg] = 0x7f;
|
State.regs[dstreg] = 0x7f;
|
else if (tmp < 0xffffffffffffff80LL)
|
else if (tmp < 0xffffffffffffff80LL)
|
State.regs[dstreg] = 0x80;
|
State.regs[dstreg] = 0x80;
|
else
|
else
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
/* 9 bit saturation */
|
/* 9 bit saturation */
|
else if (IMM8 == 0x9)
|
else if (IMM8 == 0x9)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x80)
|
if (tmp > 0x80)
|
State.regs[dstreg] = 0x80;
|
State.regs[dstreg] = 0x80;
|
else if (tmp < 0xffffffffffffff81LL)
|
else if (tmp < 0xffffffffffffff81LL)
|
State.regs[dstreg] = 0x81;
|
State.regs[dstreg] = 0x81;
|
else
|
else
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
/* 9 bit saturation */
|
/* 9 bit saturation */
|
else if (IMM8 == 0x30)
|
else if (IMM8 == 0x30)
|
{
|
{
|
signed64 tmp;
|
signed64 tmp;
|
|
|
tmp = State.regs[REG_MCRH];
|
tmp = State.regs[REG_MCRH];
|
tmp <<= 32;
|
tmp <<= 32;
|
tmp += State.regs[REG_MCRL];
|
tmp += State.regs[REG_MCRL];
|
|
|
if (tmp > 0x7fffffffffffLL)
|
if (tmp > 0x7fffffffffffLL)
|
tmp = 0x7fffffffffffLL;
|
tmp = 0x7fffffffffffLL;
|
else if (tmp < 0xffff800000000000LL)
|
else if (tmp < 0xffff800000000000LL)
|
tmp = 0xffff800000000000LL;
|
tmp = 0xffff800000000000LL;
|
|
|
tmp >>= 16;
|
tmp >>= 16;
|
State.regs[dstreg] = tmp;
|
State.regs[dstreg] = tmp;
|
}
|
}
|
}
|
}
|
|
|
// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
|
// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
|
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
|
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
|
"add"
|
"add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, c, n, v;
|
int z, c, n, v;
|
unsigned32 sum, source1, source2;
|
unsigned32 sum, source1, source2;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
source1 = State.regs[srcreg1];
|
source1 = State.regs[srcreg1];
|
source2 = State.regs[srcreg2];
|
source2 = State.regs[srcreg2];
|
sum = source1 + source2;
|
sum = source1 + source2;
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
|
|
z = (sum == 0);
|
z = (sum == 0);
|
n = (sum & 0x80000000);
|
n = (sum & 0x80000000);
|
c = (sum < source1) || (sum < source2);
|
c = (sum < source1) || (sum < source2);
|
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
|
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
|
&& (source1 & 0x80000000) != (sum & 0x80000000));
|
&& (source1 & 0x80000000) != (sum & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
|
// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
|
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
|
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
|
"addc"
|
"addc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, c, n, v;
|
int z, c, n, v;
|
unsigned32 sum, source1, source2;
|
unsigned32 sum, source1, source2;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
source1 = State.regs[srcreg1];
|
source1 = State.regs[srcreg1];
|
source2 = State.regs[srcreg2];
|
source2 = State.regs[srcreg2];
|
sum = source1 + source2 + ((PSW & PSW_C) != 0);
|
sum = source1 + source2 + ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
|
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
n = (sum & 0x80000000);
|
n = (sum & 0x80000000);
|
c = (sum < source1) || (sum < source2);
|
c = (sum < source1) || (sum < source2);
|
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
|
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
|
&& (source1 & 0x80000000) != (sum & 0x80000000));
|
&& (source1 & 0x80000000) != (sum & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
|
// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
|
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
|
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
|
"sub"
|
"sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, c, n, v;
|
int z, c, n, v;
|
unsigned32 difference, source1, source2;
|
unsigned32 difference, source1, source2;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
source1 = State.regs[srcreg1];
|
source1 = State.regs[srcreg1];
|
source2 = State.regs[srcreg2];
|
source2 = State.regs[srcreg2];
|
difference = source2 - source1;
|
difference = source2 - source1;
|
State.regs[dstreg] = difference;
|
State.regs[dstreg] = difference;
|
|
|
z = (difference == 0);
|
z = (difference == 0);
|
n = (difference & 0x80000000);
|
n = (difference & 0x80000000);
|
c = (source1 > source1);
|
c = (source1 > source1);
|
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
|
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
|
&& (source1 & 0x80000000) != (difference & 0x80000000));
|
&& (source1 & 0x80000000) != (difference & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
|
// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
|
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
|
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
|
"subc"
|
"subc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, c, n, v;
|
int z, c, n, v;
|
unsigned32 difference, source1, source2;
|
unsigned32 difference, source1, source2;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
source1 = State.regs[srcreg1];
|
source1 = State.regs[srcreg1];
|
source2 = State.regs[srcreg2];
|
source2 = State.regs[srcreg2];
|
difference = source2 - source1 - ((PSW & PSW_C) != 0);
|
difference = source2 - source1 - ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = difference;
|
State.regs[dstreg] = difference;
|
|
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
n = (difference & 0x80000000);
|
n = (difference & 0x80000000);
|
c = (source1 > source2);
|
c = (source1 > source2);
|
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
|
v = ((source1 & 0x80000000) == (source2 & 0x80000000)
|
&& (source1 & 0x80000000) != (difference & 0x80000000));
|
&& (source1 & 0x80000000) != (difference & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
|
// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
|
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
|
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
|
"and"
|
"and"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, n;
|
int z, n;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
|
State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
|
|
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000);
|
n = (State.regs[dstreg] & 0x80000000);
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
|
// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
|
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
|
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
|
"or"
|
"or"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, n;
|
int z, n;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
|
State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
|
|
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000);
|
n = (State.regs[dstreg] & 0x80000000);
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
|
// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
|
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
|
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
|
"xor"
|
"xor"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, n;
|
int z, n;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
|
State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
|
|
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000);
|
n = (State.regs[dstreg] & 0x80000000);
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
|
// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
|
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
|
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
|
"asr"
|
"asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, c, n;
|
int z, c, n;
|
signed32 temp;
|
signed32 temp;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
temp = State.regs[srcreg2];
|
temp = State.regs[srcreg2];
|
c = temp & 1;
|
c = temp & 1;
|
temp >>= State.regs[srcreg1];
|
temp >>= State.regs[srcreg1];
|
State.regs[dstreg] = temp;
|
State.regs[dstreg] = temp;
|
|
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000);
|
n = (State.regs[dstreg] & 0x80000000);
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
|
// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
|
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
|
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
|
"lsr"
|
"lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, c, n;
|
int z, c, n;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
c = State.regs[srcreg2] & 1;
|
c = State.regs[srcreg2] & 1;
|
State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
|
State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
|
|
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000);
|
n = (State.regs[dstreg] & 0x80000000);
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
|
// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
|
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
|
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
|
"asl"
|
"asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int z, n;
|
int z, n;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
|
State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
|
|
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000);
|
n = (State.regs[dstreg] & 0x80000000);
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
|
// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
|
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
|
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
|
"mul"
|
"mul"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed64 temp;
|
signed64 temp;
|
int n, z;
|
int n, z;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD2);
|
dstreg2 = translate_rreg (SD_, RD2);
|
|
|
temp = ((signed64)(signed32)State.regs[srcreg1]
|
temp = ((signed64)(signed32)State.regs[srcreg1]
|
* (signed64)(signed32)State.regs[srcreg2]);
|
* (signed64)(signed32)State.regs[srcreg2]);
|
State.regs[dstreg2] = temp & 0xffffffff;
|
State.regs[dstreg2] = temp & 0xffffffff;
|
State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
|
|
|
z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
|
z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
|
n = (State.regs[dstreg1] & 0x80000000);
|
n = (State.regs[dstreg1] & 0x80000000);
|
|
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
|
// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
|
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
|
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
|
"mulu"
|
"mulu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed64 temp;
|
signed64 temp;
|
int n, z;
|
int n, z;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD2);
|
dstreg2 = translate_rreg (SD_, RD2);
|
|
|
temp = ((unsigned64)State.regs[srcreg1]
|
temp = ((unsigned64)State.regs[srcreg1]
|
* (unsigned64)State.regs[srcreg2]);
|
* (unsigned64)State.regs[srcreg2]);
|
State.regs[dstreg2] = temp & 0xffffffff;
|
State.regs[dstreg2] = temp & 0xffffffff;
|
State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
|
|
|
z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
|
z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
|
n = (State.regs[dstreg1] & 0x80000000);
|
n = (State.regs[dstreg1] & 0x80000000);
|
|
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
|
// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
|
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
|
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (IMM8);
|
State.regs[dstreg] = load_word (IMM8);
|
}
|
}
|
|
|
// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
|
// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
|
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
|
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_word (IMM8, State.regs[srcreg]);
|
store_word (IMM8, State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
|
// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
|
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
|
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (IMM8);
|
State.regs[dstreg] = load_byte (IMM8);
|
}
|
}
|
|
|
// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
|
// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
|
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
|
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_byte (IMM8, State.regs[srcreg]);
|
store_byte (IMM8, State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
|
// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
|
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
|
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (IMM8);
|
State.regs[dstreg] = load_half (IMM8);
|
}
|
}
|
|
|
// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
|
// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
|
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
|
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_half (IMM8, State.regs[srcreg]);
|
store_half (IMM8, State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
|
// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
|
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
|
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM0);
|
srcreg1 = translate_rreg (SD_, RM0);
|
srcreg2 = translate_rreg (SD_, RI0);
|
srcreg2 = translate_rreg (SD_, RI0);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
|
State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
|
}
|
}
|
|
|
// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
|
// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
|
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
|
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg1, dstreg2;
|
int srcreg, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg1 = translate_rreg (SD_, RI0);
|
dstreg1 = translate_rreg (SD_, RI0);
|
dstreg2 = translate_rreg (SD_, RN0);
|
dstreg2 = translate_rreg (SD_, RN0);
|
store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
|
store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
|
// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
|
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
|
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM0);
|
srcreg1 = translate_rreg (SD_, RM0);
|
srcreg2 = translate_rreg (SD_, RI0);
|
srcreg2 = translate_rreg (SD_, RI0);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
|
State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
|
}
|
}
|
|
|
// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
|
// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
|
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
|
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg1, dstreg2;
|
int srcreg, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg1 = translate_rreg (SD_, RI0);
|
dstreg1 = translate_rreg (SD_, RI0);
|
dstreg2 = translate_rreg (SD_, RN0);
|
dstreg2 = translate_rreg (SD_, RN0);
|
store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
|
store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
|
// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
|
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
|
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM0);
|
srcreg1 = translate_rreg (SD_, RM0);
|
srcreg2 = translate_rreg (SD_, RI0);
|
srcreg2 = translate_rreg (SD_, RI0);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
|
State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
|
}
|
}
|
|
|
// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
|
// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
|
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
|
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg1, dstreg2;
|
int srcreg, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg1 = translate_rreg (SD_, RI0);
|
dstreg1 = translate_rreg (SD_, RI0);
|
dstreg2 = translate_rreg (SD_, RN0);
|
dstreg2 = translate_rreg (SD_, RN0);
|
store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
|
store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
|
// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
|
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
|
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
|
"mac"
|
"mac"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed64 temp;
|
signed64 temp;
|
unsigned32 sum;
|
unsigned32 sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD2);
|
dstreg2 = translate_rreg (SD_, RD2);
|
|
|
temp = ((signed64)(signed32)State.regs[srcreg1]
|
temp = ((signed64)(signed32)State.regs[srcreg1]
|
* (signed64)(signed32)State.regs[srcreg2]);
|
* (signed64)(signed32)State.regs[srcreg2]);
|
|
|
sum = State.regs[dstreg2] + (temp & 0xffffffff);
|
sum = State.regs[dstreg2] + (temp & 0xffffffff);
|
c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
|
State.regs[dstreg2] = sum;
|
State.regs[dstreg2] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[dstreg1] + temp + c;
|
sum = State.regs[dstreg1] + temp + c;
|
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
if (v)
|
if (v)
|
{
|
{
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
PSW &= ~(PSW_V);
|
PSW &= ~(PSW_V);
|
PSW |= (( v ? PSW_V : 0));
|
PSW |= (( v ? PSW_V : 0));
|
}
|
}
|
}
|
}
|
|
|
// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
|
// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
|
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
|
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
|
"macu"
|
"macu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed64 temp;
|
signed64 temp;
|
unsigned32 sum;
|
unsigned32 sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD2);
|
dstreg2 = translate_rreg (SD_, RD2);
|
|
|
temp = ((unsigned64)State.regs[srcreg1]
|
temp = ((unsigned64)State.regs[srcreg1]
|
* (unsigned64)State.regs[srcreg2]);
|
* (unsigned64)State.regs[srcreg2]);
|
|
|
sum = State.regs[dstreg2] + (temp & 0xffffffff);
|
sum = State.regs[dstreg2] + (temp & 0xffffffff);
|
c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
|
State.regs[dstreg2] = sum;
|
State.regs[dstreg2] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[dstreg1] + temp + c;
|
sum = State.regs[dstreg1] + temp + c;
|
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
if (v)
|
if (v)
|
{
|
{
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
PSW &= ~(PSW_V);
|
PSW &= ~(PSW_V);
|
PSW |= (( v ? PSW_V : 0));
|
PSW |= (( v ? PSW_V : 0));
|
}
|
}
|
}
|
}
|
|
|
// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
|
// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
|
8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
|
8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
|
"macb"
|
"macb"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
signed32 temp, sum;
|
signed32 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
temp = ((signed32)(State.regs[srcreg2] & 0xff)
|
temp = ((signed32)(State.regs[srcreg2] & 0xff)
|
* (signed32)(State.regs[srcreg1] & 0xff));
|
* (signed32)(State.regs[srcreg1] & 0xff));
|
sum = State.regs[dstreg] + temp;
|
sum = State.regs[dstreg] + temp;
|
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
if (v)
|
if (v)
|
{
|
{
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
PSW &= ~(PSW_V);
|
PSW &= ~(PSW_V);
|
PSW |= ((v ? PSW_V : 0));
|
PSW |= ((v ? PSW_V : 0));
|
}
|
}
|
}
|
}
|
|
|
// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
|
// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
|
8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
|
8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
|
"macbu"
|
"macbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
signed32 temp, sum;
|
signed32 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
|
* (unsigned32)(State.regs[srcreg1] & 0xff));
|
* (unsigned32)(State.regs[srcreg1] & 0xff));
|
sum = State.regs[dstreg] + temp;
|
sum = State.regs[dstreg] + temp;
|
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
if (v)
|
if (v)
|
{
|
{
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
PSW &= ~(PSW_V);
|
PSW &= ~(PSW_V);
|
PSW |= ((v ? PSW_V : 0));
|
PSW |= ((v ? PSW_V : 0));
|
}
|
}
|
}
|
}
|
|
|
// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
|
// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
|
8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
|
8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
|
"mach"
|
"mach"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD0);
|
|
|
temp = ((signed32)(State.regs[srcreg2] & 0xffff)
|
temp = ((signed32)(State.regs[srcreg2] & 0xffff)
|
* (signed32)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(State.regs[srcreg1] & 0xffff));
|
State.regs[dstreg2] += (temp & 0xffffffff);
|
State.regs[dstreg2] += (temp & 0xffffffff);
|
sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
|
sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
|
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
if (v)
|
if (v)
|
{
|
{
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
PSW &= ~(PSW_V);
|
PSW &= ~(PSW_V);
|
PSW |= ((v ? PSW_V : 0));
|
PSW |= ((v ? PSW_V : 0));
|
}
|
}
|
}
|
}
|
|
|
// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
|
// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
|
8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
|
8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
|
"machu"
|
"machu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD0);
|
|
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
|
* (unsigned32)(State.regs[srcreg1] & 0xffff));
|
* (unsigned32)(State.regs[srcreg1] & 0xffff));
|
State.regs[dstreg2] += (temp & 0xffffffff);
|
State.regs[dstreg2] += (temp & 0xffffffff);
|
sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
|
sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
|
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
if (v)
|
if (v)
|
{
|
{
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
PSW &= ~(PSW_V);
|
PSW &= ~(PSW_V);
|
PSW |= ((v ? PSW_V : 0));
|
PSW |= ((v ? PSW_V : 0));
|
}
|
}
|
}
|
}
|
|
|
// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
|
// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
|
8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
|
8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
|
"dmach"
|
"dmach"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
temp = ((signed32)(State.regs[srcreg2] & 0xffff)
|
temp = ((signed32)(State.regs[srcreg2] & 0xffff)
|
* (signed32)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
|
* (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[dstreg];
|
sum = temp + temp2 + State.regs[dstreg];
|
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
if (v)
|
if (v)
|
{
|
{
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
PSW &= ~(PSW_V);
|
PSW &= ~(PSW_V);
|
PSW |= ((v ? PSW_V : 0));
|
PSW |= ((v ? PSW_V : 0));
|
}
|
}
|
}
|
}
|
|
|
// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
|
// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
|
8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
|
8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
|
"dmachu"
|
"dmachu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
|
temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
|
* (unsigned32)(State.regs[srcreg1] & 0xffff));
|
* (unsigned32)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
|
* (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[dstreg];
|
sum = temp + temp2 + State.regs[dstreg];
|
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
if (v)
|
if (v)
|
{
|
{
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
PSW &= ~(PSW_V);
|
PSW &= ~(PSW_V);
|
PSW |= ((v ? PSW_V : 0));
|
PSW |= ((v ? PSW_V : 0));
|
}
|
}
|
}
|
}
|
|
|
// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
|
// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
|
8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
|
8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
|
"dmulh"
|
"dmulh"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed64 temp;
|
signed64 temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD2);
|
dstreg2 = translate_rreg (SD_, RD2);
|
|
|
temp = ((signed32)(State.regs[srcreg1] & 0xffff)
|
temp = ((signed32)(State.regs[srcreg1] & 0xffff)
|
* (signed32)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(State.regs[srcreg1] & 0xffff));
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)((State.regs[srcreg1] >>16) & 0xffff));
|
* (signed32)((State.regs[srcreg1] >>16) & 0xffff));
|
State.regs[dstreg1] = temp;
|
State.regs[dstreg1] = temp;
|
}
|
}
|
|
|
// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
|
// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
|
8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
|
8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
|
"dmulhu"
|
"dmulhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed64 temp;
|
signed64 temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg1 = translate_rreg (SD_, RD0);
|
dstreg2 = translate_rreg (SD_, RD2);
|
dstreg2 = translate_rreg (SD_, RD2);
|
|
|
temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
|
temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
|
* (unsigned32)(State.regs[srcreg1] & 0xffff));
|
* (unsigned32)(State.regs[srcreg1] & 0xffff));
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
|
* (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
|
State.regs[dstreg1] = temp;
|
State.regs[dstreg1] = temp;
|
}
|
}
|
|
|
// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
|
// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
|
8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
|
8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
|
"sat24"
|
"sat24"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
int value, n, z;
|
int value, n, z;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
value = State.regs[srcreg];
|
value = State.regs[srcreg];
|
|
|
if (value >= 0x7fffff)
|
if (value >= 0x7fffff)
|
State.regs[dstreg] = 0x7fffff;
|
State.regs[dstreg] = 0x7fffff;
|
else if (value <= 0xff800000)
|
else if (value <= 0xff800000)
|
State.regs[dstreg] = 0xff800000;
|
State.regs[dstreg] = 0xff800000;
|
else
|
else
|
State.regs[dstreg] = value;
|
State.regs[dstreg] = value;
|
|
|
n = (State.regs[dstreg] & 0x800000) != 0;
|
n = (State.regs[dstreg] & 0x800000) != 0;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
|
// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
|
8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
|
8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
|
"bsch"
|
"bsch"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int temp, c, i;
|
int temp, c, i;
|
int srcreg1, srcreg2, dstreg;
|
int srcreg1, srcreg2, dstreg;
|
int start;
|
int start;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg1 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RN0);
|
srcreg2 = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RD0);
|
dstreg = translate_rreg (SD_, RD0);
|
|
|
temp = State.regs[srcreg1];
|
temp = State.regs[srcreg1];
|
start = (State.regs[srcreg2] & 0x1f) - 1;
|
start = (State.regs[srcreg2] & 0x1f) - 1;
|
if (start == -1)
|
if (start == -1)
|
start = 31;
|
start = 31;
|
|
|
c = 0;
|
c = 0;
|
for (i = start; i >= 0; i--)
|
for (i = start; i >= 0; i--)
|
{
|
{
|
if (temp & (1 << i))
|
if (temp & (1 << i))
|
{
|
{
|
c = 1;
|
c = 1;
|
State.regs[dstreg] = i;
|
State.regs[dstreg] = i;
|
break;
|
break;
|
}
|
}
|
}
|
}
|
|
|
if (i < 0)
|
if (i < 0)
|
{
|
{
|
c = 0;
|
c = 0;
|
State.regs[dstreg] = 0;
|
State.regs[dstreg] = 0;
|
}
|
}
|
PSW &= ~(PSW_C);
|
PSW &= ~(PSW_C);
|
PSW |= (c ? PSW_C : 0);
|
PSW |= (c ? PSW_C : 0);
|
}
|
}
|
|
|
// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
|
// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
|
8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
|
8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
|
// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
|
8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
|
8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
|
"movu"
|
"movu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
|
State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
|
}
|
}
|
|
|
// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
|
// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
|
8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
|
8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
|
"add"
|
"add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
|
genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
|
}
|
}
|
|
|
// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
|
// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
|
8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
|
8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
|
"addc"
|
"addc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg, z, n, c, v;
|
int dstreg, z, n, c, v;
|
unsigned32 sum, imm, reg2;
|
unsigned32 sum, imm, reg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
reg2 = State.regs[dstreg];
|
reg2 = State.regs[dstreg];
|
sum = imm + reg2 + ((PSW & PSW_C) != 0);
|
sum = imm + reg2 + ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
|
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
n = (sum & 0x80000000);
|
n = (sum & 0x80000000);
|
c = (sum < imm) || (sum < reg2);
|
c = (sum < imm) || (sum < reg2);
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
&& (reg2 & 0x80000000) != (sum & 0x80000000));
|
&& (reg2 & 0x80000000) != (sum & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
|
// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
|
8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
|
8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
|
"sub"
|
"sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
|
genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
|
}
|
}
|
|
|
// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
|
// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
|
8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
|
8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
|
"subc"
|
"subc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg, z, n, c, v;
|
int dstreg, z, n, c, v;
|
unsigned32 difference, imm, reg2;
|
unsigned32 difference, imm, reg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
reg2 = State.regs[dstreg];
|
reg2 = State.regs[dstreg];
|
difference = reg2 - imm - ((PSW & PSW_C) != 0);
|
difference = reg2 - imm - ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = difference;
|
State.regs[dstreg] = difference;
|
|
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
n = (difference & 0x80000000);
|
n = (difference & 0x80000000);
|
c = (imm > reg2);
|
c = (imm > reg2);
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
&& (reg2 & 0x80000000) != (difference & 0x80000000));
|
&& (reg2 & 0x80000000) != (difference & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
|
// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
|
8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
|
8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
|
"cmp"
|
"cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
|
genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
|
// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
|
8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
|
8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_xreg (SD_, XRN0);
|
dstreg = translate_xreg (SD_, XRN0);
|
|
|
State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
|
State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
|
}
|
}
|
|
|
// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
|
// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
|
8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
|
8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
|
"and"
|
"and"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z,n;
|
int z,n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
|
State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
|
// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
|
8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
|
8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
|
"or"
|
"or"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z,n;
|
int z,n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
|
State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
|
// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
|
8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
|
8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
|
"xor"
|
"xor"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z,n;
|
int z,n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
|
State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
|
// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
|
8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
|
8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
|
"asr"
|
"asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
signed32 temp;
|
signed32 temp;
|
int c, z, n;
|
int c, z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = State.regs[dstreg];
|
temp = State.regs[dstreg];
|
c = temp & 1;
|
c = temp & 1;
|
temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
|
temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[dstreg] = temp;
|
State.regs[dstreg] = temp;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
|
|
// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
|
// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
|
8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
|
8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
|
"lsr"
|
"lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n, c;
|
int z, n, c;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
c = State.regs[dstreg] & 1;
|
c = State.regs[dstreg] & 1;
|
State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
|
// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
|
8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
|
8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
|
"asl"
|
"asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
|
// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
|
8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
|
8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
|
"mul"
|
"mul"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
unsigned64 temp;
|
unsigned64 temp;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((signed64)(signed32)State.regs[dstreg]
|
temp = ((signed64)(signed32)State.regs[dstreg]
|
* (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
|
* (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
|
// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
|
8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
|
8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
|
"mulu"
|
"mulu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
unsigned64 temp;
|
unsigned64 temp;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned64)State.regs[dstreg]
|
temp = ((unsigned64)State.regs[dstreg]
|
* (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
|
* (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
|
// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
|
8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
|
8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
|
"btst"
|
"btst"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
|
genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
|
// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
|
8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
|
8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[srcreg]
|
State.regs[dstreg] = load_word (State.regs[srcreg]
|
+ EXTEND24 (FETCH24 (IMM24A,
|
+ EXTEND24 (FETCH24 (IMM24A,
|
IMM24B, IMM24C)));
|
IMM24B, IMM24C)));
|
}
|
}
|
|
|
// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
|
// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
|
8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
|
8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
|
store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
|
// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
|
8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
|
8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (State.regs[srcreg]
|
State.regs[dstreg] = load_byte (State.regs[srcreg]
|
+ EXTEND24 (FETCH24 (IMM24A,
|
+ EXTEND24 (FETCH24 (IMM24A,
|
IMM24B, IMM24C)));
|
IMM24B, IMM24C)));
|
}
|
}
|
|
|
// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
|
// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
|
8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
|
8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
|
store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
|
// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
|
8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
|
8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[srcreg]
|
State.regs[dstreg] = load_half (State.regs[srcreg]
|
+ EXTEND24 (FETCH24 (IMM24A,
|
+ EXTEND24 (FETCH24 (IMM24A,
|
IMM24B, IMM24C)));
|
IMM24B, IMM24C)));
|
}
|
}
|
|
|
// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
|
// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
|
8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
|
8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
|
store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
|
// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
|
8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
|
8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
|
// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
|
8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
|
8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
|
|
// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
|
// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
|
8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
|
8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[REG_SP]
|
State.regs[dstreg] = load_word (State.regs[REG_SP]
|
+ FETCH24 (IMM24A, IMM24B, IMM24C));
|
+ FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
|
// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
|
8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
|
8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
|
store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn
|
// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn
|
8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
|
8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (State.regs[REG_SP]
|
State.regs[dstreg] = load_byte (State.regs[REG_SP]
|
+ FETCH24 (IMM24A, IMM24B, IMM24C));
|
+ FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
|
// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
|
8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
|
8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
|
store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
|
// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
|
8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
|
8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[REG_SP]
|
State.regs[dstreg] = load_half (State.regs[REG_SP]
|
+ FETCH24 (IMM24A, IMM24B, IMM24C));
|
+ FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
|
// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
|
8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
|
8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
|
store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
|
// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
|
8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
|
8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
|
// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
|
8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
|
8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
|
// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
|
8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
|
8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
|
"mac"
|
"mac"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
|
temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
|
* (signed64)State.regs[srcreg]);
|
* (signed64)State.regs[srcreg]);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
|
// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
|
8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
|
8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
|
"macu"
|
"macu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
|
temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
|
* (unsigned64)State.regs[srcreg]);
|
* (unsigned64)State.regs[srcreg]);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
|
// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
|
8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
|
8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
|
"macb"
|
"macb"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
|
temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
|
* (signed64)State.regs[srcreg] & 0xff);
|
* (signed64)State.regs[srcreg] & 0xff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
|
// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
|
8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
|
8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
|
"macbu"
|
"macbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
|
temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
|
* (unsigned64)State.regs[srcreg] & 0xff);
|
* (unsigned64)State.regs[srcreg] & 0xff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
|
// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
|
8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
|
8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
|
"mach"
|
"mach"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
|
temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
|
* (signed64)State.regs[srcreg] & 0xffff);
|
* (signed64)State.regs[srcreg] & 0xffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
|
// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
|
8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
|
8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
|
"machu"
|
"machu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN2);
|
srcreg = translate_rreg (SD_, RN2);
|
|
|
temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
|
temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
|
* (unsigned64)State.regs[srcreg] & 0xffff);
|
* (unsigned64)State.regs[srcreg] & 0xffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
|
// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
|
8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
|
8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
|
// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
|
8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
|
8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
|
store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
|
}
|
}
|
|
|
|
|
// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
|
// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
|
8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
|
8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
|
// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
|
8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
|
8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
|
store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
|
}
|
}
|
|
|
|
|
// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
|
// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
|
8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
|
8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
|
State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
|
}
|
}
|
|
|
// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
|
// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
|
8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
|
8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
|
store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
|
}
|
}
|
|
|
|
|
// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
|
// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
|
8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
|
8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
}
|
}
|
|
|
// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
|
// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
|
8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
|
8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
|
"movu"
|
"movu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
}
|
}
|
|
|
// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
|
// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
|
8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
|
8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
|
"add"
|
"add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
|
genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
|
}
|
}
|
|
|
// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
|
// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
|
8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
|
8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
|
"addc"
|
"addc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
unsigned32 imm, reg2, sum;
|
unsigned32 imm, reg2, sum;
|
int z, n, c, v;
|
int z, n, c, v;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
reg2 = State.regs[dstreg];
|
reg2 = State.regs[dstreg];
|
sum = imm + reg2 + ((PSW & PSW_C) != 0);
|
sum = imm + reg2 + ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = sum;
|
State.regs[dstreg] = sum;
|
|
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
z = ((PSW & PSW_Z) != 0) && (sum == 0);
|
n = (sum & 0x80000000);
|
n = (sum & 0x80000000);
|
c = (sum < imm) || (sum < reg2);
|
c = (sum < imm) || (sum < reg2);
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
&& (reg2 & 0x80000000) != (sum & 0x80000000));
|
&& (reg2 & 0x80000000) != (sum & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
|
// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
|
8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
|
8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
|
"sub"
|
"sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
|
genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
|
}
|
}
|
|
|
// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
|
// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
|
8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
|
8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
|
"subc"
|
"subc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
unsigned32 imm, reg2, difference;
|
unsigned32 imm, reg2, difference;
|
int z, n, c, v;
|
int z, n, c, v;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
reg2 = State.regs[dstreg];
|
reg2 = State.regs[dstreg];
|
difference = reg2 - imm - ((PSW & PSW_C) != 0);
|
difference = reg2 - imm - ((PSW & PSW_C) != 0);
|
State.regs[dstreg] = difference;
|
State.regs[dstreg] = difference;
|
|
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
z = ((PSW & PSW_Z) != 0) && (difference == 0);
|
n = (difference & 0x80000000);
|
n = (difference & 0x80000000);
|
c = (imm > reg2);
|
c = (imm > reg2);
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
v = ((reg2 & 0x80000000) == (imm & 0x80000000)
|
&& (reg2 & 0x80000000) != (difference & 0x80000000));
|
&& (reg2 & 0x80000000) != (difference & 0x80000000));
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
}
|
}
|
|
|
// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
|
// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
|
8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
|
8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
|
"cmp"
|
"cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
|
// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
|
8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
|
8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_xreg (SD_, XRN0);
|
dstreg = translate_xreg (SD_, XRN0);
|
|
|
State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
|
}
|
}
|
|
|
// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
|
// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
|
8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
|
8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
|
"and"
|
"and"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z,n;
|
int z,n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
|
// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
|
8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
|
8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
|
"or"
|
"or"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z,n;
|
int z,n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
|
// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
|
8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
|
8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
|
"xor"
|
"xor"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z,n;
|
int z,n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
|
// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
|
8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
|
8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
|
"asr"
|
"asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
signed32 temp;
|
signed32 temp;
|
int c, z, n;
|
int c, z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = State.regs[dstreg];
|
temp = State.regs[dstreg];
|
c = temp & 1;
|
c = temp & 1;
|
temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
State.regs[dstreg] = temp;
|
State.regs[dstreg] = temp;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
|
// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
|
8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
|
8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
|
"lsr"
|
"lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n, c;
|
int z, n, c;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
c = State.regs[dstreg] & 1;
|
c = State.regs[dstreg] & 1;
|
State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
}
|
}
|
|
|
// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
|
// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
|
8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
|
8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
|
"asl"
|
"asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW &= ~(PSW_Z | PSW_N);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
|
// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
|
8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
|
8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
|
"mul"
|
"mul"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
unsigned64 temp;
|
unsigned64 temp;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((signed64)(signed32)State.regs[dstreg]
|
temp = ((signed64)(signed32)State.regs[dstreg]
|
* (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
|
* (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
|
// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
|
8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
|
8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
|
"mulu"
|
"mulu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
unsigned64 temp;
|
unsigned64 temp;
|
int z, n;
|
int z, n;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
|
|
temp = ((unsigned64)State.regs[dstreg]
|
temp = ((unsigned64)State.regs[dstreg]
|
* (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
|
* (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[dstreg] = temp & 0xffffffff;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
|
z = (State.regs[dstreg] == 0);
|
z = (State.regs[dstreg] == 0);
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
n = (State.regs[dstreg] & 0x80000000) != 0;
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
}
|
}
|
|
|
// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
|
// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
|
8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
|
8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
|
"btst"
|
"btst"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
|
// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
|
8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
|
8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[srcreg]
|
State.regs[dstreg] = load_word (State.regs[srcreg]
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
}
|
}
|
|
|
// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
|
// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
|
8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
|
8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
|
// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
|
8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
|
8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (State.regs[srcreg]
|
State.regs[dstreg] = load_byte (State.regs[srcreg]
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
}
|
}
|
|
|
// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
|
// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
|
8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
|
8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
|
// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
|
8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
|
8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[srcreg]
|
State.regs[dstreg] = load_half (State.regs[srcreg]
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
}
|
}
|
|
|
// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
|
// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
|
8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
|
8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
|
// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
|
8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
|
8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
}
|
}
|
|
|
// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
|
// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
|
8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
|
8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
store_word (State.regs[dstreg], State.regs[srcreg]);
|
State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
}
|
}
|
|
|
|
|
// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
|
// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
|
8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
|
8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (State.regs[REG_SP]
|
State.regs[dstreg] = load_word (State.regs[REG_SP]
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
}
|
}
|
|
|
// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
|
// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
|
8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
|
8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
|
// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
|
8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
|
8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (State.regs[REG_SP]
|
State.regs[dstreg] = load_byte (State.regs[REG_SP]
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
}
|
}
|
|
|
// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
|
// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
|
8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
|
8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
|
// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
|
8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
|
8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[REG_SP]
|
State.regs[dstreg] = load_half (State.regs[REG_SP]
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
}
|
}
|
|
|
// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
|
// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
|
8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
|
8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
|
State.regs[srcreg]);
|
State.regs[srcreg]);
|
}
|
}
|
|
|
|
|
// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
|
// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
|
8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
|
8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM0);
|
srcreg = translate_rreg (SD_, RM0);
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
State.regs[dstreg] = load_half (State.regs[srcreg]);
|
State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
}
|
}
|
|
|
// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
|
// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
|
8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
|
8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
store_half (State.regs[dstreg], State.regs[srcreg]);
|
State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
}
|
}
|
|
|
|
|
// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
|
// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
|
8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
|
8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
|
"mac"
|
"mac"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, imm;
|
int srcreg, imm;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((signed64)(signed32)State.regs[srcreg]
|
temp = ((signed64)(signed32)State.regs[srcreg]
|
* (signed64)(signed32)imm);
|
* (signed64)(signed32)imm);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
|
// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
|
8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
|
8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
|
"macu"
|
"macu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, imm;
|
int srcreg, imm;
|
signed64 temp, sum;
|
signed64 temp, sum;
|
int c, v;
|
int c, v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((unsigned64)State.regs[srcreg]
|
temp = ((unsigned64)State.regs[srcreg]
|
* (unsigned64)imm);
|
* (unsigned64)imm);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
temp >>= 32;
|
temp >>= 32;
|
temp &= 0xffffffff;
|
temp &= 0xffffffff;
|
sum = State.regs[REG_MCRH] + temp + c;
|
sum = State.regs[REG_MCRH] + temp + c;
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRH] = sum;
|
State.regs[REG_MCRH] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
|
// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
|
8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
|
8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
|
"macb"
|
"macb"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, imm;
|
int srcreg, imm;
|
signed32 temp, sum;
|
signed32 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
|
temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
|
* (signed32)(signed8)(imm & 0xff));
|
* (signed32)(signed8)(imm & 0xff));
|
sum = State.regs[REG_MCRL] + temp;
|
sum = State.regs[REG_MCRL] + temp;
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
|
// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
|
8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
|
8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
|
"macbu"
|
"macbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, imm;
|
int srcreg, imm;
|
signed32 temp, sum;
|
signed32 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((unsigned32)(State.regs[srcreg] & 0xff)
|
temp = ((unsigned32)(State.regs[srcreg] & 0xff)
|
* (unsigned32)(imm & 0xff));
|
* (unsigned32)(imm & 0xff));
|
sum = State.regs[REG_MCRL] + temp;
|
sum = State.regs[REG_MCRL] + temp;
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
|
// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
|
8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
|
8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
|
"mach"
|
"mach"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, imm;
|
int srcreg, imm;
|
signed32 temp, sum;
|
signed32 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
|
* (signed32)(signed16)(imm & 0xffff));
|
* (signed32)(signed16)(imm & 0xffff));
|
sum = State.regs[REG_MCRL] + temp;
|
sum = State.regs[REG_MCRL] + temp;
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
|
// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
|
8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
|
8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
|
"machu"
|
"machu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, imm;
|
int srcreg, imm;
|
signed32 temp, sum;
|
signed32 temp, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
|
temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
|
* (unsigned32)(imm & 0xffff));
|
* (unsigned32)(imm & 0xffff));
|
sum = State.regs[REG_MCRL] + temp;
|
sum = State.regs[REG_MCRL] + temp;
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
|
// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
|
8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
|
8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
|
"dmach"
|
"dmach"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, imm;
|
int srcreg, imm;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
|
* (signed32)(signed16)(imm & 0xffff));
|
* (signed32)(signed16)(imm & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
|
* (signed32)(signed16)((imm >> 16) & 0xffff));
|
* (signed32)(signed16)((imm >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
|
// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
|
8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
|
8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
|
"dmachu"
|
"dmachu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, imm;
|
int srcreg, imm;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
int v;
|
int v;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RN0);
|
srcreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
|
temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
|
* (unsigned32)(imm & 0xffff));
|
* (unsigned32)(imm & 0xffff));
|
temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
|
temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
|
* (unsigned32)((imm >> 16) & 0xffff));
|
* (unsigned32)((imm >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
&& (temp & 0x80000000) != (sum & 0x80000000));
|
State.regs[REG_MCRL] = sum;
|
State.regs[REG_MCRL] = sum;
|
if (v)
|
if (v)
|
State.regs[REG_MCVF] = 1;
|
State.regs[REG_MCVF] = 1;
|
}
|
}
|
|
|
// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
|
// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
|
8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
|
8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
|
"dmulh"
|
"dmulh"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int imm, dstreg;
|
int imm, dstreg;
|
signed32 temp;
|
signed32 temp;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
|
* (signed32)(signed16)(imm & 0xffff));
|
* (signed32)(signed16)(imm & 0xffff));
|
State.regs[REG_MDRQ] = temp;
|
State.regs[REG_MDRQ] = temp;
|
temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
|
temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
|
* (signed32)(signed16)((imm>>16) & 0xffff));
|
* (signed32)(signed16)((imm>>16) & 0xffff));
|
State.regs[dstreg] = temp;
|
State.regs[dstreg] = temp;
|
}
|
}
|
|
|
// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
|
// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
|
8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
|
8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
|
"dmulhu"
|
"dmulhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int imm, dstreg;
|
int imm, dstreg;
|
signed32 temp;
|
signed32 temp;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN0);
|
dstreg = translate_rreg (SD_, RN0);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
|
|
|
temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
|
temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
|
* (unsigned32)(imm & 0xffff));
|
* (unsigned32)(imm & 0xffff));
|
State.regs[REG_MDRQ] = temp;
|
State.regs[REG_MDRQ] = temp;
|
temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
|
temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
|
* (unsigned32)((imm >>16) & 0xffff));
|
* (unsigned32)((imm >>16) & 0xffff));
|
State.regs[dstreg] = temp;
|
State.regs[dstreg] = temp;
|
}
|
}
|
|
|
// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
|
// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
|
8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
|
8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
}
|
}
|
|
|
// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
|
// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
|
8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
|
8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
|
"mov"
|
"mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
|
// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
|
8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
|
8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
}
|
}
|
|
|
// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
|
// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
|
8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
|
8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
|
"movbu"
|
"movbu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
|
// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
|
8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
|
8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg;
|
int dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg = translate_rreg (SD_, RN2);
|
dstreg = translate_rreg (SD_, RN2);
|
State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
|
}
|
}
|
|
|
// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
|
// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
|
8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
|
8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
|
"movhu"
|
"movhu"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg;
|
int srcreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM2);
|
srcreg = translate_rreg (SD_, RM2);
|
store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
|
}
|
}
|
|
|
// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
|
8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
|
"add_add"
|
"add_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
|
8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
|
"add_add"
|
"add_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
|
8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
|
"add_sub"
|
"add_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
|
8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
|
"add_sub"
|
"add_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
|
8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
|
"add_cmp"
|
"add_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] += State.regs[srcreg1];
|
State.regs[dstreg1] += State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
|
8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
|
"add_cmp"
|
"add_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] += State.regs[srcreg1];
|
State.regs[dstreg1] += State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
|
8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
|
"add_mov"
|
"add_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
|
8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
|
"add_mov"
|
"add_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
|
8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
|
"add_asr"
|
"add_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
|
8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
|
"add_asr"
|
"add_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
|
8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
|
"add_lsr"
|
"add_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
|
8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
|
"add_lsr"
|
"add_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
|
8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
|
"add_asl"
|
"add_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
|
8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
|
"add_asl"
|
"add_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
result1 = State.regs[dstreg1] + State.regs[srcreg1];
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
|
8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
|
"cmp_add"
|
"cmp_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
|
8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
|
"cmp_add"
|
"cmp_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
}
|
}
|
|
|
// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
|
8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
|
"cmp_sub"
|
"cmp_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
|
8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
|
"cmp_sub"
|
"cmp_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
}
|
}
|
|
|
// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
|
8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
|
"cmp_mov"
|
"cmp_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
|
8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
|
"cmp_mov"
|
"cmp_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
}
|
}
|
|
|
// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
|
8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
|
"cmp_asr"
|
"cmp_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
}
|
}
|
|
|
// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
|
8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
|
"cmp_asr"
|
"cmp_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
}
|
}
|
|
|
// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
|
8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
|
"cmp_lsr"
|
"cmp_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
|
8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
|
"cmp_lsr"
|
"cmp_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
|
8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
|
"cmp_asl"
|
"cmp_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
|
8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
|
"cmp_asl"
|
"cmp_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
}
|
}
|
|
|
// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
|
8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
|
"sub_add"
|
"sub_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
|
8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
|
"sub_add"
|
"sub_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
|
8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
|
"sub_sub"
|
"sub_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
|
8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
|
"sub_sub"
|
"sub_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
|
8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
|
"sub_cmp"
|
"sub_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] -= State.regs[srcreg1];
|
State.regs[dstreg1] -= State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
|
8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
|
"sub_cmp"
|
"sub_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] -= State.regs[srcreg1];
|
State.regs[dstreg1] -= State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
|
8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
|
"sub_mov"
|
"sub_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
|
8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
|
"sub_mov"
|
"sub_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
|
8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
|
"sub_asr"
|
"sub_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
|
8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
|
"sub_asr"
|
"sub_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
|
8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
|
"sub_lsr"
|
"sub_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
|
8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
|
"sub_lsr"
|
"sub_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
|
8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
|
"sub_asl"
|
"sub_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
|
8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
|
"sub_asl"
|
"sub_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
result1 = State.regs[dstreg1] - State.regs[srcreg1];
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
|
8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
|
"mov_add"
|
"mov_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
|
8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
|
"mov_add"
|
"mov_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
|
8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
|
"mov_sub"
|
"mov_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
|
8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
|
"mov_sub"
|
"mov_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
|
8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
|
"mov_cmp"
|
"mov_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] = State.regs[srcreg1];
|
State.regs[dstreg1] = State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
|
8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
|
"mov_cmp"
|
"mov_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] = State.regs[srcreg1];
|
State.regs[dstreg1] = State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
|
8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
|
"mov_mov"
|
"mov_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
|
8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
|
"mov_mov"
|
"mov_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
|
8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
|
"mov_asr"
|
"mov_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
|
8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
|
"mov_asr"
|
"mov_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
|
8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
|
"mov_lsr"
|
"mov_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
|
8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
|
"mov_lsr"
|
"mov_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
|
8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
|
"mov_asl"
|
"mov_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
|
8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
|
"mov_asl"
|
"mov_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
|
8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
|
"add_add"
|
"add_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
|
// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
|
8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
|
"add_add"
|
"add_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
|
8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
|
"add_sub"
|
"add_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
|
// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
|
8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
|
"add_sub"
|
"add_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
|
8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
|
"add_cmp"
|
"add_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] += EXTEND4 (IMM4A);
|
State.regs[dstreg1] += EXTEND4 (IMM4A);
|
}
|
}
|
|
|
// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
|
// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
|
8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
|
"add_cmp"
|
"add_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] += EXTEND4 (IMM4A);
|
State.regs[dstreg1] += EXTEND4 (IMM4A);
|
}
|
}
|
|
|
// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
|
8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
|
"add_mov"
|
"add_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
|
// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
|
8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
|
"add_mov"
|
"add_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
|
8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
|
"add_asr"
|
"add_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
|
// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
|
8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
|
"add_asr"
|
"add_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
|
8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
|
"add_lsr"
|
"add_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
|
// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
|
8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
|
"add_lsr"
|
"add_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
|
8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
|
"add_asl"
|
"add_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
|
// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
|
8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
|
"add_asl"
|
"add_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
|
8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
|
"cmp_add"
|
"cmp_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
|
// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
|
8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
|
"cmp_add"
|
"cmp_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
}
|
}
|
|
|
// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
|
8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
|
"cmp_sub"
|
"cmp_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
|
// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
|
8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
|
"cmp_sub"
|
"cmp_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
}
|
}
|
|
|
// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
|
8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
|
"cmp_mov"
|
"cmp_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
|
// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
|
8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
|
"cmp_mov"
|
"cmp_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
}
|
}
|
|
|
// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
|
8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
|
"cmp_asr"
|
"cmp_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
}
|
}
|
|
|
// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
|
// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
|
8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
|
"cmp_asr"
|
"cmp_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
}
|
}
|
|
|
// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
|
8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
|
"cmp_lsr"
|
"cmp_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
|
// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
|
8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
|
"cmp_lsr"
|
"cmp_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
|
8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
|
"cmp_asl"
|
"cmp_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
}
|
}
|
|
|
// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
|
// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
|
8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
|
"cmp_asl"
|
"cmp_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
}
|
}
|
|
|
// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
|
8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
|
"sub_add"
|
"sub_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
|
// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
|
8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
|
"sub_add"
|
"sub_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
|
8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
|
"sub_sub"
|
"sub_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
|
// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
|
8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
|
"sub_sub"
|
"sub_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
|
8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
|
"sub_cmp"
|
"sub_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] -= EXTEND4 (IMM4A);
|
State.regs[dstreg1] -= EXTEND4 (IMM4A);
|
}
|
}
|
|
|
// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
|
// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
|
8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
|
"sub_cmp"
|
"sub_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] -= EXTEND4 (IMM4A);
|
State.regs[dstreg1] -= EXTEND4 (IMM4A);
|
}
|
}
|
|
|
// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
|
8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
|
"sub_mov"
|
"sub_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
|
// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
|
8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
|
"sub_mov"
|
"sub_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
|
8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
|
"sub_asr"
|
"sub_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
|
// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
|
8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
|
"sub_asr"
|
"sub_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
|
8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
|
"sub_lsr"
|
"sub_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
|
// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
|
8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
|
"sub_lsr"
|
"sub_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
|
8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
|
"sub_asl"
|
"sub_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
|
// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
|
8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
|
"sub_asl"
|
"sub_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
|
8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
|
"mov_add"
|
"mov_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
|
// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
|
8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
|
"mov_add"
|
"mov_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
|
8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
|
"mov_sub"
|
"mov_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
|
// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
|
8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
|
"mov_sub"
|
"mov_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
|
8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
|
"mov_cmp"
|
"mov_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] = EXTEND4 (IMM4A);
|
State.regs[dstreg1] = EXTEND4 (IMM4A);
|
}
|
}
|
|
|
// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
|
// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
|
8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
|
"mov_cmp"
|
"mov_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] = EXTEND4 (IMM4A);
|
State.regs[dstreg1] = EXTEND4 (IMM4A);
|
}
|
}
|
|
|
// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
|
// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
|
8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
|
"mov_mov"
|
"mov_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
|
// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
|
8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
|
"mov_mov"
|
"mov_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
|
8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
|
"mov_asr"
|
"mov_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
|
// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
|
8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
|
"mov_asr"
|
"mov_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
|
8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
|
"mov_lsr"
|
"mov_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
|
// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
|
8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
|
"mov_lsr"
|
"mov_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
|
// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
|
8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
|
"mov_asl"
|
"mov_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg2, dstreg1, dstreg2;
|
int srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
|
// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
|
8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
|
8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
|
"mov_asl"
|
"mov_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int dstreg1, dstreg2;
|
int dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = EXTEND4 (IMM4A);
|
result1 = EXTEND4 (IMM4A);
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
|
8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
|
"and_add"
|
"and_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
|
8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
|
"and_add"
|
"and_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
|
8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
|
"and_sub"
|
"and_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
|
8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
|
"and_sub"
|
"and_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
|
8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
|
"and_cmp"
|
"and_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] &= State.regs[srcreg1];
|
State.regs[dstreg1] &= State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
|
8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
|
"and_cmp"
|
"and_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] &= State.regs[srcreg1];
|
State.regs[dstreg1] &= State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
|
8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
|
"and_mov"
|
"and_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
|
8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
|
"and_mov"
|
"and_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
|
8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
|
"and_asr"
|
"and_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
|
8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
|
"and_asr"
|
"and_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
|
8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
|
"and_lsr"
|
"and_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
|
8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
|
"and_lsr"
|
"and_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
|
8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
|
"and_asl"
|
"and_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
|
8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
|
"and_asl"
|
"and_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
result1 = State.regs[dstreg1] & State.regs[srcreg1];
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
|
8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
|
"dmach_add"
|
"dmach_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
|
8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
|
"dmach_add"
|
"dmach_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
|
8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
|
"dmach_sub"
|
"dmach_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
|
8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
|
"dmach_sub"
|
"dmach_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
|
8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
|
"dmach_cmp"
|
"dmach_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
|
8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
|
"dmach_cmp"
|
"dmach_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
|
8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
|
"dmach_mov"
|
"dmach_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
|
8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
|
"dmach_mov"
|
"dmach_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
|
8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
|
"dmach_asr"
|
"dmach_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
|
8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
|
"dmach_asr"
|
"dmach_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
|
8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
|
"dmach_lsr"
|
"dmach_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
|
8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
|
"dmach_lsr"
|
"dmach_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
|
8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
|
"dmach_asl"
|
"dmach_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
|
8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
|
"dmach_asl"
|
"dmach_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
signed32 temp, temp2, sum;
|
signed32 temp, temp2, sum;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
* (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
* (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
sum = temp + temp2 + State.regs[REG_MCRL];
|
|
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = sum;
|
State.regs[dstreg1] = sum;
|
}
|
}
|
|
|
// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
|
8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
|
"xor_add"
|
"xor_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
|
8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
|
"xor_add"
|
"xor_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
|
8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
|
"xor_sub"
|
"xor_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
|
8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
|
"xor_sub"
|
"xor_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
|
8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
|
"xor_cmp"
|
"xor_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] ^= State.regs[srcreg1];
|
State.regs[dstreg1] ^= State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
|
8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
|
"xor_cmp"
|
"xor_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] ^= State.regs[srcreg1];
|
State.regs[dstreg1] ^= State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
|
8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
|
"xor_mov"
|
"xor_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
|
8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
|
"xor_mov"
|
"xor_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
|
8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
|
"xor_asr"
|
"xor_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
|
8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
|
"xor_asr"
|
"xor_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
|
8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
|
"xor_lsr"
|
"xor_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
|
8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
|
"xor_lsr"
|
"xor_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
|
8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
|
"xor_asl"
|
"xor_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
|
8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
|
"xor_asl"
|
"xor_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
|
8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
|
"swhw_add"
|
"swhw_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
|
8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
|
"swhw_add"
|
"swhw_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
|
8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
|
"swhw_sub"
|
"swhw_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
|
8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
|
"swhw_sub"
|
"swhw_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
|
8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
|
"swhw_cmp"
|
"swhw_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
|
State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
}
|
}
|
|
|
// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
|
8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
|
"swhw_cmp"
|
"swhw_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
|
State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
}
|
}
|
|
|
// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
|
8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
|
"swhw_mov"
|
"swhw_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
|
8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
|
"swhw_mov"
|
"swhw_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
|
8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
|
"swhw_asr"
|
"swhw_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
|
8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
|
"swhw_asr"
|
"swhw_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
|
8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
|
"swhw_lsr"
|
"swhw_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
|
8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
|
"swhw_lsr"
|
"swhw_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
|
8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
|
"swhw_asl"
|
"swhw_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
|
8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
|
"swhw_asl"
|
"swhw_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
result1 = (((State.regs[srcreg1] & 0xffff) << 16)
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
| ((State.regs[srcreg1] >> 16) & 0xffff));
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
|
8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
|
"or_add"
|
"or_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
|
8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
|
"or_add"
|
"or_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
|
8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
|
"or_sub"
|
"or_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
|
8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
|
"or_sub"
|
"or_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
|
8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
|
"or_cmp"
|
"or_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
|
State.regs[dstreg1] |= State.regs[srcreg1];
|
State.regs[dstreg1] |= State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
|
8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
|
"or_cmp"
|
"or_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
State.regs[dstreg1] |= State.regs[srcreg1];
|
State.regs[dstreg1] |= State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
|
8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
|
"or_mov"
|
"or_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
|
8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
|
"or_mov"
|
"or_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
|
8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
|
"or_asr"
|
"or_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
|
8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
|
"or_asr"
|
"or_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
|
8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
|
"or_lsr"
|
"or_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
|
8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
|
"or_lsr"
|
"or_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
|
8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
|
"or_asl"
|
"or_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
|
8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
|
"or_asl"
|
"or_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
result1 = State.regs[dstreg1] | State.regs[srcreg1];
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
|
8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
|
"sat16_add"
|
"sat16_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg2] += State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
|
8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
|
"sat16_add"
|
"sat16_add"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg2] += EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
|
8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
|
"sat16_sub"
|
"sat16_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg2] -= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
|
8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
|
"sat16_sub"
|
"sat16_sub"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg2] -= EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
|
8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
|
"sat16_cmp"
|
"sat16_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (State.regs[dstreg2], State.regs[dstreg1]);
|
genericCmp (State.regs[dstreg2], State.regs[dstreg1]);
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
State.regs[dstreg1] = 0x7fff;
|
State.regs[dstreg1] = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
State.regs[dstreg1] = 0xffff8000;
|
State.regs[dstreg1] = 0xffff8000;
|
else
|
else
|
State.regs[dstreg1] = State.regs[srcreg1];
|
State.regs[dstreg1] = State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
|
8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
|
"sat16_cmp"
|
"sat16_cmp"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
State.regs[dstreg1] = 0x7fff;
|
State.regs[dstreg1] = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
State.regs[dstreg1] = 0xffff8000;
|
State.regs[dstreg1] = 0xffff8000;
|
else
|
else
|
State.regs[dstreg1] = State.regs[srcreg1];
|
State.regs[dstreg1] = State.regs[srcreg1];
|
}
|
}
|
|
|
// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
|
8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
|
"sat16_mov"
|
"sat16_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg2] = State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
|
// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
|
8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
|
"sat16_mov"
|
"sat16_mov"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg2] = EXTEND4 (IMM4);
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
|
8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
|
"sat16_asr"
|
"sat16_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= State.regs[srcreg2];
|
temp >>= State.regs[srcreg2];
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
|
8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
|
"sat16_asr"
|
"sat16_asr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
signed int temp;
|
signed int temp;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
temp = State.regs[dstreg2];
|
temp = State.regs[dstreg2];
|
temp >>= IMM4;
|
temp >>= IMM4;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg2] = temp;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
|
8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
|
"sat16_lsr"
|
"sat16_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg2] >>= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
|
8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
|
"sat16_lsr"
|
"sat16_lsr"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg2] >>= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
|
|
// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
|
// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
|
8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
|
8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
|
"sat16_asl"
|
"sat16_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int srcreg1, srcreg2, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg2 = translate_rreg (SD_, RM2);
|
srcreg2 = translate_rreg (SD_, RM2);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg2] <<= State.regs[srcreg2];
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
|
// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
|
8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
|
8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
|
"sat16_asl"
|
"sat16_asl"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg1, dstreg1, dstreg2;
|
int srcreg1, dstreg1, dstreg2;
|
int result1;
|
int result1;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg1 = translate_rreg (SD_, RM1);
|
srcreg1 = translate_rreg (SD_, RM1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg1 = translate_rreg (SD_, RN1);
|
dstreg2 = translate_rreg (SD_, RN2);
|
dstreg2 = translate_rreg (SD_, RN2);
|
|
|
if (State.regs[srcreg1] >= 0x7fff)
|
if (State.regs[srcreg1] >= 0x7fff)
|
result1 = 0x7fff;
|
result1 = 0x7fff;
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
else if (State.regs[srcreg1] <= 0xffff8000)
|
result1 = 0xffff8000;
|
result1 = 0xffff8000;
|
else
|
else
|
result1 = State.regs[srcreg1];
|
result1 = State.regs[srcreg1];
|
|
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg2] <<= IMM4;
|
State.regs[dstreg1] = result1;
|
State.regs[dstreg1] = result1;
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
|
"mov_llt"
|
"mov_llt"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
|
if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
|
"mov_lgt"
|
"mov_lgt"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if (!((PSW & PSW_Z)
|
if (!((PSW & PSW_Z)
|
|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
|
|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
|
"mov_lge"
|
"mov_lge"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
|
if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
|
"mov_lle"
|
"mov_lle"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if ((PSW & PSW_Z)
|
if ((PSW & PSW_Z)
|
|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
|
|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
|
"mov_lcs"
|
"mov_lcs"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if (PSW & PSW_C)
|
if (PSW & PSW_C)
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
|
"mov_lhi"
|
"mov_lhi"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
|
if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
|
"mov_lcc"
|
"mov_lcc"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if (!(PSW & PSW_C))
|
if (!(PSW & PSW_C))
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
|
"mov_lls"
|
"mov_lls"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
|
if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
|
"mov_leq"
|
"mov_leq"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if (PSW & PSW_Z)
|
if (PSW & PSW_Z)
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
|
"mov_lne"
|
"mov_lne"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
if (!(PSW & PSW_Z))
|
if (!(PSW & PSW_Z))
|
{
|
{
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
}
|
}
|
|
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
|
// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
|
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
|
"mov_lra"
|
"mov_lra"
|
*am33
|
*am33
|
*am33_2
|
*am33_2
|
{
|
{
|
int srcreg, dstreg;
|
int srcreg, dstreg;
|
|
|
PC = cia;
|
PC = cia;
|
srcreg = translate_rreg (SD_, RM);
|
srcreg = translate_rreg (SD_, RM);
|
dstreg = translate_rreg (SD_, RN);
|
dstreg = translate_rreg (SD_, RN);
|
|
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[dstreg] = load_word (State.regs[srcreg]);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
State.regs[srcreg] += EXTEND4 (IMM4);
|
|
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
|
nia = PC;
|
nia = PC;
|
}
|
}
|
|
|
:include::am33_2:am33-2.igen
|
:include::am33_2:am33-2.igen
|
|
|
