/* This file is part of the program GDB, the GNU debugger.
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/* This file is part of the program GDB, the GNU debugger.
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Copyright (C) 1998, 2007, 2008 Free Software Foundation, Inc.
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Copyright (C) 1998, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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Contributed by Cygnus Solutions.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#include "sim-main.h"
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#include "sim-main.h"
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#include "hw-main.h"
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#include "hw-main.h"
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#include "sim-hw.h"
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#include "sim-hw.h"
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/* DEVICE
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/* DEVICE
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mn103int - mn103002 interrupt controller
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mn103int - mn103002 interrupt controller
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DESCRIPTION
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DESCRIPTION
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Implements the mn103002 interrupt controller described in the
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Implements the mn103002 interrupt controller described in the
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mn103002 user guide.
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mn103002 user guide.
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PROPERTIES
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PROPERTIES
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reg = <icr-adr> <icr-siz> <iagr-adr> <iadr-siz> <extmd-adr> <extmd-siz>
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reg = <icr-adr> <icr-siz> <iagr-adr> <iadr-siz> <extmd-adr> <extmd-siz>
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Specify the address of the ICR (total of 30 registers), IAGR and
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Specify the address of the ICR (total of 30 registers), IAGR and
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EXTMD registers (within the parent bus).
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EXTMD registers (within the parent bus).
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The reg property value `0x34000100 0x7C 0x34000200 0x8 0x3400280
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The reg property value `0x34000100 0x7C 0x34000200 0x8 0x3400280
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0x8' locates the interrupt controller at the addresses specified in
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0x8' locates the interrupt controller at the addresses specified in
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the mn103002 interrupt controller user guide.
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the mn103002 interrupt controller user guide.
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PORTS
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PORTS
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nmi (output)
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nmi (output)
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Non-maskable interrupt output port. An event on this output ports
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Non-maskable interrupt output port. An event on this output ports
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indicates a NMI request from the interrupt controller. The value
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indicates a NMI request from the interrupt controller. The value
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attached to the event should be ignored.
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attached to the event should be ignored.
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level (output)
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level (output)
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Maskable interrupt level output port. An event on this output port
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Maskable interrupt level output port. An event on this output port
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indicates a maskable interrupt request at the specified level. The
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indicates a maskable interrupt request at the specified level. The
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event value defines the level being requested.
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event value defines the level being requested.
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The interrupt controller will generate an event on this port
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The interrupt controller will generate an event on this port
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whenever there is a change to the internal state of the interrupt
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whenever there is a change to the internal state of the interrupt
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controller.
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controller.
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ack (input)
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ack (input)
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Signal from processor indicating that a maskable interrupt has been
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Signal from processor indicating that a maskable interrupt has been
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accepted and the interrupt controller should latch the IAGR with
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accepted and the interrupt controller should latch the IAGR with
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value of the current highest priority interrupting group.
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value of the current highest priority interrupting group.
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The event value is the interrupt level being accepted by the
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The event value is the interrupt level being accepted by the
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processor. It should be consistent with the most recent LEVEL sent
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processor. It should be consistent with the most recent LEVEL sent
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to the processor from the interrupt controller.
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to the processor from the interrupt controller.
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int[0..100] (input)
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int[0..100] (input)
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Level or edge triggered interrupt input port. Each of the 30
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Level or edge triggered interrupt input port. Each of the 30
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groups (0..30) can have up to 4 (0..3) interrupt inputs. The
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groups (0..30) can have up to 4 (0..3) interrupt inputs. The
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interpretation of a port event/value is determined by the
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interpretation of a port event/value is determined by the
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configuration of the corresponding interrupt group.
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configuration of the corresponding interrupt group.
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For convenience, numerous aliases to these interrupt inputs are
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For convenience, numerous aliases to these interrupt inputs are
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provided.
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provided.
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BUGS
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BUGS
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For edge triggered interrupts, the interrupt controller does not
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For edge triggered interrupts, the interrupt controller does not
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differentiate between POSITIVE (rising) and NEGATIVE (falling)
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differentiate between POSITIVE (rising) and NEGATIVE (falling)
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edges. Instead any input port event is considered to be an
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edges. Instead any input port event is considered to be an
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interrupt trigger.
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interrupt trigger.
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For level sensitive interrupts, the interrupt controller ignores
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For level sensitive interrupts, the interrupt controller ignores
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active HIGH/LOW settings and instead always interprets a nonzero
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active HIGH/LOW settings and instead always interprets a nonzero
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port value as an interrupt assertion and a zero port value as a
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port value as an interrupt assertion and a zero port value as a
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negation.
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negation.
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*/
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*/
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/* The interrupt groups - numbered according to mn103002 convention */
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/* The interrupt groups - numbered according to mn103002 convention */
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enum mn103int_trigger {
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enum mn103int_trigger {
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ACTIVE_LOW,
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ACTIVE_LOW,
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ACTIVE_HIGH,
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ACTIVE_HIGH,
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POSITIVE_EDGE,
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POSITIVE_EDGE,
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NEGATIVE_EDGE,
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NEGATIVE_EDGE,
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};
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};
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enum mn103int_type {
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enum mn103int_type {
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NMI_GROUP,
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NMI_GROUP,
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LEVEL_GROUP,
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LEVEL_GROUP,
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};
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};
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struct mn103int_group {
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struct mn103int_group {
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int gid;
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int gid;
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int level;
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int level;
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unsigned enable;
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unsigned enable;
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unsigned request;
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unsigned request;
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unsigned input;
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unsigned input;
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enum mn103int_trigger trigger;
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enum mn103int_trigger trigger;
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enum mn103int_type type;
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enum mn103int_type type;
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};
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};
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enum {
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enum {
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FIRST_NMI_GROUP = 0,
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FIRST_NMI_GROUP = 0,
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LAST_NMI_GROUP = 1,
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LAST_NMI_GROUP = 1,
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FIRST_LEVEL_GROUP = 2,
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FIRST_LEVEL_GROUP = 2,
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LAST_LEVEL_GROUP = 30,
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LAST_LEVEL_GROUP = 30,
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NR_GROUPS,
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NR_GROUPS,
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};
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};
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enum {
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enum {
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LOWEST_LEVEL = 7,
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LOWEST_LEVEL = 7,
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};
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};
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/* The interrupt controller register address blocks */
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/* The interrupt controller register address blocks */
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struct mn103int_block {
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struct mn103int_block {
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unsigned_word base;
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unsigned_word base;
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unsigned_word bound;
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unsigned_word bound;
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};
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};
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enum { ICR_BLOCK, IAGR_BLOCK, EXTMD_BLOCK, NR_BLOCKS };
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enum { ICR_BLOCK, IAGR_BLOCK, EXTMD_BLOCK, NR_BLOCKS };
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struct mn103int {
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struct mn103int {
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struct mn103int_block block[NR_BLOCKS];
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struct mn103int_block block[NR_BLOCKS];
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struct mn103int_group group[NR_GROUPS];
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struct mn103int_group group[NR_GROUPS];
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unsigned interrupt_accepted_group;
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unsigned interrupt_accepted_group;
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};
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};
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/* output port ID's */
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/* output port ID's */
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enum {
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enum {
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NMI_PORT,
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NMI_PORT,
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LEVEL_PORT,
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LEVEL_PORT,
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};
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};
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/* input port ID's */
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/* input port ID's */
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enum {
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enum {
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G0_PORT = 0,
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G0_PORT = 0,
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G1_PORT = 4,
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G1_PORT = 4,
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G2_PORT = 8,
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G2_PORT = 8,
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G3_PORT = 12,
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G3_PORT = 12,
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G4_PORT = 16,
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G4_PORT = 16,
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G5_PORT = 20,
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G5_PORT = 20,
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G6_PORT = 24,
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G6_PORT = 24,
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G7_PORT = 28,
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G7_PORT = 28,
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G8_PORT = 32,
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G8_PORT = 32,
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G9_PORT = 36,
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G9_PORT = 36,
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G10_PORT = 40,
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G10_PORT = 40,
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G11_PORT = 44,
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G11_PORT = 44,
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G12_PORT = 48,
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G12_PORT = 48,
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G13_PORT = 52,
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G13_PORT = 52,
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G14_PORT = 56,
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G14_PORT = 56,
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G15_PORT = 60,
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G15_PORT = 60,
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G16_PORT = 64,
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G16_PORT = 64,
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G17_PORT = 68,
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G17_PORT = 68,
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G18_PORT = 72,
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G18_PORT = 72,
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G19_PORT = 76,
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G19_PORT = 76,
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G20_PORT = 80,
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G20_PORT = 80,
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G21_PORT = 84,
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G21_PORT = 84,
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G22_PORT = 88,
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G22_PORT = 88,
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G23_PORT = 92,
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G23_PORT = 92,
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IRQ0_PORT = G23_PORT,
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IRQ0_PORT = G23_PORT,
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G24_PORT = 96,
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G24_PORT = 96,
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G25_PORT = 100,
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G25_PORT = 100,
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G26_PORT = 104,
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G26_PORT = 104,
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G27_PORT = 108,
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G27_PORT = 108,
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IRQ4_PORT = G27_PORT,
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IRQ4_PORT = G27_PORT,
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G28_PORT = 112,
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G28_PORT = 112,
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G29_PORT = 116,
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G29_PORT = 116,
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G30_PORT = 120,
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G30_PORT = 120,
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NR_G_PORTS = 124,
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NR_G_PORTS = 124,
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ACK_PORT,
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ACK_PORT,
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};
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};
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static const struct hw_port_descriptor mn103int_ports[] = {
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static const struct hw_port_descriptor mn103int_ports[] = {
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/* interrupt outputs */
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/* interrupt outputs */
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{ "nmi", NMI_PORT, 0, output_port, },
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{ "nmi", NMI_PORT, 0, output_port, },
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{ "level", LEVEL_PORT, 0, output_port, },
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{ "level", LEVEL_PORT, 0, output_port, },
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/* interrupt ack (latch) input from cpu */
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/* interrupt ack (latch) input from cpu */
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{ "ack", ACK_PORT, 0, input_port, },
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{ "ack", ACK_PORT, 0, input_port, },
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/* interrupt inputs (as names) */
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/* interrupt inputs (as names) */
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{ "nmirq", G0_PORT + 0, 0, input_port, },
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{ "nmirq", G0_PORT + 0, 0, input_port, },
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{ "watchdog", G0_PORT + 1, 0, input_port, },
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{ "watchdog", G0_PORT + 1, 0, input_port, },
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{ "syserr", G0_PORT + 2, 0, input_port, },
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{ "syserr", G0_PORT + 2, 0, input_port, },
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{ "timer-0-underflow", G2_PORT, 0, input_port, },
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{ "timer-0-underflow", G2_PORT, 0, input_port, },
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{ "timer-1-underflow", G3_PORT, 0, input_port, },
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{ "timer-1-underflow", G3_PORT, 0, input_port, },
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{ "timer-2-underflow", G4_PORT, 0, input_port, },
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{ "timer-2-underflow", G4_PORT, 0, input_port, },
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{ "timer-3-underflow", G5_PORT, 0, input_port, },
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{ "timer-3-underflow", G5_PORT, 0, input_port, },
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{ "timer-4-underflow", G6_PORT, 0, input_port, },
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{ "timer-4-underflow", G6_PORT, 0, input_port, },
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{ "timer-5-underflow", G7_PORT, 0, input_port, },
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{ "timer-5-underflow", G7_PORT, 0, input_port, },
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{ "timer-6-underflow", G8_PORT, 0, input_port, },
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{ "timer-6-underflow", G8_PORT, 0, input_port, },
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{ "timer-6-compare-a", G9_PORT, 0, input_port, },
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{ "timer-6-compare-a", G9_PORT, 0, input_port, },
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{ "timer-6-compare-b", G10_PORT, 0, input_port, },
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{ "timer-6-compare-b", G10_PORT, 0, input_port, },
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{ "dma-0-end", G12_PORT, 0, input_port, },
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{ "dma-0-end", G12_PORT, 0, input_port, },
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{ "dma-1-end", G13_PORT, 0, input_port, },
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{ "dma-1-end", G13_PORT, 0, input_port, },
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{ "dma-2-end", G14_PORT, 0, input_port, },
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{ "dma-2-end", G14_PORT, 0, input_port, },
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{ "dma-3-end", G15_PORT, 0, input_port, },
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{ "dma-3-end", G15_PORT, 0, input_port, },
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{ "serial-0-receive", G16_PORT, 0, input_port, },
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{ "serial-0-receive", G16_PORT, 0, input_port, },
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{ "serial-0-transmit", G17_PORT, 0, input_port, },
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{ "serial-0-transmit", G17_PORT, 0, input_port, },
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{ "serial-1-receive", G18_PORT, 0, input_port, },
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{ "serial-1-receive", G18_PORT, 0, input_port, },
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{ "serial-1-transmit", G19_PORT, 0, input_port, },
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{ "serial-1-transmit", G19_PORT, 0, input_port, },
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{ "serial-2-receive", G20_PORT, 0, input_port, },
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{ "serial-2-receive", G20_PORT, 0, input_port, },
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{ "serial-2-transmit", G21_PORT, 0, input_port, },
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{ "serial-2-transmit", G21_PORT, 0, input_port, },
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{ "irq-0", G23_PORT, 0, input_port, },
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{ "irq-0", G23_PORT, 0, input_port, },
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{ "irq-1", G24_PORT, 0, input_port, },
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{ "irq-1", G24_PORT, 0, input_port, },
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{ "irq-2", G25_PORT, 0, input_port, },
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{ "irq-2", G25_PORT, 0, input_port, },
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{ "irq-3", G26_PORT, 0, input_port, },
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{ "irq-3", G26_PORT, 0, input_port, },
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{ "irq-4", G27_PORT, 0, input_port, },
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{ "irq-4", G27_PORT, 0, input_port, },
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{ "irq-5", G28_PORT, 0, input_port, },
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{ "irq-5", G28_PORT, 0, input_port, },
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{ "irq-6", G29_PORT, 0, input_port, },
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{ "irq-6", G29_PORT, 0, input_port, },
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{ "irq-7", G30_PORT, 0, input_port, },
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{ "irq-7", G30_PORT, 0, input_port, },
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/* interrupt inputs (as generic numbers) */
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/* interrupt inputs (as generic numbers) */
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{ "int", 0, NR_G_PORTS, input_port, },
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{ "int", 0, NR_G_PORTS, input_port, },
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{ NULL, },
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{ NULL, },
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};
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};
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/* Macros for extracting/restoring the various register bits */
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/* Macros for extracting/restoring the various register bits */
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#define EXTRACT_ID(X) (LSEXTRACTED8 ((X), 3, 0))
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#define EXTRACT_ID(X) (LSEXTRACTED8 ((X), 3, 0))
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#define INSERT_ID(X) (LSINSERTED8 ((X), 3, 0))
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#define INSERT_ID(X) (LSINSERTED8 ((X), 3, 0))
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#define EXTRACT_IR(X) (LSEXTRACTED8 ((X), 7, 4))
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#define EXTRACT_IR(X) (LSEXTRACTED8 ((X), 7, 4))
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#define INSERT_IR(X) (LSINSERTED8 ((X), 7, 4))
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#define INSERT_IR(X) (LSINSERTED8 ((X), 7, 4))
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#define EXTRACT_IE(X) (LSEXTRACTED8 ((X), 3, 0))
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#define EXTRACT_IE(X) (LSEXTRACTED8 ((X), 3, 0))
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#define INSERT_IE(X) (LSINSERTED8 ((X), 3, 0))
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#define INSERT_IE(X) (LSINSERTED8 ((X), 3, 0))
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#define EXTRACT_LV(X) (LSEXTRACTED8 ((X), 6, 4))
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#define EXTRACT_LV(X) (LSEXTRACTED8 ((X), 6, 4))
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#define INSERT_LV(X) (LSINSERTED8 ((X), 6, 4))
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#define INSERT_LV(X) (LSINSERTED8 ((X), 6, 4))
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/* Finish off the partially created hw device. Attach our local
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc */
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callbacks. Wire up our port names etc */
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static hw_io_read_buffer_method mn103int_io_read_buffer;
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static hw_io_read_buffer_method mn103int_io_read_buffer;
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static hw_io_write_buffer_method mn103int_io_write_buffer;
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static hw_io_write_buffer_method mn103int_io_write_buffer;
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static hw_port_event_method mn103int_port_event;
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static hw_port_event_method mn103int_port_event;
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static hw_ioctl_method mn103int_ioctl;
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static hw_ioctl_method mn103int_ioctl;
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static void
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static void
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attach_mn103int_regs (struct hw *me,
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attach_mn103int_regs (struct hw *me,
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struct mn103int *controller)
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struct mn103int *controller)
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{
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{
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int i;
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int i;
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if (hw_find_property (me, "reg") == NULL)
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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hw_abort (me, "Missing \"reg\" property");
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for (i = 0; i < NR_BLOCKS; i++)
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for (i = 0; i < NR_BLOCKS; i++)
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{
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{
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unsigned_word attach_address;
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unsigned_word attach_address;
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int attach_space;
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int attach_space;
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unsigned attach_size;
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unsigned attach_size;
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reg_property_spec reg;
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reg_property_spec reg;
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if (!hw_find_reg_array_property (me, "reg", i, ®))
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if (!hw_find_reg_array_property (me, "reg", i, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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®.address,
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&attach_space,
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&attach_space,
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&attach_address,
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&attach_address,
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me);
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me);
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controller->block[i].base = attach_address;
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controller->block[i].base = attach_address;
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hw_unit_size_to_attach_size (hw_parent (me),
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hw_unit_size_to_attach_size (hw_parent (me),
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®.size,
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®.size,
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&attach_size, me);
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&attach_size, me);
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controller->block[i].bound = attach_address + (attach_size - 1);
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controller->block[i].bound = attach_address + (attach_size - 1);
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hw_attach_address (hw_parent (me),
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hw_attach_address (hw_parent (me),
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0,
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0,
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attach_space, attach_address, attach_size,
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attach_space, attach_address, attach_size,
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me);
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me);
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}
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}
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}
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}
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|
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static void
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static void
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mn103int_finish (struct hw *me)
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mn103int_finish (struct hw *me)
|
{
|
{
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int gid;
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int gid;
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struct mn103int *controller;
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struct mn103int *controller;
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controller = HW_ZALLOC (me, struct mn103int);
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controller = HW_ZALLOC (me, struct mn103int);
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set_hw_data (me, controller);
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set_hw_data (me, controller);
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set_hw_io_read_buffer (me, mn103int_io_read_buffer);
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set_hw_io_read_buffer (me, mn103int_io_read_buffer);
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set_hw_io_write_buffer (me, mn103int_io_write_buffer);
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set_hw_io_write_buffer (me, mn103int_io_write_buffer);
|
set_hw_ports (me, mn103int_ports);
|
set_hw_ports (me, mn103int_ports);
|
set_hw_port_event (me, mn103int_port_event);
|
set_hw_port_event (me, mn103int_port_event);
|
me->to_ioctl = mn103int_ioctl;
|
me->to_ioctl = mn103int_ioctl;
|
|
|
/* Attach ourself to our parent bus */
|
/* Attach ourself to our parent bus */
|
attach_mn103int_regs (me, controller);
|
attach_mn103int_regs (me, controller);
|
|
|
/* Initialize all the groups according to their default configuration */
|
/* Initialize all the groups according to their default configuration */
|
for (gid = 0; gid < NR_GROUPS; gid++)
|
for (gid = 0; gid < NR_GROUPS; gid++)
|
{
|
{
|
struct mn103int_group *group = &controller->group[gid];
|
struct mn103int_group *group = &controller->group[gid];
|
group->trigger = NEGATIVE_EDGE;
|
group->trigger = NEGATIVE_EDGE;
|
group->gid = gid;
|
group->gid = gid;
|
if (FIRST_NMI_GROUP <= gid && gid <= LAST_NMI_GROUP)
|
if (FIRST_NMI_GROUP <= gid && gid <= LAST_NMI_GROUP)
|
{
|
{
|
group->enable = 0xf;
|
group->enable = 0xf;
|
group->type = NMI_GROUP;
|
group->type = NMI_GROUP;
|
}
|
}
|
else if (FIRST_LEVEL_GROUP <= gid && gid <= LAST_LEVEL_GROUP)
|
else if (FIRST_LEVEL_GROUP <= gid && gid <= LAST_LEVEL_GROUP)
|
{
|
{
|
group->enable = 0x0;
|
group->enable = 0x0;
|
group->type = LEVEL_GROUP;
|
group->type = LEVEL_GROUP;
|
}
|
}
|
else
|
else
|
hw_abort (me, "internal error - unknown group id");
|
hw_abort (me, "internal error - unknown group id");
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
/* Perform the nasty work of figuring out which of the interrupt
|
/* Perform the nasty work of figuring out which of the interrupt
|
groups should have its interrupt delivered. */
|
groups should have its interrupt delivered. */
|
|
|
static int
|
static int
|
find_highest_interrupt_group (struct hw *me,
|
find_highest_interrupt_group (struct hw *me,
|
struct mn103int *controller)
|
struct mn103int *controller)
|
{
|
{
|
int gid;
|
int gid;
|
int selected;
|
int selected;
|
|
|
/* FIRST_NMI_GROUP (group zero) is used as a special default value
|
/* FIRST_NMI_GROUP (group zero) is used as a special default value
|
when searching for an interrupt group.*/
|
when searching for an interrupt group.*/
|
selected = FIRST_NMI_GROUP;
|
selected = FIRST_NMI_GROUP;
|
controller->group[FIRST_NMI_GROUP].level = 7;
|
controller->group[FIRST_NMI_GROUP].level = 7;
|
|
|
for (gid = FIRST_LEVEL_GROUP; gid <= LAST_LEVEL_GROUP; gid++)
|
for (gid = FIRST_LEVEL_GROUP; gid <= LAST_LEVEL_GROUP; gid++)
|
{
|
{
|
struct mn103int_group *group = &controller->group[gid];
|
struct mn103int_group *group = &controller->group[gid];
|
if ((group->request & group->enable) != 0)
|
if ((group->request & group->enable) != 0)
|
{
|
{
|
/* Remember, lower level, higher priority. */
|
/* Remember, lower level, higher priority. */
|
if (group->level < controller->group[selected].level)
|
if (group->level < controller->group[selected].level)
|
{
|
{
|
selected = gid;
|
selected = gid;
|
}
|
}
|
}
|
}
|
}
|
}
|
return selected;
|
return selected;
|
}
|
}
|
|
|
|
|
/* Notify the processor of an interrupt level update */
|
/* Notify the processor of an interrupt level update */
|
|
|
static void
|
static void
|
push_interrupt_level (struct hw *me,
|
push_interrupt_level (struct hw *me,
|
struct mn103int *controller)
|
struct mn103int *controller)
|
{
|
{
|
int selected = find_highest_interrupt_group (me, controller);
|
int selected = find_highest_interrupt_group (me, controller);
|
int level = controller->group[selected].level;
|
int level = controller->group[selected].level;
|
HW_TRACE ((me, "port-out - selected=%d level=%d", selected, level));
|
HW_TRACE ((me, "port-out - selected=%d level=%d", selected, level));
|
hw_port_event (me, LEVEL_PORT, level);
|
hw_port_event (me, LEVEL_PORT, level);
|
}
|
}
|
|
|
|
|
/* An event arrives on an interrupt port */
|
/* An event arrives on an interrupt port */
|
|
|
static void
|
static void
|
mn103int_port_event (struct hw *me,
|
mn103int_port_event (struct hw *me,
|
int my_port,
|
int my_port,
|
struct hw *source,
|
struct hw *source,
|
int source_port,
|
int source_port,
|
int level)
|
int level)
|
{
|
{
|
struct mn103int *controller = hw_data (me);
|
struct mn103int *controller = hw_data (me);
|
|
|
switch (my_port)
|
switch (my_port)
|
{
|
{
|
|
|
case ACK_PORT:
|
case ACK_PORT:
|
{
|
{
|
int selected = find_highest_interrupt_group (me, controller);
|
int selected = find_highest_interrupt_group (me, controller);
|
if (controller->group[selected].level != level)
|
if (controller->group[selected].level != level)
|
hw_abort (me, "botched level synchronisation");
|
hw_abort (me, "botched level synchronisation");
|
controller->interrupt_accepted_group = selected;
|
controller->interrupt_accepted_group = selected;
|
HW_TRACE ((me, "port-event port=ack level=%d - selected=%d",
|
HW_TRACE ((me, "port-event port=ack level=%d - selected=%d",
|
level, selected));
|
level, selected));
|
break;
|
break;
|
}
|
}
|
|
|
default:
|
default:
|
{
|
{
|
int gid;
|
int gid;
|
int iid;
|
int iid;
|
struct mn103int_group *group;
|
struct mn103int_group *group;
|
unsigned interrupt;
|
unsigned interrupt;
|
if (my_port > NR_G_PORTS)
|
if (my_port > NR_G_PORTS)
|
hw_abort (me, "Event on unknown port %d", my_port);
|
hw_abort (me, "Event on unknown port %d", my_port);
|
|
|
/* map the port onto an interrupt group */
|
/* map the port onto an interrupt group */
|
gid = (my_port % NR_G_PORTS) / 4;
|
gid = (my_port % NR_G_PORTS) / 4;
|
group = &controller->group[gid];
|
group = &controller->group[gid];
|
iid = (my_port % 4);
|
iid = (my_port % 4);
|
interrupt = 1 << iid;
|
interrupt = 1 << iid;
|
|
|
/* update our cached input */
|
/* update our cached input */
|
if (level)
|
if (level)
|
group->input |= interrupt;
|
group->input |= interrupt;
|
else
|
else
|
group->input &= ~interrupt;
|
group->input &= ~interrupt;
|
|
|
/* update the request bits */
|
/* update the request bits */
|
switch (group->trigger)
|
switch (group->trigger)
|
{
|
{
|
case ACTIVE_LOW:
|
case ACTIVE_LOW:
|
case ACTIVE_HIGH:
|
case ACTIVE_HIGH:
|
if (level)
|
if (level)
|
group->request |= interrupt;
|
group->request |= interrupt;
|
break;
|
break;
|
case NEGATIVE_EDGE:
|
case NEGATIVE_EDGE:
|
case POSITIVE_EDGE:
|
case POSITIVE_EDGE:
|
group->request |= interrupt;
|
group->request |= interrupt;
|
}
|
}
|
|
|
/* force a corresponding output */
|
/* force a corresponding output */
|
switch (group->type)
|
switch (group->type)
|
{
|
{
|
|
|
case NMI_GROUP:
|
case NMI_GROUP:
|
{
|
{
|
/* for NMI's the event is the trigger */
|
/* for NMI's the event is the trigger */
|
HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - NMI",
|
HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - NMI",
|
my_port, gid, iid));
|
my_port, gid, iid));
|
if ((group->request & group->enable) != 0)
|
if ((group->request & group->enable) != 0)
|
{
|
{
|
HW_TRACE ((me, "port-out NMI"));
|
HW_TRACE ((me, "port-out NMI"));
|
hw_port_event (me, NMI_PORT, 1);
|
hw_port_event (me, NMI_PORT, 1);
|
}
|
}
|
break;
|
break;
|
}
|
}
|
|
|
case LEVEL_GROUP:
|
case LEVEL_GROUP:
|
{
|
{
|
/* if an interrupt is now pending */
|
/* if an interrupt is now pending */
|
HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - INT",
|
HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - INT",
|
my_port, gid, iid));
|
my_port, gid, iid));
|
push_interrupt_level (me, controller);
|
push_interrupt_level (me, controller);
|
break;
|
break;
|
}
|
}
|
}
|
}
|
break;
|
break;
|
}
|
}
|
|
|
}
|
}
|
}
|
}
|
|
|
/* Read/write to to an ICR (group control register) */
|
/* Read/write to to an ICR (group control register) */
|
|
|
static struct mn103int_group *
|
static struct mn103int_group *
|
decode_group (struct hw *me,
|
decode_group (struct hw *me,
|
struct mn103int *controller,
|
struct mn103int *controller,
|
unsigned_word base,
|
unsigned_word base,
|
unsigned_word *offset)
|
unsigned_word *offset)
|
{
|
{
|
int gid = (base / 4) % NR_GROUPS;
|
int gid = (base / 4) % NR_GROUPS;
|
*offset = (base % 4);
|
*offset = (base % 4);
|
return &controller->group[gid];
|
return &controller->group[gid];
|
}
|
}
|
|
|
static unsigned8
|
static unsigned8
|
read_icr (struct hw *me,
|
read_icr (struct hw *me,
|
struct mn103int *controller,
|
struct mn103int *controller,
|
unsigned_word base)
|
unsigned_word base)
|
{
|
{
|
unsigned_word offset;
|
unsigned_word offset;
|
struct mn103int_group *group = decode_group (me, controller, base, &offset);
|
struct mn103int_group *group = decode_group (me, controller, base, &offset);
|
unsigned8 val = 0;
|
unsigned8 val = 0;
|
switch (group->type)
|
switch (group->type)
|
{
|
{
|
|
|
case NMI_GROUP:
|
case NMI_GROUP:
|
switch (offset)
|
switch (offset)
|
{
|
{
|
case 0:
|
case 0:
|
val = INSERT_ID (group->request);
|
val = INSERT_ID (group->request);
|
HW_TRACE ((me, "read-icr group=%d:0 nmi 0x%02x",
|
HW_TRACE ((me, "read-icr group=%d:0 nmi 0x%02x",
|
group->gid, val));
|
group->gid, val));
|
break;
|
break;
|
default:
|
default:
|
break;
|
break;
|
}
|
}
|
break;
|
break;
|
|
|
case LEVEL_GROUP:
|
case LEVEL_GROUP:
|
switch (offset)
|
switch (offset)
|
{
|
{
|
case 0:
|
case 0:
|
val = (INSERT_IR (group->request)
|
val = (INSERT_IR (group->request)
|
| INSERT_ID (group->request & group->enable));
|
| INSERT_ID (group->request & group->enable));
|
HW_TRACE ((me, "read-icr group=%d:0 level 0x%02x",
|
HW_TRACE ((me, "read-icr group=%d:0 level 0x%02x",
|
group->gid, val));
|
group->gid, val));
|
break;
|
break;
|
case 1:
|
case 1:
|
val = (INSERT_LV (group->level)
|
val = (INSERT_LV (group->level)
|
| INSERT_IE (group->enable));
|
| INSERT_IE (group->enable));
|
HW_TRACE ((me, "read-icr level-%d:1 level 0x%02x",
|
HW_TRACE ((me, "read-icr level-%d:1 level 0x%02x",
|
group->gid, val));
|
group->gid, val));
|
break;
|
break;
|
}
|
}
|
break;
|
break;
|
|
|
default:
|
default:
|
break;
|
break;
|
|
|
}
|
}
|
|
|
return val;
|
return val;
|
}
|
}
|
|
|
static void
|
static void
|
write_icr (struct hw *me,
|
write_icr (struct hw *me,
|
struct mn103int *controller,
|
struct mn103int *controller,
|
unsigned_word base,
|
unsigned_word base,
|
unsigned8 val)
|
unsigned8 val)
|
{
|
{
|
unsigned_word offset;
|
unsigned_word offset;
|
struct mn103int_group *group = decode_group (me, controller, base, &offset);
|
struct mn103int_group *group = decode_group (me, controller, base, &offset);
|
switch (group->type)
|
switch (group->type)
|
{
|
{
|
|
|
case NMI_GROUP:
|
case NMI_GROUP:
|
switch (offset)
|
switch (offset)
|
{
|
{
|
case 0:
|
case 0:
|
HW_TRACE ((me, "write-icr group=%d:0 nmi 0x%02x",
|
HW_TRACE ((me, "write-icr group=%d:0 nmi 0x%02x",
|
group->gid, val));
|
group->gid, val));
|
group->request &= ~EXTRACT_ID (val);
|
group->request &= ~EXTRACT_ID (val);
|
break;
|
break;
|
/* Special backdoor access to SYSEF flag from CPU. See
|
/* Special backdoor access to SYSEF flag from CPU. See
|
interp.c:program_interrupt(). */
|
interp.c:program_interrupt(). */
|
case 3:
|
case 3:
|
HW_TRACE ((me, "write-icr-special group=%d:0 nmi 0x%02x",
|
HW_TRACE ((me, "write-icr-special group=%d:0 nmi 0x%02x",
|
group->gid, val));
|
group->gid, val));
|
group->request |= EXTRACT_ID (val);
|
group->request |= EXTRACT_ID (val);
|
default:
|
default:
|
break;
|
break;
|
}
|
}
|
break;
|
break;
|
|
|
case LEVEL_GROUP:
|
case LEVEL_GROUP:
|
switch (offset)
|
switch (offset)
|
{
|
{
|
case 0: /* request/detect */
|
case 0: /* request/detect */
|
/* Clear any ID bits and then set them according to IR */
|
/* Clear any ID bits and then set them according to IR */
|
HW_TRACE ((me, "write-icr group=%d:0 level 0x%02x %x:%x:%x",
|
HW_TRACE ((me, "write-icr group=%d:0 level 0x%02x %x:%x:%x",
|
group->gid, val,
|
group->gid, val,
|
group->request, EXTRACT_IR (val), EXTRACT_ID (val)));
|
group->request, EXTRACT_IR (val), EXTRACT_ID (val)));
|
group->request =
|
group->request =
|
((EXTRACT_IR (val) & EXTRACT_ID (val))
|
((EXTRACT_IR (val) & EXTRACT_ID (val))
|
| (EXTRACT_IR (val) & group->request)
|
| (EXTRACT_IR (val) & group->request)
|
| (~EXTRACT_IR (val) & ~EXTRACT_ID (val) & group->request));
|
| (~EXTRACT_IR (val) & ~EXTRACT_ID (val) & group->request));
|
break;
|
break;
|
case 1: /* level/enable */
|
case 1: /* level/enable */
|
HW_TRACE ((me, "write-icr group=%d:1 level 0x%02x",
|
HW_TRACE ((me, "write-icr group=%d:1 level 0x%02x",
|
group->gid, val));
|
group->gid, val));
|
group->level = EXTRACT_LV (val);
|
group->level = EXTRACT_LV (val);
|
group->enable = EXTRACT_IE (val);
|
group->enable = EXTRACT_IE (val);
|
break;
|
break;
|
default:
|
default:
|
/* ignore */
|
/* ignore */
|
break;
|
break;
|
}
|
}
|
push_interrupt_level (me, controller);
|
push_interrupt_level (me, controller);
|
break;
|
break;
|
|
|
default:
|
default:
|
break;
|
break;
|
|
|
}
|
}
|
}
|
}
|
|
|
|
|
/* Read the IAGR (Interrupt accepted group register) */
|
/* Read the IAGR (Interrupt accepted group register) */
|
|
|
static unsigned8
|
static unsigned8
|
read_iagr (struct hw *me,
|
read_iagr (struct hw *me,
|
struct mn103int *controller,
|
struct mn103int *controller,
|
unsigned_word offset)
|
unsigned_word offset)
|
{
|
{
|
unsigned8 val;
|
unsigned8 val;
|
switch (offset)
|
switch (offset)
|
{
|
{
|
case 0:
|
case 0:
|
{
|
{
|
if (!(controller->group[controller->interrupt_accepted_group].request
|
if (!(controller->group[controller->interrupt_accepted_group].request
|
& controller->group[controller->interrupt_accepted_group].enable))
|
& controller->group[controller->interrupt_accepted_group].enable))
|
{
|
{
|
/* oops, lost the request */
|
/* oops, lost the request */
|
val = 0;
|
val = 0;
|
HW_TRACE ((me, "read-iagr:0 lost-0"));
|
HW_TRACE ((me, "read-iagr:0 lost-0"));
|
}
|
}
|
else
|
else
|
{
|
{
|
val = (controller->interrupt_accepted_group << 2);
|
val = (controller->interrupt_accepted_group << 2);
|
HW_TRACE ((me, "read-iagr:0 %d", (int) val));
|
HW_TRACE ((me, "read-iagr:0 %d", (int) val));
|
}
|
}
|
break;
|
break;
|
}
|
}
|
case 1:
|
case 1:
|
val = 0;
|
val = 0;
|
HW_TRACE ((me, "read-iagr:1 %d", (int) val));
|
HW_TRACE ((me, "read-iagr:1 %d", (int) val));
|
break;
|
break;
|
default:
|
default:
|
val = 0;
|
val = 0;
|
HW_TRACE ((me, "read-iagr 0x%08lx bad offset", (long) offset));
|
HW_TRACE ((me, "read-iagr 0x%08lx bad offset", (long) offset));
|
break;
|
break;
|
}
|
}
|
return val;
|
return val;
|
}
|
}
|
|
|
|
|
/* Reads/writes to the EXTMD (external interrupt trigger configuration
|
/* Reads/writes to the EXTMD (external interrupt trigger configuration
|
register) */
|
register) */
|
|
|
static struct mn103int_group *
|
static struct mn103int_group *
|
external_group (struct mn103int *controller,
|
external_group (struct mn103int *controller,
|
unsigned_word offset)
|
unsigned_word offset)
|
{
|
{
|
switch (offset)
|
switch (offset)
|
{
|
{
|
case 0:
|
case 0:
|
return &controller->group[IRQ0_PORT/4];
|
return &controller->group[IRQ0_PORT/4];
|
case 1:
|
case 1:
|
return &controller->group[IRQ4_PORT/4];
|
return &controller->group[IRQ4_PORT/4];
|
default:
|
default:
|
return NULL;
|
return NULL;
|
}
|
}
|
}
|
}
|
|
|
static unsigned8
|
static unsigned8
|
read_extmd (struct hw *me,
|
read_extmd (struct hw *me,
|
struct mn103int *controller,
|
struct mn103int *controller,
|
unsigned_word offset)
|
unsigned_word offset)
|
{
|
{
|
int gid;
|
int gid;
|
unsigned8 val = 0;
|
unsigned8 val = 0;
|
struct mn103int_group *group = external_group (controller, offset);
|
struct mn103int_group *group = external_group (controller, offset);
|
if (group != NULL)
|
if (group != NULL)
|
{
|
{
|
for (gid = 0; gid < 4; gid++)
|
for (gid = 0; gid < 4; gid++)
|
{
|
{
|
val |= (group[gid].trigger << (gid * 2));
|
val |= (group[gid].trigger << (gid * 2));
|
}
|
}
|
}
|
}
|
HW_TRACE ((me, "read-extmd 0x%02lx", (long) val));
|
HW_TRACE ((me, "read-extmd 0x%02lx", (long) val));
|
return val;
|
return val;
|
}
|
}
|
|
|
static void
|
static void
|
write_extmd (struct hw *me,
|
write_extmd (struct hw *me,
|
struct mn103int *controller,
|
struct mn103int *controller,
|
unsigned_word offset,
|
unsigned_word offset,
|
unsigned8 val)
|
unsigned8 val)
|
{
|
{
|
int gid;
|
int gid;
|
struct mn103int_group *group = external_group (controller, offset);
|
struct mn103int_group *group = external_group (controller, offset);
|
if (group != NULL)
|
if (group != NULL)
|
{
|
{
|
for (gid = 0; gid < 4; gid++)
|
for (gid = 0; gid < 4; gid++)
|
{
|
{
|
group[gid].trigger = (val >> (gid * 2)) & 0x3;
|
group[gid].trigger = (val >> (gid * 2)) & 0x3;
|
/* MAYBE: interrupts already pending? */
|
/* MAYBE: interrupts already pending? */
|
}
|
}
|
}
|
}
|
HW_TRACE ((me, "write-extmd 0x%02lx", (long) val));
|
HW_TRACE ((me, "write-extmd 0x%02lx", (long) val));
|
}
|
}
|
|
|
|
|
/* generic read/write */
|
/* generic read/write */
|
|
|
static int
|
static int
|
decode_addr (struct hw *me,
|
decode_addr (struct hw *me,
|
struct mn103int *controller,
|
struct mn103int *controller,
|
unsigned_word address,
|
unsigned_word address,
|
unsigned_word *offset)
|
unsigned_word *offset)
|
{
|
{
|
int i;
|
int i;
|
for (i = 0; i < NR_BLOCKS; i++)
|
for (i = 0; i < NR_BLOCKS; i++)
|
{
|
{
|
if (address >= controller->block[i].base
|
if (address >= controller->block[i].base
|
&& address <= controller->block[i].bound)
|
&& address <= controller->block[i].bound)
|
{
|
{
|
*offset = address - controller->block[i].base;
|
*offset = address - controller->block[i].base;
|
return i;
|
return i;
|
}
|
}
|
}
|
}
|
hw_abort (me, "bad address");
|
hw_abort (me, "bad address");
|
return -1;
|
return -1;
|
}
|
}
|
|
|
static unsigned
|
static unsigned
|
mn103int_io_read_buffer (struct hw *me,
|
mn103int_io_read_buffer (struct hw *me,
|
void *dest,
|
void *dest,
|
int space,
|
int space,
|
unsigned_word base,
|
unsigned_word base,
|
unsigned nr_bytes)
|
unsigned nr_bytes)
|
{
|
{
|
struct mn103int *controller = hw_data (me);
|
struct mn103int *controller = hw_data (me);
|
unsigned8 *buf = dest;
|
unsigned8 *buf = dest;
|
unsigned byte;
|
unsigned byte;
|
/* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */
|
/* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */
|
for (byte = 0; byte < nr_bytes; byte++)
|
for (byte = 0; byte < nr_bytes; byte++)
|
{
|
{
|
unsigned_word address = base + byte;
|
unsigned_word address = base + byte;
|
unsigned_word offset;
|
unsigned_word offset;
|
switch (decode_addr (me, controller, address, &offset))
|
switch (decode_addr (me, controller, address, &offset))
|
{
|
{
|
case ICR_BLOCK:
|
case ICR_BLOCK:
|
buf[byte] = read_icr (me, controller, offset);
|
buf[byte] = read_icr (me, controller, offset);
|
break;
|
break;
|
case IAGR_BLOCK:
|
case IAGR_BLOCK:
|
buf[byte] = read_iagr (me, controller, offset);
|
buf[byte] = read_iagr (me, controller, offset);
|
break;
|
break;
|
case EXTMD_BLOCK:
|
case EXTMD_BLOCK:
|
buf[byte] = read_extmd (me, controller, offset);
|
buf[byte] = read_extmd (me, controller, offset);
|
break;
|
break;
|
default:
|
default:
|
hw_abort (me, "bad switch");
|
hw_abort (me, "bad switch");
|
}
|
}
|
}
|
}
|
return nr_bytes;
|
return nr_bytes;
|
}
|
}
|
|
|
static unsigned
|
static unsigned
|
mn103int_io_write_buffer (struct hw *me,
|
mn103int_io_write_buffer (struct hw *me,
|
const void *source,
|
const void *source,
|
int space,
|
int space,
|
unsigned_word base,
|
unsigned_word base,
|
unsigned nr_bytes)
|
unsigned nr_bytes)
|
{
|
{
|
struct mn103int *controller = hw_data (me);
|
struct mn103int *controller = hw_data (me);
|
const unsigned8 *buf = source;
|
const unsigned8 *buf = source;
|
unsigned byte;
|
unsigned byte;
|
/* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */
|
/* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */
|
for (byte = 0; byte < nr_bytes; byte++)
|
for (byte = 0; byte < nr_bytes; byte++)
|
{
|
{
|
unsigned_word address = base + byte;
|
unsigned_word address = base + byte;
|
unsigned_word offset;
|
unsigned_word offset;
|
switch (decode_addr (me, controller, address, &offset))
|
switch (decode_addr (me, controller, address, &offset))
|
{
|
{
|
case ICR_BLOCK:
|
case ICR_BLOCK:
|
write_icr (me, controller, offset, buf[byte]);
|
write_icr (me, controller, offset, buf[byte]);
|
break;
|
break;
|
case IAGR_BLOCK:
|
case IAGR_BLOCK:
|
/* not allowed */
|
/* not allowed */
|
break;
|
break;
|
case EXTMD_BLOCK:
|
case EXTMD_BLOCK:
|
write_extmd (me, controller, offset, buf[byte]);
|
write_extmd (me, controller, offset, buf[byte]);
|
break;
|
break;
|
default:
|
default:
|
hw_abort (me, "bad switch");
|
hw_abort (me, "bad switch");
|
}
|
}
|
}
|
}
|
return nr_bytes;
|
return nr_bytes;
|
}
|
}
|
|
|
static int
|
static int
|
mn103int_ioctl(struct hw *me,
|
mn103int_ioctl(struct hw *me,
|
hw_ioctl_request request,
|
hw_ioctl_request request,
|
va_list ap)
|
va_list ap)
|
{
|
{
|
struct mn103int *controller = (struct mn103int *)hw_data(me);
|
struct mn103int *controller = (struct mn103int *)hw_data(me);
|
controller->group[0].request = EXTRACT_ID(4);
|
controller->group[0].request = EXTRACT_ID(4);
|
mn103int_port_event(me, 2 /* nmi_port(syserr) */, NULL, 0, 0);
|
mn103int_port_event(me, 2 /* nmi_port(syserr) */, NULL, 0, 0);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
|
|
const struct hw_descriptor dv_mn103int_descriptor[] = {
|
const struct hw_descriptor dv_mn103int_descriptor[] = {
|
{ "mn103int", mn103int_finish, },
|
{ "mn103int", mn103int_finish, },
|
{ NULL },
|
{ NULL },
|
};
|
};
|
|
|
