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PSIM - model the PowerPC environment
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PSIM - model the PowerPC environment
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Copyright (C) 1994-1996, Andrew Cagney .
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Copyright (C) 1994-1996, Andrew Cagney .
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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Building PSIM
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Building PSIM
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This file describes how to build the program PSIM
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This file describes how to build the program PSIM
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o Walk through a basic build
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o Walk through a basic build
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o Discussion of PSIM's components and
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o Discussion of PSIM's components and
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how they relate to the build process
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how they relate to the build process
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o Detailed description of each of PSIM's
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o Detailed description of each of PSIM's
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compile time configuration options
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compile time configuration options
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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BUILDING PSIM:
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BUILDING PSIM:
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PSIM 1.0.2 is included in GDB-4.16. To build PSIM you will need the
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PSIM 1.0.2 is included in GDB-4.16. To build PSIM you will need the
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following:
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following:
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gdb-4.16.tar.gz Available from your favorite GNU
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gdb-4.16.tar.gz Available from your favorite GNU
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ftp site
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ftp site
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gcc GCC version two includes suport
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gcc GCC version two includes suport
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for long long (64bit integer)
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for long long (64bit integer)
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arrithemetic which PSIM uses. Hence
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arrithemetic which PSIM uses. Hence
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it is recommended that you build PSIM
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it is recommended that you build PSIM
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using GCC.
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using GCC.
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Method:
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Method:
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1. Unpack gdb
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1. Unpack gdb
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$ cd .../scratch
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$ cd .../scratch
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$ gunzip < gdb-4.16.tar.gz | tar xf -
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$ gunzip < gdb-4.16.tar.gz | tar xf -
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2. Configure gdb
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2. Configure gdb
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First consult the gdb documentation
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First consult the gdb documentation
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$ cd .../scratch
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$ cd .../scratch
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$ cd gdb-4.16
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$ cd gdb-4.16
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$ more README
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$ more README
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$ more gdb/README
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$ more gdb/README
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then something like (I assume SH):
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then something like (I assume SH):
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$ CC=gcc ./configure \
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$ CC=gcc ./configure \
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--enable-sim-powerpc \
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--enable-sim-powerpc \
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--target=powerpc-unknown-eabi \
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--target=powerpc-unknown-eabi \
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--prefix=/applications/psim
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--prefix=/applications/psim
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4. Build (again specifying GCC)
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4. Build (again specifying GCC)
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$ make CC=gcc
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$ make CC=gcc
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alternatively, if you are short on disk space or only
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alternatively, if you are short on disk space or only
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want to build the simulator:
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want to build the simulator:
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$ ( cd libiberty && make CC=gcc )
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$ ( cd libiberty && make CC=gcc )
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$ ( cd bfd && make CC=gcc )
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$ ( cd bfd && make CC=gcc )
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$ ( cd sim/ppc && make CC=gcc )
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$ ( cd sim/ppc && make CC=gcc )
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5. Install
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5. Install
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$ make CC=gcc install
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$ make CC=gcc install
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or just
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or just
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$ cp gdb/gdb ~/bin/powerpc-unknown-eabisim-gdb
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$ cp gdb/gdb ~/bin/powerpc-unknown-eabisim-gdb
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$ cp sim/ppc/run ~/bin/powerpc-unknown-eabisim-run
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$ cp sim/ppc/run ~/bin/powerpc-unknown-eabisim-run
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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UPDATING PSIM:
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UPDATING PSIM:
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A PSIM is an ongoing development. Occasional snapshots which both contain new
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A PSIM is an ongoing development. Occasional snapshots which both contain new
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features and fix old bugs are made available. See the ftp directory:
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features and fix old bugs are made available. See the ftp directory:
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ftp://ftp.ci.com.au/pub/psim/beta
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ftp://ftp.ci.com.au/pub/psim/beta
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or ftp://cambridge.cygnus.com/pub/psim/beta
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or ftp://cambridge.cygnus.com/pub/psim/beta
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for the latest version. To build/install one of these snapshots, you
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for the latest version. To build/install one of these snapshots, you
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replace the sim/ppc found in the gdb archive with with one from the
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replace the sim/ppc found in the gdb archive with with one from the
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snapshot. Then just re-configure and rebuild/install.
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snapshot. Then just re-configure and rebuild/install.
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Procedure:
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Procedure:
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0. A starting point
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0. A starting point
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$ cd gdb-4.16
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$ cd gdb-4.16
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1. Remove the old psim directory
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1. Remove the old psim directory
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$ mv sim/ppc sim/old.ppc
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$ mv sim/ppc sim/old.ppc
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2. Unpack the new one
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2. Unpack the new one
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$ gunzip < ../psim-NNNNNN.tar.gz | tar tf -
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$ gunzip < ../psim-NNNNNN.tar.gz | tar tf -
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$ gunzip < ../psim-NNNNNN.tar.gz | tar tf -
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$ gunzip < ../psim-NNNNNN.tar.gz | tar tf -
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3. Reconfigure/rebuild (as seen above):
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3. Reconfigure/rebuild (as seen above):
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$ CC=gcc ./configure \
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$ CC=gcc ./configure \
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--enable-sim-powerpc \
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--enable-sim-powerpc \
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--target=powerpc-unknown-eabi \
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--target=powerpc-unknown-eabi \
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--prefix=/applications/psim
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--prefix=/applications/psim
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$ make CC=gcc
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$ make CC=gcc
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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UPDATES TO GDB:
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UPDATES TO GDB:
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From time to time, problems involving the integration of PSIM into gdb
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From time to time, problems involving the integration of PSIM into gdb
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are found. While eventually each of these problems is resolved there
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are found. While eventually each of these problems is resolved there
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can be periouds during which a local hack may be needed.
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can be periouds during which a local hack may be needed.
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At the time of writing the following were outstanding:
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At the time of writing the following were outstanding:
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ATTACH command:
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ATTACH command:
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ftp://ftp.ci.com.au/pub/psim/gdb-4.15+attach.diff.gz
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ftp://ftp.ci.com.au/pub/psim/gdb-4.15+attach.diff.gz
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or ftp://cambridge.cygnus.com/pub/psim/gdb-4.15+attach.diff.gz
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or ftp://cambridge.cygnus.com/pub/psim/gdb-4.15+attach.diff.gz
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PSIM, unlike the other simulators found in GDB, is able to load
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PSIM, unlike the other simulators found in GDB, is able to load
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the description of a target machine (including the initial
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the description of a target machine (including the initial
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state of all processor registers) from a file.
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state of all processor registers) from a file.
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Unfortunatly GDB does not yet have a standard command that
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Unfortunatly GDB does not yet have a standard command that
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facilitates the use of this feature. Until such a command is
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facilitates the use of this feature. Until such a command is
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added, the patch (hack?) gdb-4.15+attach.diff.gz can be used to
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added, the patch (hack?) gdb-4.15+attach.diff.gz can be used to
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extend GDB's attach command so that it can be used to initialize
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extend GDB's attach command so that it can be used to initialize
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the simulators configuration from a file.
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the simulators configuration from a file.
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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RUNNING PROGRAMS:
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RUNNING PROGRAMS:
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See the file:
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See the file:
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ftp://ftp.ci.com.au/pub/psim/RUN
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ftp://ftp.ci.com.au/pub/psim/RUN
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or ftp://cambridge.cygnus.com/pub/psim/RUN
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or ftp://cambridge.cygnus.com/pub/psim/RUN
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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COMPILE TIME CONFIGURATION OPTIONS:
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COMPILE TIME CONFIGURATION OPTIONS:
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PSIM's compile time configuration is controlled by autoconf. PSIM's
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PSIM's compile time configuration is controlled by autoconf. PSIM's
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configure script recognises options of the form:
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configure script recognises options of the form:
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--enable-sim-
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--enable-sim-
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And can be specified on the configure command line (at the top level
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And can be specified on the configure command line (at the top level
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of the gdb directory tree) vis:
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of the gdb directory tree) vis:
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$ cd gdb-4.15
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$ cd gdb-4.15
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$ CC=gcc ./configure \
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$ CC=gcc ./configure \
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--target=powerpc-unknown-eabisim \
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--target=powerpc-unknown-eabisim \
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--prefix=/applications/psim \
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--prefix=/applications/psim \
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--enable-sim-inline
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--enable-sim-inline
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$ make CC=gcc
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$ make CC=gcc
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For a brief list of PSIM's configuration options, configure --help
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For a brief list of PSIM's configuration options, configure --help
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will list them vis:
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will list them vis:
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$ cd sim/ppc
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$ cd sim/ppc
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$ ./configure --help
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$ ./configure --help
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Each PSIM specific option is discussed in detail below.
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Each PSIM specific option is discussed in detail below.
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--enable-sim-cflags=
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--enable-sim-cflags=
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Specify additional C compiler flags that are to be used when compiling
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Specify additional C compiler flags that are to be used when compiling
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just PSIM.
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just PSIM.
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PSIM places heavy demands on both the host machine and its C compiler. So that
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PSIM places heavy demands on both the host machine and its C compiler. So that
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the builder has better control over the compiler the above option can be used
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the builder has better control over the compiler the above option can be used
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to pass additional options to the compiler while PSIM is being built.
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to pass additional options to the compiler while PSIM is being built.
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Ex: No debug information
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Ex: No debug information
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PSIM can be built with everything inline. Unfortunately, because of
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PSIM can be built with everything inline. Unfortunately, because of
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all the debugging information generated the C compiler can grow very
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all the debugging information generated the C compiler can grow very
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very large as a result. For GCC, the debug information can be
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very large as a result. For GCC, the debug information can be
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restricted with the `-g0' option. To specify that this option should
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restricted with the `-g0' option. To specify that this option should
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be include in the CFLAGS when compiling the psim source code use:
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be include in the CFLAGS when compiling the psim source code use:
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--enable-sim-cflags=-g0
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--enable-sim-cflags=-g0
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Ex: Additional optimization flags
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Ex: Additional optimization flags
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A significant gain in performance can be achieved by tuning the
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A significant gain in performance can be achieved by tuning the
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optimization flags passed to the C compiler. For instance on an x86
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optimization flags passed to the C compiler. For instance on an x86
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you may consider:
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you may consider:
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--enable-sim-cflags='-g0 -O2 -fno-strength-reduce -f...'
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--enable-sim-cflags='-g0 -O2 -fno-strength-reduce -f...'
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--enable-sim-warnings=
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--enable-sim-warnings=
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Turn on additional GCC specific checks.
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Turn on additional GCC specific checks.
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Some hosts (NetBSD, Linux, Solaris-2.5) have complete header files
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Some hosts (NetBSD, Linux, Solaris-2.5) have complete header files
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that include correct prototypes for all library functions. On such
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that include correct prototypes for all library functions. On such
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hosts, PSIM can be built with many more than the standard C checks
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hosts, PSIM can be built with many more than the standard C checks
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enabled. The option --enable-sim-warnings controls this.
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enabled. The option --enable-sim-warnings controls this.
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Ex: Default warnings
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Ex: Default warnings
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With just --enable-sim-warnings, the following -W options are enabled:
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With just --enable-sim-warnings, the following -W options are enabled:
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-Werror -Wall -Wpointer-arith -Wmissing-prototypes.
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-Werror -Wall -Wpointer-arith -Wmissing-prototypes.
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--enable-sim-opcode=which
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--enable-sim-opcode=which
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Specify the file containing the rules for generating the instruction
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Specify the file containing the rules for generating the instruction
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decode and execute functions from the file ppc-instructions.
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decode and execute functions from the file ppc-instructions.
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The form of the instruction decode and execute functions is controlled
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The form of the instruction decode and execute functions is controlled
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by an opcode table. It specifies: the combination of switch
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by an opcode table. It specifies: the combination of switch
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statements and jump tables to use when decoding an instruction and how
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statements and jump tables to use when decoding an instruction and how
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much of each instruction should be decoded before calling the
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much of each instruction should be decoded before calling the
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instruction execute function.
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instruction execute function.
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PSIM includes a number of opcode tables:
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PSIM includes a number of opcode tables:
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psim-opcode-simple
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psim-opcode-simple
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Generates a small compact two level switch statement
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Generates a small compact two level switch statement
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that will compile quickly and run reasonably fast.
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that will compile quickly and run reasonably fast.
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This may be useful on a small machine.
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This may be useful on a small machine.
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psim-opcode-complex
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psim-opcode-complex
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(the default) A fairly aggressive instruction decode
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(the default) A fairly aggressive instruction decode
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table that includes the breaking out of a number
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table that includes the breaking out of a number
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of special instruction cases (eg RA==0 vs RA!=0).
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of special instruction cases (eg RA==0 vs RA!=0).
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psim-opcode-flat
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psim-opcode-flat
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Identical to complex except a switch statement
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Identical to complex except a switch statement
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is used. Ideal for when the icache is being
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is used. Ideal for when the icache is being
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disabled.
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disabled.
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psim-opcode-stupid
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psim-opcode-stupid
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In addition to the instruction decodes performed
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In addition to the instruction decodes performed
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by psim-opcode-complex, this also full decodes mtspr,
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by psim-opcode-complex, this also full decodes mtspr,
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mfspr, and branch instructions. The table generated
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mfspr, and branch instructions. The table generated
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is very large and, as a consequence, only performs
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is very large and, as a consequence, only performs
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well on machines with large caches.
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well on machines with large caches.
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ppc-opcode-test-1
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ppc-opcode-test-1
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ppc-opcode-test-2
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ppc-opcode-test-2
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Generate test (but workable) tables. These exercise
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Generate test (but workable) tables. These exercise
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PSIM's ability to generate instruction decode functions
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PSIM's ability to generate instruction decode functions
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that are a combination of jump-tables and switch statements.
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that are a combination of jump-tables and switch statements.
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The program igen generates the instruction tables from the opcode
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The program igen generates the instruction tables from the opcode
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table and the ppc-instruction table.
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table and the ppc-instruction table.
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--enable-sim-switch
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--enable-sim-switch
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Enable/disable the use of a switch statement when looking up the
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Enable/disable the use of a switch statement when looking up the
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attributes of a SPR register.
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attributes of a SPR register.
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The PowerPC architecture defines a number of Special Purpose Registers
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The PowerPC architecture defines a number of Special Purpose Registers
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(SPR's). Associated with each of these registers are a number of
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(SPR's). Associated with each of these registers are a number of
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attributes (such as validity or size) which the instructions
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attributes (such as validity or size) which the instructions
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mtspr/mfspr query as part of their execution.
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mtspr/mfspr query as part of their execution.
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For PSIM, this information is kept in a table (ppc-spr-table). The
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For PSIM, this information is kept in a table (ppc-spr-table). The
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program dgen converts this table into lookup routines (contained in
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program dgen converts this table into lookup routines (contained in
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the generated files spreg.h spreg.c) that can be used to query an
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the generated files spreg.h spreg.c) that can be used to query an
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SPR's attributes. Those lookup routines are either implemented as
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SPR's attributes. Those lookup routines are either implemented as
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a table or alternatively as a number of switch statements:
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a table or alternatively as a number of switch statements:
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spr_table spr_info[] = { .... };
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spr_table spr_info[] = { .... };
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int spr_length(sprs spr) { return spr_info[spr].length; }
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int spr_length(sprs spr) { return spr_info[spr].length; }
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vs
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vs
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int spr_length(sprs spr) { switch (spr) { case ..: return ..; } }
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int spr_length(sprs spr) { switch (spr) { case ..: return ..; } }
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In general the first implementation (a table) is the most efficient.
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In general the first implementation (a table) is the most efficient.
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It may, however, prove that when performing an aggressive optimization
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It may, however, prove that when performing an aggressive optimization
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where both the SPR is known and the above function is being inlined
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where both the SPR is known and the above function is being inlined
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(with the consequence that GCC can eliminate the switch statement)
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(with the consequence that GCC can eliminate the switch statement)
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that the second choice is improves performance.
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that the second choice is improves performance.
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In practice, only a marginal (if any benefit) has ever been seen.
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In practice, only a marginal (if any benefit) has ever been seen.
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--enable-sim-duplicate
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--enable-sim-duplicate
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Create a duplicate copy of each instruction function hardwiring
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Create a duplicate copy of each instruction function hardwiring
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instruction fields that would have otherwise have been variable.
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instruction fields that would have otherwise have been variable.
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As discussed above, igen outputs a C function generated from the file
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As discussed above, igen outputs a C function generated from the file
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ppc-instructions (using the opcode rules) for each of the
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ppc-instructions (using the opcode rules) for each of the
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instructions. Thus multiple entries in the instruction decode tables
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instructions. Thus multiple entries in the instruction decode tables
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may be pointing back at the same function. Enabling duplicate, will
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may be pointing back at the same function. Enabling duplicate, will
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result in psim creating a duplicate of the instruction's function for
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result in psim creating a duplicate of the instruction's function for
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each different entry in the instruction decode tables.
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each different entry in the instruction decode tables.
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For instance, given the branch instruction:
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For instance, given the branch instruction:
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0.19,6.BO,11.BI,16./,21.528,31.LK
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0.19,6.BO,11.BI,16./,21.528,31.LK
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...
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...
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if (LK) LR = (spreg)IEA(CIA + 4);
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if (LK) LR = (spreg)IEA(CIA + 4);
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...
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...
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igen as part of its instruction lookup table may have generated two
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igen as part of its instruction lookup table may have generated two
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different entries - one for LK=0 and one for LK=1. With duplicate
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different entries - one for LK=0 and one for LK=1. With duplicate
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enabled, igen outputs (almost) duplicate copies of branch function,
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enabled, igen outputs (almost) duplicate copies of branch function,
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one with LK hardwired to 0 and one with LK hardwired to 1.
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one with LK hardwired to 0 and one with LK hardwired to 1.
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By doing this the compiler is provided with additional information that
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By doing this the compiler is provided with additional information that
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will allow it possibly eliminate dead code. (such as the assignment
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will allow it possibly eliminate dead code. (such as the assignment
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to LK if LR==0).
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to LK if LR==0).
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Ex: default
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Ex: default
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Because this feature is such a big win, --enable-sim-duplicate is
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Because this feature is such a big win, --enable-sim-duplicate is
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turned on by default.
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turned on by default.
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Ex: A small machine
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Ex: A small machine
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Only rarely (eg on a very small host) would this feature need to be
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Only rarely (eg on a very small host) would this feature need to be
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disabled (using: --disable-sim-duplicate).
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disabled (using: --disable-sim-duplicate).
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--enable-sim-filter=rule
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--enable-sim-filter=rule
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Include/exclude PowerPC instructions that are specific to a particular
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Include/exclude PowerPC instructions that are specific to a particular
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implementation.
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implementation.
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Some of the PowerPC instructions included in the file ppc-instructions
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Some of the PowerPC instructions included in the file ppc-instructions
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are limited to certain specific PPC implementations. For instance,
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are limited to certain specific PPC implementations. For instance,
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the instruction:
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the instruction:
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0.58,6.RT,11.RA,16.DS,30.2:DS:64::Load Word Algebraic
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0.58,6.RT,11.RA,16.DS,30.2:DS:64::Load Word Algebraic
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Is only valid for the 64bit architecture. The enable-sim-filter flag
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Is only valid for the 64bit architecture. The enable-sim-filter flag
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is passed to igen so that it can `filter out' any invalid
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is passed to igen so that it can `filter out' any invalid
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instructions. The filter rule has the form:
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instructions. The filter rule has the form:
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-f
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-f
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thus:
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thus:
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--enable-sim-filter='-f 64'
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--enable-sim-filter='-f 64'
|
|
|
(the default) would filter out all 64bit instructions.
|
(the default) would filter out all 64bit instructions.
|
|
|
Ex: Remove floating point instructions
|
Ex: Remove floating point instructions
|
|
|
A given 32bit PowerPC implementation may not include floating point
|
A given 32bit PowerPC implementation may not include floating point
|
hardware. Consequently there is little point in including floating
|
hardware. Consequently there is little point in including floating
|
point instructions in the instruction table. The option:
|
point instructions in the instruction table. The option:
|
|
|
--enable-sim-filter='-f 64 -f f'
|
--enable-sim-filter='-f 64 -f f'
|
|
|
will eliminate all floating point instructions from the instruction
|
will eliminate all floating point instructions from the instruction
|
table.
|
table.
|
|
|
|
|
|
|
--enable-sim-icache=size
|
--enable-sim-icache=size
|
|
|
|
|
Set the size of the cache used to hold decoded instructions.
|
Set the size of the cache used to hold decoded instructions.
|
|
|
Psim executes instructions in two separate steps:
|
Psim executes instructions in two separate steps:
|
|
|
o instruction fetch/decode
|
o instruction fetch/decode
|
|
|
o instruction execution
|
o instruction execution
|
|
|
For a given instruction, the first stage need only be executed once
|
For a given instruction, the first stage need only be executed once
|
(the first time the instruction is encountered) while the second stage
|
(the first time the instruction is encountered) while the second stage
|
must be executed every time the program `executes' that instruction.
|
must be executed every time the program `executes' that instruction.
|
|
|
Exploiting this, PSIM can maintain a cache of decoded instructions.
|
Exploiting this, PSIM can maintain a cache of decoded instructions.
|
It will then use the decoded instruction from the cache in preference
|
It will then use the decoded instruction from the cache in preference
|
to fetching/decoding the real instruction from memory.
|
to fetching/decoding the real instruction from memory.
|
|
|
Ex: default
|
Ex: default
|
|
|
Because this feature is normally such a big win, it is enabled by
|
Because this feature is normally such a big win, it is enabled by
|
default (with the cache size set to 1024 entries).
|
default (with the cache size set to 1024 entries).
|
|
|
The 1024 entries equals 4096 bytes (or one page) of instructions.
|
The 1024 entries equals 4096 bytes (or one page) of instructions.
|
Larger caches can be used but with caution - PSIM does not check for
|
Larger caches can be used but with caution - PSIM does not check for
|
address aliasing within its instruction cache.
|
address aliasing within its instruction cache.
|
|
|
Ex: disable the cache
|
Ex: disable the cache
|
|
|
There may be cases (for instance where the cache has a low hit rate)
|
There may be cases (for instance where the cache has a low hit rate)
|
where the psim performs better with no instruction cache. For such
|
where the psim performs better with no instruction cache. For such
|
situations, the cache can be disabled vis: --disable-sim-icache.
|
situations, the cache can be disabled vis: --disable-sim-icache.
|
|
|
|
|
|
|
--enable-sim-inline[=module]
|
--enable-sim-inline[=module]
|
|
|
|
|
Specify the inlining of one or more modules.
|
Specify the inlining of one or more modules.
|
|
|
Many architectures (in particular the x86) suffer from a large
|
Many architectures (in particular the x86) suffer from a large
|
function call overhead. By eliminating function calls (through
|
function call overhead. By eliminating function calls (through
|
inlining of functions) a large performance gain can be achieved.
|
inlining of functions) a large performance gain can be achieved.
|
|
|
In PSIM, modules are inlined in one of two possible ways. Some
|
In PSIM, modules are inlined in one of two possible ways. Some
|
modules (such as the byte swapping code) can be inlined into any
|
modules (such as the byte swapping code) can be inlined into any
|
module that calls them. Other modules, due to complex
|
module that calls them. Other modules, due to complex
|
interdependencies, are only inlined as a group when compiling the
|
interdependencies, are only inlined as a group when compiling the
|
external interface module psim.c.
|
external interface module psim.c.
|
|
|
Ex: default
|
Ex: default
|
|
|
By default the modules endian (handle be/le), bits (manipulate
|
By default the modules endian (handle be/le), bits (manipulate
|
bit-fields within words), cpu (the processor object) and events
|
bit-fields within words), cpu (the processor object) and events
|
(timers) are inlined in any module that calls them. This gives a
|
(timers) are inlined in any module that calls them. This gives a
|
reasonable performance gain with little additional compilation
|
reasonable performance gain with little additional compilation
|
overhead.
|
overhead.
|
|
|
Ex: recommended --enable-sim-inline
|
Ex: recommended --enable-sim-inline
|
|
|
Assuming you machine is reasonably well configured, this option is
|
Assuming you machine is reasonably well configured, this option is
|
highly recommended. On the x86 several orders of magnitude
|
highly recommended. On the x86 several orders of magnitude
|
improvement in performance is possible.
|
improvement in performance is possible.
|
|
|
Ex: fine tuning
|
Ex: fine tuning
|
|
|
The file std-config.h contains a detailed description of how the
|
The file std-config.h contains a detailed description of how the
|
inlining works. Individual modules can be inlined by specifying them.
|
inlining works. Individual modules can be inlined by specifying them.
|
For if you have a very large cache the model module could be inlined
|
For if you have a very large cache the model module could be inlined
|
with:
|
with:
|
|
|
--enable-sim-inline=MODEL
|
--enable-sim-inline=MODEL
|
|
|
|
|
|
|
--enable-sim-bswap
|
--enable-sim-bswap
|
|
|
|
|
(x86 specific) Use the i486/P5/P6 byte swap instruction.
|
(x86 specific) Use the i486/P5/P6 byte swap instruction.
|
|
|
PSIM contains generic byte swapping code. For the x86 (P[4-6]) PSIM
|
PSIM contains generic byte swapping code. For the x86 (P[4-6]) PSIM
|
can be built so that it uses the bswap instruction instead of relying
|
can be built so that it uses the bswap instruction instead of relying
|
on the compiler to generate byte swap code.
|
on the compiler to generate byte swap code.
|
|
|
Ex: default
|
Ex: default
|
|
|
By default, when compiling with GCC-2 on an i486/P5/P6 the bswap
|
By default, when compiling with GCC-2 on an i486/P5/P6 the bswap
|
instruction is used.
|
instruction is used.
|
|
|
|
|
|
|
--enable-sim-endian=endian
|
--enable-sim-endian=endian
|
|
|
|
|
Specify the byte order of the target.
|
Specify the byte order of the target.
|
|
|
By default, PSIM is able to execute both big and little endian
|
By default, PSIM is able to execute both big and little endian
|
executables. As a consequence, every byte swap routine includes a
|
executables. As a consequence, every byte swap routine includes a
|
test to see if the byte swap is really needed. By specifying the byte
|
test to see if the byte swap is really needed. By specifying the byte
|
order of the target (and the host below) the need for this test can be
|
order of the target (and the host below) the need for this test can be
|
eliminated.
|
eliminated.
|
|
|
Clearly setting the byte order of the target is only useful when known
|
Clearly setting the byte order of the target is only useful when known
|
before hand.
|
before hand.
|
|
|
|
|
|
|
--enable-sim-hostendain=end
|
--enable-sim-hostendain=end
|
|
|
|
|
As above but for the host.
|
As above but for the host.
|
|
|
Normally this option should not be needed. configure (autoconf) should
|
Normally this option should not be needed. configure (autoconf) should
|
determine the byte order of the host automatically. However if for
|
determine the byte order of the host automatically. However if for
|
some reason there is a problem, this option can be used to override
|
some reason there is a problem, this option can be used to override
|
autoconf.
|
autoconf.
|
|
|
|
|
|
|
--enable-sim-smp=n
|
--enable-sim-smp=n
|
|
|
|
|
Set the maximum number of processors that PSIM can model.
|
Set the maximum number of processors that PSIM can model.
|
|
|
Psim can model (with small limitation discussed else where) a
|
Psim can model (with small limitation discussed else where) a
|
multi-processor PowerPC environment. While the overhead of
|
multi-processor PowerPC environment. While the overhead of
|
co-ordinating the execution of a number of processors is relatively
|
co-ordinating the execution of a number of processors is relatively
|
small it is still significant when compared to handling only one
|
small it is still significant when compared to handling only one
|
processor.
|
processor.
|
|
|
This option only sets the maximum number of processors that can be
|
This option only sets the maximum number of processors that can be
|
simulated. The number active during a given simulation run us
|
simulated. The number active during a given simulation run us
|
determined at run time.
|
determined at run time.
|
|
|
Ex: default
|
Ex: default
|
|
|
By default 5 processors are configured but only one is enabled.
|
By default 5 processors are configured but only one is enabled.
|
Additional processors can be enabled with the runtime option:
|
Additional processors can be enabled with the runtime option:
|
|
|
-o '/openprom/options/smp 5'
|
-o '/openprom/options/smp 5'
|
|
|
Ex: recommended
|
Ex: recommended
|
|
|
Unless you intend studying multi-processor systems there is little reason for
|
Unless you intend studying multi-processor systems there is little reason for
|
having PSIM configured with SMP support. Specifying:
|
having PSIM configured with SMP support. Specifying:
|
|
|
--disable-sim-smp
|
--disable-sim-smp
|
or --enable-sim-smp=0
|
or --enable-sim-smp=0
|
|
|
will eliminate any SMP such as:
|
will eliminate any SMP such as:
|
|
|
for (cpu = 0; cpu < nr_cpus; cpu++)
|
for (cpu = 0; cpu < nr_cpus; cpu++)
|
...
|
...
|
|
|
|
|
|
|
--enable-sim-xor-endian=n
|
--enable-sim-xor-endian=n
|
|
|
|
|
Set the byte-size of the bus involved in the PowerPC's xor endian byte
|
Set the byte-size of the bus involved in the PowerPC's xor endian byte
|
swapping.
|
swapping.
|
|
|
The PowerPC's implementation of BE/LE mode is different to what a
|
The PowerPC's implementation of BE/LE mode is different to what a
|
programmer may first expect. The details of this implementation are
|
programmer may first expect. The details of this implementation are
|
discussed at length in PowerPC documentation.
|
discussed at length in PowerPC documentation.
|
|
|
Ex: default
|
Ex: default
|
|
|
By default this is configured with a value of 8 (the bus size of most
|
By default this is configured with a value of 8 (the bus size of most
|
60x processors).
|
60x processors).
|
|
|
Ex: recommended
|
Ex: recommended
|
|
|
Unless you are expecting to test/debug PowerPC be/le switching code
|
Unless you are expecting to test/debug PowerPC be/le switching code
|
this option is of little use and should be disabled:
|
this option is of little use and should be disabled:
|
|
|
--disable-sim-xor-endian
|
--disable-sim-xor-endian
|
|
|
|
|
|
|
--enable-sim-bitsize=n
|
--enable-sim-bitsize=n
|
|
|
|
|
Specify the bit size (32/64) of the PowerPC to be modelled.
|
Specify the bit size (32/64) of the PowerPC to be modelled.
|
|
|
Note: By default 32 is specified. The implementation of the 64bit
|
Note: By default 32 is specified. The implementation of the 64bit
|
architecture is still under development.
|
architecture is still under development.
|
|
|
|
|
--enable-sim-hostbitsize=32|64
|
--enable-sim-hostbitsize=32|64
|
|
|
As above but for the host.
|
As above but for the host.
|
|
|
NOTE: Psim has yet to be built on a 64bit host.
|
NOTE: Psim has yet to be built on a 64bit host.
|
|
|
|
|
|
|
--enable-sim-env=env
|
--enable-sim-env=env
|
|
|
|
|
Hardwire the PowerPC environment being modelled (user, virtual or
|
Hardwire the PowerPC environment being modelled (user, virtual or
|
operating).
|
operating).
|
|
|
The PowerPC architecture defines three different levels of compliance to its
|
The PowerPC architecture defines three different levels of compliance to its
|
architectural specification. These environments are discussed in detail in
|
architectural specification. These environments are discussed in detail in
|
PowerPC publications.
|
PowerPC publications.
|
|
|
user - normal user programs
|
user - normal user programs
|
virtual - an extension of the user environment (includes timers)
|
virtual - an extension of the user environment (includes timers)
|
operating - kernel code
|
operating - kernel code
|
|
|
Ex: default
|
Ex: default
|
|
|
By default all three environments are supported.
|
By default all three environments are supported.
|
|
|
Ex: recommended
|
Ex: recommended
|
|
|
If you only intend running psim with user (or operating) code then
|
If you only intend running psim with user (or operating) code then
|
PSIM should be configured accordingly. For user code, it eliminates:
|
PSIM should be configured accordingly. For user code, it eliminates:
|
support for timers and events and redundant VM calls.
|
support for timers and events and redundant VM calls.
|
|
|
|
|
|
|
--enable-sim-timebase
|
--enable-sim-timebase
|
|
|
|
|
Enable/disable the time base register.
|
Enable/disable the time base register.
|
|
|
The PowerPC architecture (virtual environment) includes a time base
|
The PowerPC architecture (virtual environment) includes a time base
|
register. Maintaining that register incurs an overhead in
|
register. Maintaining that register incurs an overhead in
|
performance that can be eliminated by eliminating time-base register
|
performance that can be eliminated by eliminating time-base register
|
support.
|
support.
|
|
|
Ex: default
|
Ex: default
|
|
|
Normally this option is not used. Instead --enable-sim-env (above) us
|
Normally this option is not used. Instead --enable-sim-env (above) us
|
used to disable/enable features such as the timebase register.
|
used to disable/enable features such as the timebase register.
|
|
|
|
|
|
|
--enable-sim-alignment=align
|
--enable-sim-alignment=align
|
|
|
|
|
Control the PowerPC's memory access alignment restrictions.
|
Control the PowerPC's memory access alignment restrictions.
|
|
|
The PowerPC in LE mode only allows memory transfers of a correctly
|
The PowerPC in LE mode only allows memory transfers of a correctly
|
aligned size/address. The above option controls how misaligned
|
aligned size/address. The above option controls how misaligned
|
accesses are handled.
|
accesses are handled.
|
|
|
strict All accesses must be correctly aligned
|
strict All accesses must be correctly aligned
|
|
|
nonstrict Unaligned access allowed (the are split
|
nonstrict Unaligned access allowed (the are split
|
into a number of aligned accesses).
|
into a number of aligned accesses).
|
|
|
Ex: default
|
Ex: default
|
|
|
Unless otherwise specified PSIM will auto configure a BE program to
|
Unless otherwise specified PSIM will auto configure a BE program to
|
allow miss-aligned accesses while a LE program will not.
|
allow miss-aligned accesses while a LE program will not.
|
|
|
Ex: 604e
|
Ex: 604e
|
|
|
The recently announced 604e processor allows miss-aligned accesses in both
|
The recently announced 604e processor allows miss-aligned accesses in both
|
BE and LE modes. If modeling the 604e then you should specify:
|
BE and LE modes. If modeling the 604e then you should specify:
|
|
|
--enable-sim-alignment=nonstrict
|
--enable-sim-alignment=nonstrict
|
|
|
|
|
|
|
--enable-sim-trace
|
--enable-sim-trace
|
|
|
|
|
Include code to trace PSIM's internal progress (also controlled by the
|
Include code to trace PSIM's internal progress (also controlled by the
|
-t option).
|
-t option).
|
|
|
Checking to see if a trace message should be output slows down a
|
Checking to see if a trace message should be output slows down a
|
simulation. Disabling this option (--disable-sim-trace) eliminates
|
simulation. Disabling this option (--disable-sim-trace) eliminates
|
completely that code.
|
completely that code.
|
|
|
|
|
|
|
--enable-sim-assert
|
--enable-sim-assert
|
|
|
|
|
Include the code that checks the correctness of parts of PSIM.
|
Include the code that checks the correctness of parts of PSIM.
|
|
|
Eliminating such code (--disable-sim-assert) eliminates internal
|
Eliminating such code (--disable-sim-assert) eliminates internal
|
consistency tests and their overhead.
|
consistency tests and their overhead.
|
|
|
|
|
|
|
--enable-sim-reserved-bits
|
--enable-sim-reserved-bits
|
|
|
|
|
Include code to check that the reserved fields of the instruction are
|
Include code to check that the reserved fields of the instruction are
|
zero.
|
zero.
|
|
|
The PowerPC architecture defines certain fields of some instructions
|
The PowerPC architecture defines certain fields of some instructions
|
as reserved (`/'). By default, for each instruction, PSIM will check
|
as reserved (`/'). By default, for each instruction, PSIM will check
|
the reserved fields causing an invalid instruction exception if a
|
the reserved fields causing an invalid instruction exception if a
|
field is invalid. Disabling this option eliminates this test. This
|
field is invalid. Disabling this option eliminates this test. This
|
is at the slight risk of PSIM treating an invalid instruction as
|
is at the slight risk of PSIM treating an invalid instruction as
|
valid.
|
valid.
|
|
|
|
|
|
|
--enable-sim-float
|
--enable-sim-float
|
|
|
|
|
Include support for hardware floating point.
|
Include support for hardware floating point.
|
|
|
|
|
|
|
--enable-sim-monitor=mon
|
--enable-sim-monitor=mon
|
|
|
|
|
Include support for basic instruction counting.
|
Include support for basic instruction counting.
|
|
|
If you are not interested in the performance of either you program or
|
If you are not interested in the performance of either you program or
|
the simulator then you can disable this option.
|
the simulator then you can disable this option.
|
|
|
|
|
|
|
--enable-sim-model=which
|
--enable-sim-model=which
|
|
|
Hardwire the processor that will be used as a reference when modeling
|
Hardwire the processor that will be used as a reference when modeling
|
execution units.
|
execution units.
|
|
|
|
|
|
|
--enable-sim-default-model=which
|
--enable-sim-default-model=which
|
|
|
|
|
Specify the processor of choice for the execution unit model.
|
Specify the processor of choice for the execution unit model.
|
|
|
|
|
|
|
--enable-sim-model-issue
|
--enable-sim-model-issue
|
|
|
|
|
Include support for the modeling of processor execution units.
|
Include support for the modeling of processor execution units.
|
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
TYPICAL CONFIGURATION OPTIONS:
|
TYPICAL CONFIGURATION OPTIONS:
|
|
|
|
|
VEA CODE ONLY:
|
VEA CODE ONLY:
|
|
|
Here of note are:
|
Here of note are:
|
|
|
o ramp up the compiler options (some
|
o ramp up the compiler options (some
|
of the below are P5 specific).
|
of the below are P5 specific).
|
|
|
o disable anything not used
|
o disable anything not used
|
|
|
CC=gcc ./configure \
|
CC=gcc ./configure \
|
--prefix=/applications/psim \
|
--prefix=/applications/psim \
|
--target=powerpc-unknown-eabi \
|
--target=powerpc-unknown-eabi \
|
--enable-sim-powerpc \
|
--enable-sim-powerpc \
|
--enable-sim-warnings \
|
--enable-sim-warnings \
|
--enable-sim-inline \
|
--enable-sim-inline \
|
--disable-sim-smp \
|
--disable-sim-smp \
|
--enable-sim-duplicate \
|
--enable-sim-duplicate \
|
--enable-sim-endian=big \
|
--enable-sim-endian=big \
|
--disable-sim-xor-endian \
|
--disable-sim-xor-endian \
|
--enable-sim-env=user \
|
--enable-sim-env=user \
|
--disable-sim-reserved-bits \
|
--disable-sim-reserved-bits \
|
--disable-sim-assert \
|
--disable-sim-assert \
|
--disable-sim-trace \
|
--disable-sim-trace \
|
--enable-sim-cflags='-g0,-O2,-fno-strength-reduce,-fomit-frame-pointer'
|
--enable-sim-cflags='-g0,-O2,-fno-strength-reduce,-fomit-frame-pointer'
|
|
|
|
|
OEA CODE ONLY:
|
OEA CODE ONLY:
|
|
|
The key configuration changes are:
|
The key configuration changes are:
|
|
|
o turn off the instruction cache. The overhead
|
o turn off the instruction cache. The overhead
|
of flushing and reloading it is greater than
|
of flushing and reloading it is greater than
|
not having a cache.
|
not having a cache.
|
|
|
o use a switch statement (ppc-opcode-flat) for
|
o use a switch statement (ppc-opcode-flat) for
|
the instruction decode and then (-O3) fully
|
the instruction decode and then (-O3) fully
|
inline all functions.
|
inline all functions.
|
|
|
o --enable-sim-warnings is not present. GCC (2.7.2)
|
o --enable-sim-warnings is not present. GCC (2.7.2)
|
gets confused by the instruction decode table
|
gets confused by the instruction decode table
|
generated by igen (contains a perfect switch)
|
generated by igen (contains a perfect switch)
|
and, as a consequence, generates a bogus warning.
|
and, as a consequence, generates a bogus warning.
|
|
|
CC=gcc ./configure \
|
CC=gcc ./configure \
|
--prefix=/applications/psim \
|
--prefix=/applications/psim \
|
--target=powerpc-unknown-eabi \
|
--target=powerpc-unknown-eabi \
|
--enable-sim-powerpc \
|
--enable-sim-powerpc \
|
--enable-sim-inline \
|
--enable-sim-inline \
|
--disable-sim-smp \
|
--disable-sim-smp \
|
--enable-sim-duplicate \
|
--enable-sim-duplicate \
|
--enable-sim-endian=big \
|
--enable-sim-endian=big \
|
--disable-sim-xor-endian \
|
--disable-sim-xor-endian \
|
--enable-sim-env=operating \
|
--enable-sim-env=operating \
|
--disable-sim-reserved-bits \
|
--disable-sim-reserved-bits \
|
--disable-sim-assert \
|
--disable-sim-assert \
|
--disable-sim-trace \
|
--disable-sim-trace \
|
--enable-sim-opcode=ppc-opcode-flat \
|
--enable-sim-opcode=ppc-opcode-flat \
|
--disable-sim-icache \
|
--disable-sim-icache \
|
--enable-sim-cflags='-g0,-O3,-fno-strength-reduce,-fomit-frame-pointer'
|
--enable-sim-cflags='-g0,-O3,-fno-strength-reduce,-fomit-frame-pointer'
|
|
|
