/* Target-dependent code for Lattice Mico32 processor, for GDB.
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/* Target-dependent code for Lattice Mico32 processor, for GDB.
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Contributed by Jon Beniston <jon@beniston.com>
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Contributed by Jon Beniston <jon@beniston.com>
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Copyright (C) 2009, 2010 Free Software Foundation, Inc.
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Copyright (C) 2009, 2010 Free Software Foundation, Inc.
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This file is part of GDB.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "defs.h"
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#include "frame.h"
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#include "frame.h"
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#include "frame-unwind.h"
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#include "frame-unwind.h"
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#include "frame-base.h"
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#include "frame-base.h"
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#include "inferior.h"
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#include "inferior.h"
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#include "dis-asm.h"
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#include "dis-asm.h"
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#include "symfile.h"
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#include "symfile.h"
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#include "remote.h"
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#include "remote.h"
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#include "gdbcore.h"
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#include "gdbcore.h"
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#include "gdb/sim-lm32.h"
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#include "gdb/sim-lm32.h"
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#include "gdb/callback.h"
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#include "gdb/callback.h"
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#include "gdb/remote-sim.h"
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#include "gdb/remote-sim.h"
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#include "sim-regno.h"
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#include "sim-regno.h"
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#include "arch-utils.h"
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#include "arch-utils.h"
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#include "regcache.h"
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#include "regcache.h"
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#include "trad-frame.h"
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#include "trad-frame.h"
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#include "reggroups.h"
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#include "reggroups.h"
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#include "opcodes/lm32-desc.h"
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#include "opcodes/lm32-desc.h"
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#include "gdb_string.h"
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#include "gdb_string.h"
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/* Macros to extract fields from an instruction. */
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/* Macros to extract fields from an instruction. */
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#define LM32_OPCODE(insn) ((insn >> 26) & 0x3f)
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#define LM32_OPCODE(insn) ((insn >> 26) & 0x3f)
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#define LM32_REG0(insn) ((insn >> 21) & 0x1f)
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#define LM32_REG0(insn) ((insn >> 21) & 0x1f)
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#define LM32_REG1(insn) ((insn >> 16) & 0x1f)
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#define LM32_REG1(insn) ((insn >> 16) & 0x1f)
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#define LM32_REG2(insn) ((insn >> 11) & 0x1f)
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#define LM32_REG2(insn) ((insn >> 11) & 0x1f)
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#define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16)
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#define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16)
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struct gdbarch_tdep
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struct gdbarch_tdep
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{
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{
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/* gdbarch target dependent data here. Currently unused for LM32. */
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/* gdbarch target dependent data here. Currently unused for LM32. */
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};
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};
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struct lm32_frame_cache
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struct lm32_frame_cache
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{
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{
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/* The frame's base. Used when constructing a frame ID. */
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/* The frame's base. Used when constructing a frame ID. */
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CORE_ADDR base;
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CORE_ADDR base;
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CORE_ADDR pc;
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CORE_ADDR pc;
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/* Size of frame. */
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/* Size of frame. */
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int size;
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int size;
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/* Table indicating the location of each and every register. */
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/* Table indicating the location of each and every register. */
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struct trad_frame_saved_reg *saved_regs;
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struct trad_frame_saved_reg *saved_regs;
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};
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};
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/* Add the available register groups. */
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/* Add the available register groups. */
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static void
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static void
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lm32_add_reggroups (struct gdbarch *gdbarch)
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lm32_add_reggroups (struct gdbarch *gdbarch)
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{
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{
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reggroup_add (gdbarch, general_reggroup);
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reggroup_add (gdbarch, general_reggroup);
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reggroup_add (gdbarch, all_reggroup);
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reggroup_add (gdbarch, all_reggroup);
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reggroup_add (gdbarch, system_reggroup);
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reggroup_add (gdbarch, system_reggroup);
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}
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}
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/* Return whether a given register is in a given group. */
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/* Return whether a given register is in a given group. */
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static int
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static int
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lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
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lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
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struct reggroup *group)
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struct reggroup *group)
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{
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{
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if (group == general_reggroup)
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if (group == general_reggroup)
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return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
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return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
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|| (regnum == SIM_LM32_PC_REGNUM);
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|| (regnum == SIM_LM32_PC_REGNUM);
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else if (group == system_reggroup)
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else if (group == system_reggroup)
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return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM))
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return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM))
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|| ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
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|| ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
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return default_register_reggroup_p (gdbarch, regnum, group);
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return default_register_reggroup_p (gdbarch, regnum, group);
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}
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}
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/* Return a name that corresponds to the given register number. */
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/* Return a name that corresponds to the given register number. */
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static const char *
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static const char *
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lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
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lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
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{
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{
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static char *register_names[] = {
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static char *register_names[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
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"r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
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"PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
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"PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
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};
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};
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if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
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if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
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return NULL;
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return NULL;
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else
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else
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return register_names[reg_nr];
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return register_names[reg_nr];
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}
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}
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/* Return type of register. */
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/* Return type of register. */
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static struct type *
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static struct type *
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lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
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lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
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{
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{
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return builtin_type (gdbarch)->builtin_int32;
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return builtin_type (gdbarch)->builtin_int32;
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}
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}
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/* Return non-zero if a register can't be written. */
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/* Return non-zero if a register can't be written. */
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static int
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static int
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lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
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lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
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{
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{
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return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
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return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
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}
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}
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/* Analyze a function's prologue. */
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/* Analyze a function's prologue. */
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static CORE_ADDR
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static CORE_ADDR
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lm32_analyze_prologue (struct gdbarch *gdbarch,
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lm32_analyze_prologue (struct gdbarch *gdbarch,
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CORE_ADDR pc, CORE_ADDR limit,
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CORE_ADDR pc, CORE_ADDR limit,
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struct lm32_frame_cache *info)
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struct lm32_frame_cache *info)
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{
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{
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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unsigned long instruction;
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unsigned long instruction;
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/* Keep reading though instructions, until we come across an instruction
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/* Keep reading though instructions, until we come across an instruction
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that isn't likely to be part of the prologue. */
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that isn't likely to be part of the prologue. */
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info->size = 0;
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info->size = 0;
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for (; pc < limit; pc += 4)
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for (; pc < limit; pc += 4)
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{
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{
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/* Read an instruction. */
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/* Read an instruction. */
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instruction = read_memory_integer (pc, 4, byte_order);
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instruction = read_memory_integer (pc, 4, byte_order);
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if ((LM32_OPCODE (instruction) == OP_SW)
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if ((LM32_OPCODE (instruction) == OP_SW)
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&& (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
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&& (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
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{
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{
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/* Any stack displaced store is likely part of the prologue.
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/* Any stack displaced store is likely part of the prologue.
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Record that the register is being saved, and the offset
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Record that the register is being saved, and the offset
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into the stack. */
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into the stack. */
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info->saved_regs[LM32_REG1 (instruction)].addr =
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info->saved_regs[LM32_REG1 (instruction)].addr =
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LM32_IMM16 (instruction);
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LM32_IMM16 (instruction);
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}
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}
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else if ((LM32_OPCODE (instruction) == OP_ADDI)
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else if ((LM32_OPCODE (instruction) == OP_ADDI)
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&& (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
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&& (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
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{
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{
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/* An add to the SP is likely to be part of the prologue.
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/* An add to the SP is likely to be part of the prologue.
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Adjust stack size by whatever the instruction adds to the sp. */
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Adjust stack size by whatever the instruction adds to the sp. */
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info->size -= LM32_IMM16 (instruction);
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info->size -= LM32_IMM16 (instruction);
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}
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}
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else if ( /* add fp,fp,sp */
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else if ( /* add fp,fp,sp */
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((LM32_OPCODE (instruction) == OP_ADD)
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((LM32_OPCODE (instruction) == OP_ADD)
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&& (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
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&& (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
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&& (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
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&& (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
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&& (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
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&& (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
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/* mv fp,imm */
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/* mv fp,imm */
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|| ((LM32_OPCODE (instruction) == OP_ADDI)
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|| ((LM32_OPCODE (instruction) == OP_ADDI)
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&& (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
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&& (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
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&& (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
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&& (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
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{
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{
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/* Likely to be in the prologue for functions that require
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/* Likely to be in the prologue for functions that require
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a frame pointer. */
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a frame pointer. */
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}
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}
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else
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else
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{
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{
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/* Any other instruction is likely not to be part of the prologue. */
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/* Any other instruction is likely not to be part of the prologue. */
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break;
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break;
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}
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}
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}
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}
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return pc;
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return pc;
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}
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}
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/* Return PC of first non prologue instruction, for the function at the
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/* Return PC of first non prologue instruction, for the function at the
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specified address. */
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specified address. */
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static CORE_ADDR
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static CORE_ADDR
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lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
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lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
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{
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{
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CORE_ADDR func_addr, limit_pc;
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CORE_ADDR func_addr, limit_pc;
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struct symtab_and_line sal;
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struct symtab_and_line sal;
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struct lm32_frame_cache frame_info;
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struct lm32_frame_cache frame_info;
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struct trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
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struct trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
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/* See if we can determine the end of the prologue via the symbol table.
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/* See if we can determine the end of the prologue via the symbol table.
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If so, then return either PC, or the PC after the prologue, whichever
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If so, then return either PC, or the PC after the prologue, whichever
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is greater. */
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is greater. */
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if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
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if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
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{
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{
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CORE_ADDR post_prologue_pc
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CORE_ADDR post_prologue_pc
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= skip_prologue_using_sal (gdbarch, func_addr);
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= skip_prologue_using_sal (gdbarch, func_addr);
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if (post_prologue_pc != 0)
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if (post_prologue_pc != 0)
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return max (pc, post_prologue_pc);
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return max (pc, post_prologue_pc);
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}
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}
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/* Can't determine prologue from the symbol table, need to examine
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/* Can't determine prologue from the symbol table, need to examine
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instructions. */
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instructions. */
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/* Find an upper limit on the function prologue using the debug
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/* Find an upper limit on the function prologue using the debug
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information. If the debug information could not be used to provide
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information. If the debug information could not be used to provide
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that bound, then use an arbitrary large number as the upper bound. */
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that bound, then use an arbitrary large number as the upper bound. */
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limit_pc = skip_prologue_using_sal (gdbarch, pc);
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limit_pc = skip_prologue_using_sal (gdbarch, pc);
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if (limit_pc == 0)
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if (limit_pc == 0)
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limit_pc = pc + 100; /* Magic. */
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limit_pc = pc + 100; /* Magic. */
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frame_info.saved_regs = saved_regs;
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frame_info.saved_regs = saved_regs;
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return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
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return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
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}
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}
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/* Create a breakpoint instruction. */
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/* Create a breakpoint instruction. */
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static const gdb_byte *
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static const gdb_byte *
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lm32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
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lm32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
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int *lenptr)
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int *lenptr)
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{
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{
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static const gdb_byte breakpoint[4] = { OP_RAISE << 2, 0, 0, 2 };
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static const gdb_byte breakpoint[4] = { OP_RAISE << 2, 0, 0, 2 };
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*lenptr = sizeof (breakpoint);
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*lenptr = sizeof (breakpoint);
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return breakpoint;
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return breakpoint;
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}
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}
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/* Setup registers and stack for faking a call to a function in the
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/* Setup registers and stack for faking a call to a function in the
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inferior. */
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inferior. */
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static CORE_ADDR
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static CORE_ADDR
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lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
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lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
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struct regcache *regcache, CORE_ADDR bp_addr,
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struct regcache *regcache, CORE_ADDR bp_addr,
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int nargs, struct value **args, CORE_ADDR sp,
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int nargs, struct value **args, CORE_ADDR sp,
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int struct_return, CORE_ADDR struct_addr)
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int struct_return, CORE_ADDR struct_addr)
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{
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{
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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int first_arg_reg = SIM_LM32_R1_REGNUM;
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int first_arg_reg = SIM_LM32_R1_REGNUM;
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int num_arg_regs = 8;
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int num_arg_regs = 8;
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int i;
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int i;
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/* Set the return address. */
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/* Set the return address. */
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regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
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regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
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/* If we're returning a large struct, a pointer to the address to
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/* If we're returning a large struct, a pointer to the address to
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store it at is passed as a first hidden parameter. */
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store it at is passed as a first hidden parameter. */
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if (struct_return)
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if (struct_return)
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{
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{
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regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
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regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
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first_arg_reg++;
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first_arg_reg++;
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num_arg_regs--;
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num_arg_regs--;
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sp -= 4;
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sp -= 4;
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}
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}
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/* Setup parameters. */
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/* Setup parameters. */
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for (i = 0; i < nargs; i++)
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for (i = 0; i < nargs; i++)
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{
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{
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struct value *arg = args[i];
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struct value *arg = args[i];
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struct type *arg_type = check_typedef (value_type (arg));
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struct type *arg_type = check_typedef (value_type (arg));
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gdb_byte *contents;
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gdb_byte *contents;
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int len;
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int len;
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int j;
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int j;
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int reg;
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int reg;
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ULONGEST val;
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ULONGEST val;
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|
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/* Promote small integer types to int. */
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/* Promote small integer types to int. */
|
switch (TYPE_CODE (arg_type))
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switch (TYPE_CODE (arg_type))
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{
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{
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case TYPE_CODE_INT:
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case TYPE_CODE_INT:
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case TYPE_CODE_BOOL:
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case TYPE_CODE_BOOL:
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case TYPE_CODE_CHAR:
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case TYPE_CODE_CHAR:
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case TYPE_CODE_RANGE:
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case TYPE_CODE_RANGE:
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case TYPE_CODE_ENUM:
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case TYPE_CODE_ENUM:
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if (TYPE_LENGTH (arg_type) < 4)
|
if (TYPE_LENGTH (arg_type) < 4)
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{
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{
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arg_type = builtin_type (gdbarch)->builtin_int32;
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arg_type = builtin_type (gdbarch)->builtin_int32;
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arg = value_cast (arg_type, arg);
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arg = value_cast (arg_type, arg);
|
}
|
}
|
break;
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break;
|
}
|
}
|
|
|
/* FIXME: Handle structures. */
|
/* FIXME: Handle structures. */
|
|
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contents = (gdb_byte *) value_contents (arg);
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contents = (gdb_byte *) value_contents (arg);
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len = TYPE_LENGTH (arg_type);
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len = TYPE_LENGTH (arg_type);
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val = extract_unsigned_integer (contents, len, byte_order);
|
val = extract_unsigned_integer (contents, len, byte_order);
|
|
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/* First num_arg_regs parameters are passed by registers,
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/* First num_arg_regs parameters are passed by registers,
|
and the rest are passed on the stack. */
|
and the rest are passed on the stack. */
|
if (i < num_arg_regs)
|
if (i < num_arg_regs)
|
regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
|
regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
|
else
|
else
|
{
|
{
|
write_memory (sp, (void *) &val, len);
|
write_memory (sp, (void *) &val, len);
|
sp -= 4;
|
sp -= 4;
|
}
|
}
|
}
|
}
|
|
|
/* Update stack pointer. */
|
/* Update stack pointer. */
|
regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
|
regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
|
|
|
/* Return adjusted stack pointer. */
|
/* Return adjusted stack pointer. */
|
return sp;
|
return sp;
|
}
|
}
|
|
|
/* Extract return value after calling a function in the inferior. */
|
/* Extract return value after calling a function in the inferior. */
|
|
|
static void
|
static void
|
lm32_extract_return_value (struct type *type, struct regcache *regcache,
|
lm32_extract_return_value (struct type *type, struct regcache *regcache,
|
gdb_byte *valbuf)
|
gdb_byte *valbuf)
|
{
|
{
|
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
int offset;
|
int offset;
|
ULONGEST l;
|
ULONGEST l;
|
CORE_ADDR return_buffer;
|
CORE_ADDR return_buffer;
|
|
|
if (TYPE_CODE (type) != TYPE_CODE_STRUCT
|
if (TYPE_CODE (type) != TYPE_CODE_STRUCT
|
&& TYPE_CODE (type) != TYPE_CODE_UNION
|
&& TYPE_CODE (type) != TYPE_CODE_UNION
|
&& TYPE_CODE (type) != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
|
&& TYPE_CODE (type) != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
|
{
|
{
|
/* Return value is returned in a single register. */
|
/* Return value is returned in a single register. */
|
regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
|
regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
|
store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
|
store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
|
}
|
}
|
else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
|
else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
|
{
|
{
|
/* 64-bit values are returned in a register pair. */
|
/* 64-bit values are returned in a register pair. */
|
regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
|
regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
|
memcpy (valbuf, &l, 4);
|
memcpy (valbuf, &l, 4);
|
regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
|
regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
|
memcpy (valbuf + 4, &l, 4);
|
memcpy (valbuf + 4, &l, 4);
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Aggregate types greater than a single register are returned in memory.
|
/* Aggregate types greater than a single register are returned in memory.
|
FIXME: Unless they are only 2 regs?. */
|
FIXME: Unless they are only 2 regs?. */
|
regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
|
regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
|
return_buffer = l;
|
return_buffer = l;
|
read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
|
read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
|
}
|
}
|
}
|
}
|
|
|
/* Write into appropriate registers a function return value of type
|
/* Write into appropriate registers a function return value of type
|
TYPE, given in virtual format. */
|
TYPE, given in virtual format. */
|
static void
|
static void
|
lm32_store_return_value (struct type *type, struct regcache *regcache,
|
lm32_store_return_value (struct type *type, struct regcache *regcache,
|
const gdb_byte *valbuf)
|
const gdb_byte *valbuf)
|
{
|
{
|
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
struct gdbarch *gdbarch = get_regcache_arch (regcache);
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
ULONGEST val;
|
ULONGEST val;
|
int len = TYPE_LENGTH (type);
|
int len = TYPE_LENGTH (type);
|
|
|
if (len <= 4)
|
if (len <= 4)
|
{
|
{
|
val = extract_unsigned_integer (valbuf, len, byte_order);
|
val = extract_unsigned_integer (valbuf, len, byte_order);
|
regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
|
regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
|
}
|
}
|
else if (len <= 8)
|
else if (len <= 8)
|
{
|
{
|
val = extract_unsigned_integer (valbuf, 4, byte_order);
|
val = extract_unsigned_integer (valbuf, 4, byte_order);
|
regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
|
regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
|
val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
|
val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
|
regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
|
regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
|
}
|
}
|
else
|
else
|
error (_("lm32_store_return_value: type length too large."));
|
error (_("lm32_store_return_value: type length too large."));
|
}
|
}
|
|
|
/* Determine whether a functions return value is in a register or memory. */
|
/* Determine whether a functions return value is in a register or memory. */
|
static enum return_value_convention
|
static enum return_value_convention
|
lm32_return_value (struct gdbarch *gdbarch, struct type *func_type,
|
lm32_return_value (struct gdbarch *gdbarch, struct type *func_type,
|
struct type *valtype, struct regcache *regcache,
|
struct type *valtype, struct regcache *regcache,
|
gdb_byte *readbuf, const gdb_byte *writebuf)
|
gdb_byte *readbuf, const gdb_byte *writebuf)
|
{
|
{
|
enum type_code code = TYPE_CODE (valtype);
|
enum type_code code = TYPE_CODE (valtype);
|
|
|
if (code == TYPE_CODE_STRUCT
|
if (code == TYPE_CODE_STRUCT
|
|| code == TYPE_CODE_UNION
|
|| code == TYPE_CODE_UNION
|
|| code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)
|
|| code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)
|
return RETURN_VALUE_STRUCT_CONVENTION;
|
return RETURN_VALUE_STRUCT_CONVENTION;
|
|
|
if (readbuf)
|
if (readbuf)
|
lm32_extract_return_value (valtype, regcache, readbuf);
|
lm32_extract_return_value (valtype, regcache, readbuf);
|
if (writebuf)
|
if (writebuf)
|
lm32_store_return_value (valtype, regcache, writebuf);
|
lm32_store_return_value (valtype, regcache, writebuf);
|
|
|
return RETURN_VALUE_REGISTER_CONVENTION;
|
return RETURN_VALUE_REGISTER_CONVENTION;
|
}
|
}
|
|
|
static CORE_ADDR
|
static CORE_ADDR
|
lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
|
lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
|
{
|
{
|
return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM);
|
return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM);
|
}
|
}
|
|
|
static CORE_ADDR
|
static CORE_ADDR
|
lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
|
lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
|
{
|
{
|
return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM);
|
return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM);
|
}
|
}
|
|
|
static struct frame_id
|
static struct frame_id
|
lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
|
lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
|
{
|
{
|
CORE_ADDR sp = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
|
CORE_ADDR sp = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
|
|
|
return frame_id_build (sp, get_frame_pc (this_frame));
|
return frame_id_build (sp, get_frame_pc (this_frame));
|
}
|
}
|
|
|
/* Put here the code to store, into fi->saved_regs, the addresses of
|
/* Put here the code to store, into fi->saved_regs, the addresses of
|
the saved registers of frame described by FRAME_INFO. This
|
the saved registers of frame described by FRAME_INFO. This
|
includes special registers such as pc and fp saved in special ways
|
includes special registers such as pc and fp saved in special ways
|
in the stack frame. sp is even more special: the address we return
|
in the stack frame. sp is even more special: the address we return
|
for it IS the sp for the next frame. */
|
for it IS the sp for the next frame. */
|
|
|
static struct lm32_frame_cache *
|
static struct lm32_frame_cache *
|
lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
|
lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
|
{
|
{
|
CORE_ADDR prologue_pc;
|
CORE_ADDR prologue_pc;
|
CORE_ADDR current_pc;
|
CORE_ADDR current_pc;
|
ULONGEST prev_sp;
|
ULONGEST prev_sp;
|
ULONGEST this_base;
|
ULONGEST this_base;
|
struct lm32_frame_cache *info;
|
struct lm32_frame_cache *info;
|
int prefixed;
|
int prefixed;
|
unsigned long instruction;
|
unsigned long instruction;
|
int op;
|
int op;
|
int offsets[32];
|
int offsets[32];
|
int i;
|
int i;
|
long immediate;
|
long immediate;
|
|
|
if ((*this_prologue_cache))
|
if ((*this_prologue_cache))
|
return (*this_prologue_cache);
|
return (*this_prologue_cache);
|
|
|
info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
|
info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
|
(*this_prologue_cache) = info;
|
(*this_prologue_cache) = info;
|
info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
|
info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
|
|
|
info->pc = get_frame_func (this_frame);
|
info->pc = get_frame_func (this_frame);
|
current_pc = get_frame_pc (this_frame);
|
current_pc = get_frame_pc (this_frame);
|
lm32_analyze_prologue (get_frame_arch (this_frame),
|
lm32_analyze_prologue (get_frame_arch (this_frame),
|
info->pc, current_pc, info);
|
info->pc, current_pc, info);
|
|
|
/* Compute the frame's base, and the previous frame's SP. */
|
/* Compute the frame's base, and the previous frame's SP. */
|
this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
|
this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
|
prev_sp = this_base + info->size;
|
prev_sp = this_base + info->size;
|
info->base = this_base;
|
info->base = this_base;
|
|
|
/* Convert callee save offsets into addresses. */
|
/* Convert callee save offsets into addresses. */
|
for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
|
for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
|
{
|
{
|
if (trad_frame_addr_p (info->saved_regs, i))
|
if (trad_frame_addr_p (info->saved_regs, i))
|
info->saved_regs[i].addr = this_base + info->saved_regs[i].addr;
|
info->saved_regs[i].addr = this_base + info->saved_regs[i].addr;
|
}
|
}
|
|
|
/* The call instruction moves the caller's PC in the callee's RA register.
|
/* The call instruction moves the caller's PC in the callee's RA register.
|
Since this is an unwind, do the reverse. Copy the location of RA register
|
Since this is an unwind, do the reverse. Copy the location of RA register
|
into PC (the address / regnum) so that a request for PC will be
|
into PC (the address / regnum) so that a request for PC will be
|
converted into a request for the RA register. */
|
converted into a request for the RA register. */
|
info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
|
info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
|
|
|
/* The previous frame's SP needed to be computed. Save the computed value. */
|
/* The previous frame's SP needed to be computed. Save the computed value. */
|
trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);
|
trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);
|
|
|
return info;
|
return info;
|
}
|
}
|
|
|
static void
|
static void
|
lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,
|
lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,
|
struct frame_id *this_id)
|
struct frame_id *this_id)
|
{
|
{
|
struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
|
struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
|
|
|
/* This marks the outermost frame. */
|
/* This marks the outermost frame. */
|
if (cache->base == 0)
|
if (cache->base == 0)
|
return;
|
return;
|
|
|
(*this_id) = frame_id_build (cache->base, cache->pc);
|
(*this_id) = frame_id_build (cache->base, cache->pc);
|
}
|
}
|
|
|
static struct value *
|
static struct value *
|
lm32_frame_prev_register (struct frame_info *this_frame,
|
lm32_frame_prev_register (struct frame_info *this_frame,
|
void **this_prologue_cache, int regnum)
|
void **this_prologue_cache, int regnum)
|
{
|
{
|
struct lm32_frame_cache *info;
|
struct lm32_frame_cache *info;
|
|
|
info = lm32_frame_cache (this_frame, this_prologue_cache);
|
info = lm32_frame_cache (this_frame, this_prologue_cache);
|
return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
|
return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
|
}
|
}
|
|
|
static const struct frame_unwind lm32_frame_unwind = {
|
static const struct frame_unwind lm32_frame_unwind = {
|
NORMAL_FRAME,
|
NORMAL_FRAME,
|
lm32_frame_this_id,
|
lm32_frame_this_id,
|
lm32_frame_prev_register,
|
lm32_frame_prev_register,
|
NULL,
|
NULL,
|
default_frame_sniffer
|
default_frame_sniffer
|
};
|
};
|
|
|
static CORE_ADDR
|
static CORE_ADDR
|
lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)
|
lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)
|
{
|
{
|
struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
|
struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
|
|
|
return info->base;
|
return info->base;
|
}
|
}
|
|
|
static const struct frame_base lm32_frame_base = {
|
static const struct frame_base lm32_frame_base = {
|
&lm32_frame_unwind,
|
&lm32_frame_unwind,
|
lm32_frame_base_address,
|
lm32_frame_base_address,
|
lm32_frame_base_address,
|
lm32_frame_base_address,
|
lm32_frame_base_address
|
lm32_frame_base_address
|
};
|
};
|
|
|
static CORE_ADDR
|
static CORE_ADDR
|
lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
|
lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
|
{
|
{
|
/* Align to the size of an instruction (so that they can safely be
|
/* Align to the size of an instruction (so that they can safely be
|
pushed onto the stack. */
|
pushed onto the stack. */
|
return sp & ~3;
|
return sp & ~3;
|
}
|
}
|
|
|
static struct gdbarch *
|
static struct gdbarch *
|
lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
{
|
{
|
struct gdbarch *gdbarch;
|
struct gdbarch *gdbarch;
|
struct gdbarch_tdep *tdep;
|
struct gdbarch_tdep *tdep;
|
|
|
/* If there is already a candidate, use it. */
|
/* If there is already a candidate, use it. */
|
arches = gdbarch_list_lookup_by_info (arches, &info);
|
arches = gdbarch_list_lookup_by_info (arches, &info);
|
if (arches != NULL)
|
if (arches != NULL)
|
return arches->gdbarch;
|
return arches->gdbarch;
|
|
|
/* None found, create a new architecture from the information provided. */
|
/* None found, create a new architecture from the information provided. */
|
tdep = XMALLOC (struct gdbarch_tdep);
|
tdep = XMALLOC (struct gdbarch_tdep);
|
gdbarch = gdbarch_alloc (&info, tdep);
|
gdbarch = gdbarch_alloc (&info, tdep);
|
|
|
/* Type sizes. */
|
/* Type sizes. */
|
set_gdbarch_short_bit (gdbarch, 16);
|
set_gdbarch_short_bit (gdbarch, 16);
|
set_gdbarch_int_bit (gdbarch, 32);
|
set_gdbarch_int_bit (gdbarch, 32);
|
set_gdbarch_long_bit (gdbarch, 32);
|
set_gdbarch_long_bit (gdbarch, 32);
|
set_gdbarch_long_long_bit (gdbarch, 64);
|
set_gdbarch_long_long_bit (gdbarch, 64);
|
set_gdbarch_float_bit (gdbarch, 32);
|
set_gdbarch_float_bit (gdbarch, 32);
|
set_gdbarch_double_bit (gdbarch, 64);
|
set_gdbarch_double_bit (gdbarch, 64);
|
set_gdbarch_long_double_bit (gdbarch, 64);
|
set_gdbarch_long_double_bit (gdbarch, 64);
|
set_gdbarch_ptr_bit (gdbarch, 32);
|
set_gdbarch_ptr_bit (gdbarch, 32);
|
|
|
/* Register info. */
|
/* Register info. */
|
set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
|
set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
|
set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
|
set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
|
set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
|
set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
|
set_gdbarch_register_name (gdbarch, lm32_register_name);
|
set_gdbarch_register_name (gdbarch, lm32_register_name);
|
set_gdbarch_register_type (gdbarch, lm32_register_type);
|
set_gdbarch_register_type (gdbarch, lm32_register_type);
|
set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
|
set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
|
|
|
/* Frame info. */
|
/* Frame info. */
|
set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
|
set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
|
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
|
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
|
set_gdbarch_decr_pc_after_break (gdbarch, 0);
|
set_gdbarch_decr_pc_after_break (gdbarch, 0);
|
set_gdbarch_frame_args_skip (gdbarch, 0);
|
set_gdbarch_frame_args_skip (gdbarch, 0);
|
|
|
/* Frame unwinding. */
|
/* Frame unwinding. */
|
set_gdbarch_frame_align (gdbarch, lm32_frame_align);
|
set_gdbarch_frame_align (gdbarch, lm32_frame_align);
|
frame_base_set_default (gdbarch, &lm32_frame_base);
|
frame_base_set_default (gdbarch, &lm32_frame_base);
|
set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);
|
set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);
|
set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);
|
set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);
|
set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);
|
set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);
|
frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
|
frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
|
|
|
/* Breakpoints. */
|
/* Breakpoints. */
|
set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);
|
set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);
|
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
|
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
|
|
|
/* Calling functions in the inferior. */
|
/* Calling functions in the inferior. */
|
set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
|
set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
|
set_gdbarch_return_value (gdbarch, lm32_return_value);
|
set_gdbarch_return_value (gdbarch, lm32_return_value);
|
|
|
/* Instruction disassembler. */
|
/* Instruction disassembler. */
|
set_gdbarch_print_insn (gdbarch, print_insn_lm32);
|
set_gdbarch_print_insn (gdbarch, print_insn_lm32);
|
|
|
lm32_add_reggroups (gdbarch);
|
lm32_add_reggroups (gdbarch);
|
set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
|
set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
|
|
|
return gdbarch;
|
return gdbarch;
|
}
|
}
|
|
|
void
|
void
|
_initialize_lm32_tdep (void)
|
_initialize_lm32_tdep (void)
|
{
|
{
|
register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
|
register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
|
}
|
}
|
|
|
