/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
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/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
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Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010
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Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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This file is part of GDB.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef MIPS_TDEP_H
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#ifndef MIPS_TDEP_H
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#define MIPS_TDEP_H
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#define MIPS_TDEP_H
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struct gdbarch;
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struct gdbarch;
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/* All the possible MIPS ABIs. */
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/* All the possible MIPS ABIs. */
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enum mips_abi
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enum mips_abi
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{
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{
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MIPS_ABI_UNKNOWN = 0,
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MIPS_ABI_UNKNOWN = 0,
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MIPS_ABI_N32,
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MIPS_ABI_N32,
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MIPS_ABI_O32,
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MIPS_ABI_O32,
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MIPS_ABI_N64,
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MIPS_ABI_N64,
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MIPS_ABI_O64,
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MIPS_ABI_O64,
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MIPS_ABI_EABI32,
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MIPS_ABI_EABI32,
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MIPS_ABI_EABI64,
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MIPS_ABI_EABI64,
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MIPS_ABI_LAST
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MIPS_ABI_LAST
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};
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};
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/* Return the MIPS ABI associated with GDBARCH. */
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/* Return the MIPS ABI associated with GDBARCH. */
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enum mips_abi mips_abi (struct gdbarch *gdbarch);
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enum mips_abi mips_abi (struct gdbarch *gdbarch);
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/* Return the MIPS ISA's register size. Just a short cut to the BFD
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/* Return the MIPS ISA's register size. Just a short cut to the BFD
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architecture's word size. */
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architecture's word size. */
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extern int mips_isa_regsize (struct gdbarch *gdbarch);
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extern int mips_isa_regsize (struct gdbarch *gdbarch);
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/* Return the current index for various MIPS registers. */
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/* Return the current index for various MIPS registers. */
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struct mips_regnum
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struct mips_regnum
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{
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{
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int pc;
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int pc;
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int fp0;
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int fp0;
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int fp_implementation_revision;
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int fp_implementation_revision;
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int fp_control_status;
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int fp_control_status;
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int badvaddr; /* Bad vaddr for addressing exception. */
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int badvaddr; /* Bad vaddr for addressing exception. */
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int cause; /* Describes last exception. */
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int cause; /* Describes last exception. */
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int hi; /* Multiply/divide temp. */
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int hi; /* Multiply/divide temp. */
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int lo; /* ... */
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int lo; /* ... */
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};
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};
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extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch);
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extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch);
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/* Some MIPS boards don't support floating point while others only
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/* Some MIPS boards don't support floating point while others only
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support single-precision floating-point operations. */
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support single-precision floating-point operations. */
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enum mips_fpu_type
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enum mips_fpu_type
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{
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{
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MIPS_FPU_DOUBLE, /* Full double precision floating point. */
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MIPS_FPU_DOUBLE, /* Full double precision floating point. */
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MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
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MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
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MIPS_FPU_NONE /* No floating point. */
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MIPS_FPU_NONE /* No floating point. */
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};
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};
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/* MIPS specific per-architecture information */
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/* MIPS specific per-architecture information */
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struct gdbarch_tdep
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struct gdbarch_tdep
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{
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{
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/* from the elf header */
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/* from the elf header */
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int elf_flags;
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int elf_flags;
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/* mips options */
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/* mips options */
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enum mips_abi mips_abi;
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enum mips_abi mips_abi;
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enum mips_abi found_abi;
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enum mips_abi found_abi;
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enum mips_fpu_type mips_fpu_type;
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enum mips_fpu_type mips_fpu_type;
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int mips_last_arg_regnum;
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int mips_last_arg_regnum;
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int mips_last_fp_arg_regnum;
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int mips_last_fp_arg_regnum;
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int default_mask_address_p;
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int default_mask_address_p;
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/* Is the target using 64-bit raw integer registers but only
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/* Is the target using 64-bit raw integer registers but only
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storing a left-aligned 32-bit value in each? */
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storing a left-aligned 32-bit value in each? */
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int mips64_transfers_32bit_regs_p;
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int mips64_transfers_32bit_regs_p;
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/* Indexes for various registers. IRIX and embedded have
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/* Indexes for various registers. IRIX and embedded have
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different values. This contains the "public" fields. Don't
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different values. This contains the "public" fields. Don't
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add any that do not need to be public. */
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add any that do not need to be public. */
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const struct mips_regnum *regnum;
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const struct mips_regnum *regnum;
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/* Register names table for the current register set. */
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/* Register names table for the current register set. */
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const char **mips_processor_reg_names;
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const char **mips_processor_reg_names;
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/* The size of register data available from the target, if known.
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/* The size of register data available from the target, if known.
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This doesn't quite obsolete the manual
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This doesn't quite obsolete the manual
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mips64_transfers_32bit_regs_p, since that is documented to force
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mips64_transfers_32bit_regs_p, since that is documented to force
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left alignment even for big endian (very strange). */
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left alignment even for big endian (very strange). */
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int register_size_valid_p;
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int register_size_valid_p;
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int register_size;
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int register_size;
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/* Return the expected next PC if FRAME is stopped at a syscall
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/* Return the expected next PC if FRAME is stopped at a syscall
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instruction. */
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instruction. */
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CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
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CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
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};
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};
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/* Register numbers of various important registers. */
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/* Register numbers of various important registers. */
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enum
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enum
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{
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{
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MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */
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MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */
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MIPS_AT_REGNUM = 1,
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MIPS_AT_REGNUM = 1,
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MIPS_V0_REGNUM = 2, /* Function integer return value. */
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MIPS_V0_REGNUM = 2, /* Function integer return value. */
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MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call */
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MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call */
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MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */
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MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */
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MIPS_SP_REGNUM = 29,
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MIPS_SP_REGNUM = 29,
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MIPS_RA_REGNUM = 31,
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MIPS_RA_REGNUM = 31,
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MIPS_PS_REGNUM = 32, /* Contains processor status. */
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MIPS_PS_REGNUM = 32, /* Contains processor status. */
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MIPS_EMBED_LO_REGNUM = 33,
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MIPS_EMBED_LO_REGNUM = 33,
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MIPS_EMBED_HI_REGNUM = 34,
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MIPS_EMBED_HI_REGNUM = 34,
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MIPS_EMBED_BADVADDR_REGNUM = 35,
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MIPS_EMBED_BADVADDR_REGNUM = 35,
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MIPS_EMBED_CAUSE_REGNUM = 36,
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MIPS_EMBED_CAUSE_REGNUM = 36,
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MIPS_EMBED_PC_REGNUM = 37,
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MIPS_EMBED_PC_REGNUM = 37,
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MIPS_EMBED_FP0_REGNUM = 38,
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MIPS_EMBED_FP0_REGNUM = 38,
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MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME */
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MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME */
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MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */
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MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */
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MIPS_PRID_REGNUM = 89, /* Processor ID. */
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MIPS_PRID_REGNUM = 89, /* Processor ID. */
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MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */
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MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */
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};
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};
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/* Defined in mips-tdep.c and used in remote-mips.c */
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/* Defined in mips-tdep.c and used in remote-mips.c */
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extern void deprecated_mips_set_processor_regs_hack (void);
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extern void deprecated_mips_set_processor_regs_hack (void);
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/* Instruction sizes and other useful constants. */
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/* Instruction sizes and other useful constants. */
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enum
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enum
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{
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{
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MIPS_INSN16_SIZE = 2,
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MIPS_INSN16_SIZE = 2,
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MIPS_INSN32_SIZE = 4,
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MIPS_INSN32_SIZE = 4,
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/* The number of floating-point or integer registers. */
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/* The number of floating-point or integer registers. */
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MIPS_NUMREGS = 32
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MIPS_NUMREGS = 32
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};
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};
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/* Single step based on where the current instruction will take us. */
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/* Single step based on where the current instruction will take us. */
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extern int mips_software_single_step (struct frame_info *frame);
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extern int mips_software_single_step (struct frame_info *frame);
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/* Tell if the program counter value in MEMADDR is in a MIPS16
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/* Tell if the program counter value in MEMADDR is in a MIPS16
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function. */
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function. */
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extern int mips_pc_is_mips16 (bfd_vma memaddr);
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extern int mips_pc_is_mips16 (bfd_vma memaddr);
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/* Return the currently configured (or set) saved register size. */
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/* Return the currently configured (or set) saved register size. */
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extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
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extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
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/* Target descriptions which only indicate the size of general
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/* Target descriptions which only indicate the size of general
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registers. */
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registers. */
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extern struct target_desc *mips_tdesc_gp32;
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extern struct target_desc *mips_tdesc_gp32;
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extern struct target_desc *mips_tdesc_gp64;
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extern struct target_desc *mips_tdesc_gp64;
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#endif /* MIPS_TDEP_H */
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#endif /* MIPS_TDEP_H */
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