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/* PPC GNU/Linux native support.

/* PPC GNU/Linux native support.

   Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003,

   Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003,

   2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.

   2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.

   This file is part of GDB.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3 of the License, or

   the Free Software Foundation; either version 3 of the License, or

   (at your option) any later version.

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   You should have received a copy of the GNU General Public License

   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "defs.h"

#include "defs.h"

#include "gdb_string.h"

#include "gdb_string.h"

#include "frame.h"

#include "frame.h"

#include "inferior.h"

#include "inferior.h"

#include "gdbcore.h"

#include "gdbcore.h"

#include "regcache.h"

#include "regcache.h"

#include "gdb_assert.h"

#include "gdb_assert.h"

#include "target.h"

#include "target.h"

#include "linux-nat.h"

#include "linux-nat.h"

#include <stdint.h>

#include <stdint.h>

#include <sys/types.h>

#include <sys/types.h>

#include <sys/param.h>

#include <sys/param.h>

#include <signal.h>

#include <signal.h>

#include <sys/user.h>

#include <sys/user.h>

#include <sys/ioctl.h>

#include <sys/ioctl.h>

#include "gdb_wait.h"

#include "gdb_wait.h"

#include <fcntl.h>

#include <fcntl.h>

#include <sys/procfs.h>

#include <sys/procfs.h>

#include <sys/ptrace.h>

#include <sys/ptrace.h>

/* Prototypes for supply_gregset etc. */

/* Prototypes for supply_gregset etc. */

#include "gregset.h"

#include "gregset.h"

#include "ppc-tdep.h"

#include "ppc-tdep.h"

#include "ppc-linux-tdep.h"

#include "ppc-linux-tdep.h"

/* Required when using the AUXV.  */

/* Required when using the AUXV.  */

#include "elf/common.h"

#include "elf/common.h"

#include "auxv.h"

#include "auxv.h"

/* This sometimes isn't defined.  */

/* This sometimes isn't defined.  */

#ifndef PT_ORIG_R3

#ifndef PT_ORIG_R3

#define PT_ORIG_R3 34

#define PT_ORIG_R3 34

#endif

#endif

#ifndef PT_TRAP

#ifndef PT_TRAP

#define PT_TRAP 40

#define PT_TRAP 40

#endif

#endif

/* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.

/* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.

   If they aren't, we can provide them ourselves (their values are fixed

   If they aren't, we can provide them ourselves (their values are fixed

   because they are part of the kernel ABI).  They are used in the AT_HWCAP

   because they are part of the kernel ABI).  They are used in the AT_HWCAP

   entry of the AUXV.  */

   entry of the AUXV.  */

#ifndef PPC_FEATURE_CELL

#ifndef PPC_FEATURE_CELL

#define PPC_FEATURE_CELL 0x00010000

#define PPC_FEATURE_CELL 0x00010000

#endif

#endif

#ifndef PPC_FEATURE_BOOKE

#ifndef PPC_FEATURE_BOOKE

#define PPC_FEATURE_BOOKE 0x00008000

#define PPC_FEATURE_BOOKE 0x00008000

#endif

#endif

#ifndef PPC_FEATURE_HAS_DFP

#ifndef PPC_FEATURE_HAS_DFP

#define PPC_FEATURE_HAS_DFP     0x00000400  /* Decimal Floating Point.  */

#define PPC_FEATURE_HAS_DFP     0x00000400  /* Decimal Floating Point.  */

#endif

#endif

/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a

/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a

   configure time check.  Some older glibc's (for instance 2.2.1)

   configure time check.  Some older glibc's (for instance 2.2.1)

   don't have a specific powerpc version of ptrace.h, and fall back on

   don't have a specific powerpc version of ptrace.h, and fall back on

   a generic one.  In such cases, sys/ptrace.h defines

   a generic one.  In such cases, sys/ptrace.h defines

   PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that

   PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that

   ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and

   ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and

   PTRACE_SETVRREGS to be.  This also makes a configury check pretty

   PTRACE_SETVRREGS to be.  This also makes a configury check pretty

   much useless.  */

   much useless.  */

/* These definitions should really come from the glibc header files,

/* These definitions should really come from the glibc header files,

   but Glibc doesn't know about the vrregs yet.  */

   but Glibc doesn't know about the vrregs yet.  */

#ifndef PTRACE_GETVRREGS

#ifndef PTRACE_GETVRREGS

#define PTRACE_GETVRREGS 18

#define PTRACE_GETVRREGS 18

#define PTRACE_SETVRREGS 19

#define PTRACE_SETVRREGS 19

#endif

#endif

/* PTRACE requests for POWER7 VSX registers.  */

/* PTRACE requests for POWER7 VSX registers.  */

#ifndef PTRACE_GETVSXREGS

#ifndef PTRACE_GETVSXREGS

#define PTRACE_GETVSXREGS 27

#define PTRACE_GETVSXREGS 27

#define PTRACE_SETVSXREGS 28

#define PTRACE_SETVSXREGS 28

#endif

#endif

/* Similarly for the ptrace requests for getting / setting the SPE

/* Similarly for the ptrace requests for getting / setting the SPE

   registers (ev0 -- ev31, acc, and spefscr).  See the description of

   registers (ev0 -- ev31, acc, and spefscr).  See the description of

   gdb_evrregset_t for details.  */

   gdb_evrregset_t for details.  */

#ifndef PTRACE_GETEVRREGS

#ifndef PTRACE_GETEVRREGS

#define PTRACE_GETEVRREGS 20

#define PTRACE_GETEVRREGS 20

#define PTRACE_SETEVRREGS 21

#define PTRACE_SETEVRREGS 21

#endif

#endif

/* Similarly for the hardware watchpoint support.  */

/* Similarly for the hardware watchpoint support.  */

#ifndef PTRACE_GET_DEBUGREG

#ifndef PTRACE_GET_DEBUGREG

#define PTRACE_GET_DEBUGREG    25

#define PTRACE_GET_DEBUGREG    25

#endif

#endif

#ifndef PTRACE_SET_DEBUGREG

#ifndef PTRACE_SET_DEBUGREG

#define PTRACE_SET_DEBUGREG    26

#define PTRACE_SET_DEBUGREG    26

#endif

#endif

#ifndef PTRACE_GETSIGINFO

#ifndef PTRACE_GETSIGINFO

#define PTRACE_GETSIGINFO    0x4202

#define PTRACE_GETSIGINFO    0x4202

#endif

#endif

/* Similarly for the general-purpose (gp0 -- gp31)

/* Similarly for the general-purpose (gp0 -- gp31)

   and floating-point registers (fp0 -- fp31).  */

   and floating-point registers (fp0 -- fp31).  */

#ifndef PTRACE_GETREGS

#ifndef PTRACE_GETREGS

#define PTRACE_GETREGS 12

#define PTRACE_GETREGS 12

#endif

#endif

#ifndef PTRACE_SETREGS

#ifndef PTRACE_SETREGS

#define PTRACE_SETREGS 13

#define PTRACE_SETREGS 13

#endif

#endif

#ifndef PTRACE_GETFPREGS

#ifndef PTRACE_GETFPREGS

#define PTRACE_GETFPREGS 14

#define PTRACE_GETFPREGS 14

#endif

#endif

#ifndef PTRACE_SETFPREGS

#ifndef PTRACE_SETFPREGS

#define PTRACE_SETFPREGS 15

#define PTRACE_SETFPREGS 15

#endif

#endif

/* This oddity is because the Linux kernel defines elf_vrregset_t as

/* This oddity is because the Linux kernel defines elf_vrregset_t as

   an array of 33 16 bytes long elements.  I.e. it leaves out vrsave.

   an array of 33 16 bytes long elements.  I.e. it leaves out vrsave.

   However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return

   However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return

   the vrsave as an extra 4 bytes at the end.  I opted for creating a

   the vrsave as an extra 4 bytes at the end.  I opted for creating a

   flat array of chars, so that it is easier to manipulate for gdb.

   flat array of chars, so that it is easier to manipulate for gdb.

   There are 32 vector registers 16 bytes longs, plus a VSCR register

   There are 32 vector registers 16 bytes longs, plus a VSCR register

   which is only 4 bytes long, but is fetched as a 16 bytes

   which is only 4 bytes long, but is fetched as a 16 bytes

   quantity. Up to here we have the elf_vrregset_t structure.

   quantity. Up to here we have the elf_vrregset_t structure.

   Appended to this there is space for the VRSAVE register: 4 bytes.

   Appended to this there is space for the VRSAVE register: 4 bytes.

   Even though this vrsave register is not included in the regset

   Even though this vrsave register is not included in the regset

   typedef, it is handled by the ptrace requests.

   typedef, it is handled by the ptrace requests.

   Note that GNU/Linux doesn't support little endian PPC hardware,

   Note that GNU/Linux doesn't support little endian PPC hardware,

   therefore the offset at which the real value of the VSCR register

   therefore the offset at which the real value of the VSCR register

   is located will be always 12 bytes.

   is located will be always 12 bytes.

   The layout is like this (where x is the actual value of the vscr reg): */

   The layout is like this (where x is the actual value of the vscr reg): */

/* *INDENT-OFF* */

/* *INDENT-OFF* */

/*

/*

   |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|

   |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|

   <------->     <-------><-------><->

   <------->     <-------><-------><->

     VR0           VR31     VSCR    VRSAVE

     VR0           VR31     VSCR    VRSAVE

*/

*/

/* *INDENT-ON* */

/* *INDENT-ON* */

#define SIZEOF_VRREGS 33*16+4

#define SIZEOF_VRREGS 33*16+4

typedef char gdb_vrregset_t[SIZEOF_VRREGS];

typedef char gdb_vrregset_t[SIZEOF_VRREGS];

/* This is the layout of the POWER7 VSX registers and the way they overlap

/* This is the layout of the POWER7 VSX registers and the way they overlap

   with the existing FPR and VMX registers.

   with the existing FPR and VMX registers.

                    VSR doubleword 0               VSR doubleword 1

                    VSR doubleword 0               VSR doubleword 1

           ----------------------------------------------------------------

           ----------------------------------------------------------------

   VSR[0]  |             FPR[0]            |                              |

   VSR[0]  |             FPR[0]            |                              |

           ----------------------------------------------------------------

           ----------------------------------------------------------------

   VSR[1]  |             FPR[1]            |                              |

   VSR[1]  |             FPR[1]            |                              |

           ----------------------------------------------------------------

           ----------------------------------------------------------------

           |              ...              |                              |

           |              ...              |                              |

           |              ...              |                              |

           |              ...              |                              |

           ----------------------------------------------------------------

           ----------------------------------------------------------------

   VSR[30] |             FPR[30]           |                              |

   VSR[30] |             FPR[30]           |                              |

           ----------------------------------------------------------------

           ----------------------------------------------------------------

   VSR[31] |             FPR[31]           |                              |

   VSR[31] |             FPR[31]           |                              |

           ----------------------------------------------------------------

           ----------------------------------------------------------------

   VSR[32] |                             VR[0]                            |

   VSR[32] |                             VR[0]                            |

           ----------------------------------------------------------------

           ----------------------------------------------------------------

   VSR[33] |                             VR[1]                            |

   VSR[33] |                             VR[1]                            |

           ----------------------------------------------------------------

           ----------------------------------------------------------------

           |                              ...                             |

           |                              ...                             |

           |                              ...                             |

           |                              ...                             |

           ----------------------------------------------------------------

           ----------------------------------------------------------------

   VSR[62] |                             VR[30]                           |

   VSR[62] |                             VR[30]                           |

           ----------------------------------------------------------------

           ----------------------------------------------------------------

   VSR[63] |                             VR[31]                           |

   VSR[63] |                             VR[31]                           |

          ----------------------------------------------------------------

          ----------------------------------------------------------------

   VSX has 64 128bit registers.  The first 32 registers overlap with

   VSX has 64 128bit registers.  The first 32 registers overlap with

   the FP registers (doubleword 0) and hence extend them with additional

   the FP registers (doubleword 0) and hence extend them with additional

   64 bits (doubleword 1).  The other 32 regs overlap with the VMX

   64 bits (doubleword 1).  The other 32 regs overlap with the VMX

   registers.  */

   registers.  */

#define SIZEOF_VSXREGS 32*8

#define SIZEOF_VSXREGS 32*8

typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];

typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];

/* On PPC processors that support the the Signal Processing Extension

/* On PPC processors that support the the Signal Processing Extension

   (SPE) APU, the general-purpose registers are 64 bits long.

   (SPE) APU, the general-purpose registers are 64 bits long.

   However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER

   However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER

   ptrace calls only access the lower half of each register, to allow

   ptrace calls only access the lower half of each register, to allow

   them to behave the same way they do on non-SPE systems.  There's a

   them to behave the same way they do on non-SPE systems.  There's a

   separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that

   separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that

   read and write the top halves of all the general-purpose registers

   read and write the top halves of all the general-purpose registers

   at once, along with some SPE-specific registers.

   at once, along with some SPE-specific registers.

   GDB itself continues to claim the general-purpose registers are 32

   GDB itself continues to claim the general-purpose registers are 32

   bits long.  It has unnamed raw registers that hold the upper halves

   bits long.  It has unnamed raw registers that hold the upper halves

   of the gprs, and the the full 64-bit SIMD views of the registers,

   of the gprs, and the the full 64-bit SIMD views of the registers,

   'ev0' -- 'ev31', are pseudo-registers that splice the top and

   'ev0' -- 'ev31', are pseudo-registers that splice the top and

   bottom halves together.

   bottom halves together.

   This is the structure filled in by PTRACE_GETEVRREGS and written to

   This is the structure filled in by PTRACE_GETEVRREGS and written to

   the inferior's registers by PTRACE_SETEVRREGS.  */

   the inferior's registers by PTRACE_SETEVRREGS.  */

struct gdb_evrregset_t

struct gdb_evrregset_t

{

{

  unsigned long evr[32];

  unsigned long evr[32];

  unsigned long long acc;

  unsigned long long acc;

  unsigned long spefscr;

  unsigned long spefscr;

};

};

/* Non-zero if our kernel may support the PTRACE_GETVSXREGS and

/* Non-zero if our kernel may support the PTRACE_GETVSXREGS and

   PTRACE_SETVSXREGS requests, for reading and writing the VSX

   PTRACE_SETVSXREGS requests, for reading and writing the VSX

   POWER7 registers 0 through 31.  Zero if we've tried one of them and

   POWER7 registers 0 through 31.  Zero if we've tried one of them and

   gotten an error.  Note that VSX registers 32 through 63 overlap

   gotten an error.  Note that VSX registers 32 through 63 overlap

   with VR registers 0 through 31.  */

   with VR registers 0 through 31.  */

int have_ptrace_getsetvsxregs = 1;

int have_ptrace_getsetvsxregs = 1;

/* Non-zero if our kernel may support the PTRACE_GETVRREGS and

/* Non-zero if our kernel may support the PTRACE_GETVRREGS and

   PTRACE_SETVRREGS requests, for reading and writing the Altivec

   PTRACE_SETVRREGS requests, for reading and writing the Altivec

   registers.  Zero if we've tried one of them and gotten an

   registers.  Zero if we've tried one of them and gotten an

   error.  */

   error.  */

int have_ptrace_getvrregs = 1;

int have_ptrace_getvrregs = 1;

/* Non-zero if our kernel may support the PTRACE_GETEVRREGS and

/* Non-zero if our kernel may support the PTRACE_GETEVRREGS and

   PTRACE_SETEVRREGS requests, for reading and writing the SPE

   PTRACE_SETEVRREGS requests, for reading and writing the SPE

   registers.  Zero if we've tried one of them and gotten an

   registers.  Zero if we've tried one of them and gotten an

   error.  */

   error.  */

int have_ptrace_getsetevrregs = 1;

int have_ptrace_getsetevrregs = 1;

/* Non-zero if our kernel may support the PTRACE_GETREGS and

/* Non-zero if our kernel may support the PTRACE_GETREGS and

   PTRACE_SETREGS requests, for reading and writing the

   PTRACE_SETREGS requests, for reading and writing the

   general-purpose registers.  Zero if we've tried one of

   general-purpose registers.  Zero if we've tried one of

   them and gotten an error.  */

   them and gotten an error.  */

int have_ptrace_getsetregs = 1;

int have_ptrace_getsetregs = 1;

/* Non-zero if our kernel may support the PTRACE_GETFPREGS and

/* Non-zero if our kernel may support the PTRACE_GETFPREGS and

   PTRACE_SETFPREGS requests, for reading and writing the

   PTRACE_SETFPREGS requests, for reading and writing the

   floating-pointers registers.  Zero if we've tried one of

   floating-pointers registers.  Zero if we've tried one of

   them and gotten an error.  */

   them and gotten an error.  */

int have_ptrace_getsetfpregs = 1;

int have_ptrace_getsetfpregs = 1;

/* *INDENT-OFF* */

/* *INDENT-OFF* */

/* registers layout, as presented by the ptrace interface:

/* registers layout, as presented by the ptrace interface:

PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,

PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,

PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,

PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,

PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,

PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,

PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,

PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,

PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,

PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,

PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,

PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,

PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,

PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,

PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,

PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,

PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */

PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */

/* *INDENT_ON * */

/* *INDENT_ON * */

static int

static int

ppc_register_u_addr (struct gdbarch *gdbarch, int regno)

ppc_register_u_addr (struct gdbarch *gdbarch, int regno)

{

{

  int u_addr = -1;

  int u_addr = -1;

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace

  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace

     interface, and not the wordsize of the program's ABI.  */

     interface, and not the wordsize of the program's ABI.  */

  int wordsize = sizeof (long);

  int wordsize = sizeof (long);

  /* General purpose registers occupy 1 slot each in the buffer */

  /* General purpose registers occupy 1 slot each in the buffer */

  if (regno >= tdep->ppc_gp0_regnum

  if (regno >= tdep->ppc_gp0_regnum

      && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)

      && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)

    u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);

    u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);

  /* Floating point regs: eight bytes each in both 32- and 64-bit

  /* Floating point regs: eight bytes each in both 32- and 64-bit

     ptrace interfaces.  Thus, two slots each in 32-bit interface, one

     ptrace interfaces.  Thus, two slots each in 32-bit interface, one

     slot each in 64-bit interface.  */

     slot each in 64-bit interface.  */

  if (tdep->ppc_fp0_regnum >= 0

  if (tdep->ppc_fp0_regnum >= 0

      && regno >= tdep->ppc_fp0_regnum

      && regno >= tdep->ppc_fp0_regnum

      && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)

      && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)

    u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);

    u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);

  /* UISA special purpose registers: 1 slot each */

  /* UISA special purpose registers: 1 slot each */

  if (regno == gdbarch_pc_regnum (gdbarch))

  if (regno == gdbarch_pc_regnum (gdbarch))

    u_addr = PT_NIP * wordsize;

    u_addr = PT_NIP * wordsize;

  if (regno == tdep->ppc_lr_regnum)

  if (regno == tdep->ppc_lr_regnum)

    u_addr = PT_LNK * wordsize;

    u_addr = PT_LNK * wordsize;

  if (regno == tdep->ppc_cr_regnum)

  if (regno == tdep->ppc_cr_regnum)

    u_addr = PT_CCR * wordsize;

    u_addr = PT_CCR * wordsize;

  if (regno == tdep->ppc_xer_regnum)

  if (regno == tdep->ppc_xer_regnum)

    u_addr = PT_XER * wordsize;

    u_addr = PT_XER * wordsize;

  if (regno == tdep->ppc_ctr_regnum)

  if (regno == tdep->ppc_ctr_regnum)

    u_addr = PT_CTR * wordsize;

    u_addr = PT_CTR * wordsize;

#ifdef PT_MQ

#ifdef PT_MQ

  if (regno == tdep->ppc_mq_regnum)

  if (regno == tdep->ppc_mq_regnum)

    u_addr = PT_MQ * wordsize;

    u_addr = PT_MQ * wordsize;

#endif

#endif

  if (regno == tdep->ppc_ps_regnum)

  if (regno == tdep->ppc_ps_regnum)

    u_addr = PT_MSR * wordsize;

    u_addr = PT_MSR * wordsize;

  if (regno == PPC_ORIG_R3_REGNUM)

  if (regno == PPC_ORIG_R3_REGNUM)

    u_addr = PT_ORIG_R3 * wordsize;

    u_addr = PT_ORIG_R3 * wordsize;

  if (regno == PPC_TRAP_REGNUM)

  if (regno == PPC_TRAP_REGNUM)

    u_addr = PT_TRAP * wordsize;

    u_addr = PT_TRAP * wordsize;

  if (tdep->ppc_fpscr_regnum >= 0

  if (tdep->ppc_fpscr_regnum >= 0

      && regno == tdep->ppc_fpscr_regnum)

      && regno == tdep->ppc_fpscr_regnum)

    {

    {

      /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the

      /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the

         kernel headers incorrectly contained the 32-bit definition of

         kernel headers incorrectly contained the 32-bit definition of

         PT_FPSCR.  For the 32-bit definition, floating-point

         PT_FPSCR.  For the 32-bit definition, floating-point

         registers occupy two 32-bit "slots", and the FPSCR lives in

         registers occupy two 32-bit "slots", and the FPSCR lives in

         the second half of such a slot-pair (hence +1).  For 64-bit,

         the second half of such a slot-pair (hence +1).  For 64-bit,

         the FPSCR instead occupies the full 64-bit 2-word-slot and

         the FPSCR instead occupies the full 64-bit 2-word-slot and

         hence no adjustment is necessary.  Hack around this.  */

         hence no adjustment is necessary.  Hack around this.  */

      if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))

      if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))

        u_addr = (48 + 32) * wordsize;

        u_addr = (48 + 32) * wordsize;

      /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit

      /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit

         slot and not just its second word.  The PT_FPSCR supplied when

         slot and not just its second word.  The PT_FPSCR supplied when

         GDB is compiled as a 32-bit app doesn't reflect this.  */

         GDB is compiled as a 32-bit app doesn't reflect this.  */

      else if (wordsize == 4 && register_size (gdbarch, regno) == 8

      else if (wordsize == 4 && register_size (gdbarch, regno) == 8

               && PT_FPSCR == (48 + 2*32 + 1))

               && PT_FPSCR == (48 + 2*32 + 1))

        u_addr = (48 + 2*32) * wordsize;

        u_addr = (48 + 2*32) * wordsize;

      else

      else

        u_addr = PT_FPSCR * wordsize;

        u_addr = PT_FPSCR * wordsize;

    }

    }

  return u_addr;

  return u_addr;

}

}

/* The Linux kernel ptrace interface for POWER7 VSX registers uses the

/* The Linux kernel ptrace interface for POWER7 VSX registers uses the

   registers set mechanism, as opposed to the interface for all the

   registers set mechanism, as opposed to the interface for all the

   other registers, that stores/fetches each register individually.  */

   other registers, that stores/fetches each register individually.  */

static void

static void

fetch_vsx_register (struct regcache *regcache, int tid, int regno)

fetch_vsx_register (struct regcache *regcache, int tid, int regno)

{

{

  int ret;

  int ret;

  gdb_vsxregset_t regs;

  gdb_vsxregset_t regs;

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);

  int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);

  ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);

  ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);

  if (ret < 0)

  if (ret < 0)

    {

    {

      if (errno == EIO)

      if (errno == EIO)

        {

        {

          have_ptrace_getsetvsxregs = 0;

          have_ptrace_getsetvsxregs = 0;

          return;

          return;

        }

        }

      perror_with_name (_("Unable to fetch VSX register"));

      perror_with_name (_("Unable to fetch VSX register"));

    }

    }

  regcache_raw_supply (regcache, regno,

  regcache_raw_supply (regcache, regno,

                       regs + (regno - tdep->ppc_vsr0_upper_regnum)

                       regs + (regno - tdep->ppc_vsr0_upper_regnum)

                       * vsxregsize);

                       * vsxregsize);

}

}

/* The Linux kernel ptrace interface for AltiVec registers uses the

/* The Linux kernel ptrace interface for AltiVec registers uses the

   registers set mechanism, as opposed to the interface for all the

   registers set mechanism, as opposed to the interface for all the

   other registers, that stores/fetches each register individually.  */

   other registers, that stores/fetches each register individually.  */

static void

static void

fetch_altivec_register (struct regcache *regcache, int tid, int regno)

fetch_altivec_register (struct regcache *regcache, int tid, int regno)

{

{

  int ret;

  int ret;

  int offset = 0;

  int offset = 0;

  gdb_vrregset_t regs;

  gdb_vrregset_t regs;

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);

  int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);

  ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);

  ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);

  if (ret < 0)

  if (ret < 0)

    {

    {

      if (errno == EIO)

      if (errno == EIO)

        {

        {

          have_ptrace_getvrregs = 0;

          have_ptrace_getvrregs = 0;

          return;

          return;

        }

        }

      perror_with_name (_("Unable to fetch AltiVec register"));

      perror_with_name (_("Unable to fetch AltiVec register"));

    }

    }

  /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes

  /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes

     long on the hardware.  We deal only with the lower 4 bytes of the

     long on the hardware.  We deal only with the lower 4 bytes of the

     vector.  VRSAVE is at the end of the array in a 4 bytes slot, so

     vector.  VRSAVE is at the end of the array in a 4 bytes slot, so

     there is no need to define an offset for it.  */

     there is no need to define an offset for it.  */

  if (regno == (tdep->ppc_vrsave_regnum - 1))

  if (regno == (tdep->ppc_vrsave_regnum - 1))

    offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);

    offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);

  regcache_raw_supply (regcache, regno,

  regcache_raw_supply (regcache, regno,

                       regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);

                       regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);

}

}

/* Fetch the top 32 bits of TID's general-purpose registers and the

/* Fetch the top 32 bits of TID's general-purpose registers and the

   SPE-specific registers, and place the results in EVRREGSET.  If we

   SPE-specific registers, and place the results in EVRREGSET.  If we

   don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with

   don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with

   zeros.

   zeros.

   All the logic to deal with whether or not the PTRACE_GETEVRREGS and

   All the logic to deal with whether or not the PTRACE_GETEVRREGS and

   PTRACE_SETEVRREGS requests are supported is isolated here, and in

   PTRACE_SETEVRREGS requests are supported is isolated here, and in

   set_spe_registers.  */

   set_spe_registers.  */

static void

static void

get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)

get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)

{

{

  if (have_ptrace_getsetevrregs)

  if (have_ptrace_getsetevrregs)

    {

    {

      if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)

      if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)

        return;

        return;

      else

      else

        {

        {

          /* EIO means that the PTRACE_GETEVRREGS request isn't supported;

          /* EIO means that the PTRACE_GETEVRREGS request isn't supported;

             we just return zeros.  */

             we just return zeros.  */

          if (errno == EIO)

          if (errno == EIO)

            have_ptrace_getsetevrregs = 0;

            have_ptrace_getsetevrregs = 0;

          else

          else

            /* Anything else needs to be reported.  */

            /* Anything else needs to be reported.  */

            perror_with_name (_("Unable to fetch SPE registers"));

            perror_with_name (_("Unable to fetch SPE registers"));

        }

        }

    }

    }

  memset (evrregset, 0, sizeof (*evrregset));

  memset (evrregset, 0, sizeof (*evrregset));

}

}

/* Supply values from TID for SPE-specific raw registers: the upper

/* Supply values from TID for SPE-specific raw registers: the upper

   halves of the GPRs, the accumulator, and the spefscr.  REGNO must

   halves of the GPRs, the accumulator, and the spefscr.  REGNO must

   be the number of an upper half register, acc, spefscr, or -1 to

   be the number of an upper half register, acc, spefscr, or -1 to

   supply the values of all registers.  */

   supply the values of all registers.  */

static void

static void

fetch_spe_register (struct regcache *regcache, int tid, int regno)

fetch_spe_register (struct regcache *regcache, int tid, int regno)

{

{

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  struct gdb_evrregset_t evrregs;

  struct gdb_evrregset_t evrregs;

  gdb_assert (sizeof (evrregs.evr[0])

  gdb_assert (sizeof (evrregs.evr[0])

              == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));

              == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));

  gdb_assert (sizeof (evrregs.acc)

  gdb_assert (sizeof (evrregs.acc)

              == register_size (gdbarch, tdep->ppc_acc_regnum));

              == register_size (gdbarch, tdep->ppc_acc_regnum));

  gdb_assert (sizeof (evrregs.spefscr)

  gdb_assert (sizeof (evrregs.spefscr)

              == register_size (gdbarch, tdep->ppc_spefscr_regnum));

              == register_size (gdbarch, tdep->ppc_spefscr_regnum));

  get_spe_registers (tid, &evrregs);

  get_spe_registers (tid, &evrregs);

  if (regno == -1)

  if (regno == -1)

    {

    {

      int i;

      int i;

      for (i = 0; i < ppc_num_gprs; i++)

      for (i = 0; i < ppc_num_gprs; i++)

        regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,

        regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,

                             &evrregs.evr[i]);

                             &evrregs.evr[i]);

    }

    }

  else if (tdep->ppc_ev0_upper_regnum <= regno

  else if (tdep->ppc_ev0_upper_regnum <= regno

           && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)

           && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)

    regcache_raw_supply (regcache, regno,

    regcache_raw_supply (regcache, regno,

                         &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);

                         &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);

  if (regno == -1

  if (regno == -1

      || regno == tdep->ppc_acc_regnum)

      || regno == tdep->ppc_acc_regnum)

    regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);

    regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);

  if (regno == -1

  if (regno == -1

      || regno == tdep->ppc_spefscr_regnum)

      || regno == tdep->ppc_spefscr_regnum)

    regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,

    regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,

                         &evrregs.spefscr);

                         &evrregs.spefscr);

}

}

static void

static void

fetch_register (struct regcache *regcache, int tid, int regno)

fetch_register (struct regcache *regcache, int tid, int regno)

{

{

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  /* This isn't really an address.  But ptrace thinks of it as one.  */

  /* This isn't really an address.  But ptrace thinks of it as one.  */

  CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);

  CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);

  int bytes_transferred;

  int bytes_transferred;

  unsigned int offset;         /* Offset of registers within the u area. */

  unsigned int offset;         /* Offset of registers within the u area. */

  char buf[MAX_REGISTER_SIZE];

  char buf[MAX_REGISTER_SIZE];

  if (altivec_register_p (gdbarch, regno))

  if (altivec_register_p (gdbarch, regno))

    {

    {

      /* If this is the first time through, or if it is not the first

      /* If this is the first time through, or if it is not the first

         time through, and we have comfirmed that there is kernel

         time through, and we have comfirmed that there is kernel

         support for such a ptrace request, then go and fetch the

         support for such a ptrace request, then go and fetch the

         register.  */

         register.  */

      if (have_ptrace_getvrregs)

      if (have_ptrace_getvrregs)

       {

       {

         fetch_altivec_register (regcache, tid, regno);

         fetch_altivec_register (regcache, tid, regno);

         return;

         return;

       }

       }

     /* If we have discovered that there is no ptrace support for

     /* If we have discovered that there is no ptrace support for

        AltiVec registers, fall through and return zeroes, because

        AltiVec registers, fall through and return zeroes, because

        regaddr will be -1 in this case.  */

        regaddr will be -1 in this case.  */

    }

    }

  if (vsx_register_p (gdbarch, regno))

  if (vsx_register_p (gdbarch, regno))

    {

    {

      if (have_ptrace_getsetvsxregs)

      if (have_ptrace_getsetvsxregs)

        {

        {

          fetch_vsx_register (regcache, tid, regno);

          fetch_vsx_register (regcache, tid, regno);

          return;

          return;

        }

        }

    }

    }

  else if (spe_register_p (gdbarch, regno))

  else if (spe_register_p (gdbarch, regno))

    {

    {

      fetch_spe_register (regcache, tid, regno);

      fetch_spe_register (regcache, tid, regno);

      return;

      return;

    }

    }

  if (regaddr == -1)

  if (regaddr == -1)

    {

    {

      memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */

      memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */

      regcache_raw_supply (regcache, regno, buf);

      regcache_raw_supply (regcache, regno, buf);

      return;

      return;

    }

    }

  /* Read the raw register using sizeof(long) sized chunks.  On a

  /* Read the raw register using sizeof(long) sized chunks.  On a

     32-bit platform, 64-bit floating-point registers will require two

     32-bit platform, 64-bit floating-point registers will require two

     transfers.  */

     transfers.  */

  for (bytes_transferred = 0;

  for (bytes_transferred = 0;

       bytes_transferred < register_size (gdbarch, regno);

       bytes_transferred < register_size (gdbarch, regno);

       bytes_transferred += sizeof (long))

       bytes_transferred += sizeof (long))

    {

    {

      errno = 0;

      errno = 0;

      *(long *) &buf[bytes_transferred]

      *(long *) &buf[bytes_transferred]

        = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);

        = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);

      regaddr += sizeof (long);

      regaddr += sizeof (long);

      if (errno != 0)

      if (errno != 0)

        {

        {

          char message[128];

          char message[128];

          sprintf (message, "reading register %s (#%d)",

          sprintf (message, "reading register %s (#%d)",

                   gdbarch_register_name (gdbarch, regno), regno);

                   gdbarch_register_name (gdbarch, regno), regno);

          perror_with_name (message);

          perror_with_name (message);

        }

        }

    }

    }

  /* Now supply the register.  Keep in mind that the regcache's idea

  /* Now supply the register.  Keep in mind that the regcache's idea

     of the register's size may not be a multiple of sizeof

     of the register's size may not be a multiple of sizeof

     (long).  */

     (long).  */

  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)

  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)

    {

    {

      /* Little-endian values are always found at the left end of the

      /* Little-endian values are always found at the left end of the

         bytes transferred.  */

         bytes transferred.  */

      regcache_raw_supply (regcache, regno, buf);

      regcache_raw_supply (regcache, regno, buf);

    }

    }

  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)

  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)

    {

    {

      /* Big-endian values are found at the right end of the bytes

      /* Big-endian values are found at the right end of the bytes

         transferred.  */

         transferred.  */

      size_t padding = (bytes_transferred - register_size (gdbarch, regno));

      size_t padding = (bytes_transferred - register_size (gdbarch, regno));

      regcache_raw_supply (regcache, regno, buf + padding);

      regcache_raw_supply (regcache, regno, buf + padding);

    }

    }

  else

  else

    internal_error (__FILE__, __LINE__,

    internal_error (__FILE__, __LINE__,

                    _("fetch_register: unexpected byte order: %d"),

                    _("fetch_register: unexpected byte order: %d"),

                    gdbarch_byte_order (gdbarch));

                    gdbarch_byte_order (gdbarch));

}

}

static void

static void

supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)

supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)

{

{

  int i;

  int i;

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);

  int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);

  for (i = 0; i < ppc_num_vshrs; i++)

  for (i = 0; i < ppc_num_vshrs; i++)

    {

    {

        regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,

        regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,

                             *vsxregsetp + i * vsxregsize);

                             *vsxregsetp + i * vsxregsize);

    }

    }

}

}

static void

static void

supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)

supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)

{

{

  int i;

  int i;

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch *gdbarch = get_regcache_arch (regcache);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;

  int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;

  int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);

  int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);

  int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);

  int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);

  for (i = 0; i < num_of_vrregs; i++)

  for (i = 0; i < num_of_vrregs; i++)

    {

    {

      /* The last 2 registers of this set are only 32 bit long, not

      /* The last 2 registers of this set are only 32 bit long, not

         128.  However an offset is necessary only for VSCR because it

         128.  However an offset is necessary only for VSCR because it

         occupies a whole vector, while VRSAVE occupies a full 4 bytes

         occupies a whole vector, while VRSAVE occupies a full 4 bytes

         slot.  */

         slot.  */

      if (i == (num_of_vrregs - 2))

      if (i == (num_of_vrregs - 2))

        regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,

        regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,

                             *vrregsetp + i * vrregsize + offset);

                             *vrregsetp + i * vrregsize + offset);

      else

      else

        regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,

        regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,

                             *vrregsetp + i * vrregsize);

                             *vrregsetp + i * vrregsize);

    }

    }

}

}

static void

static void

fetch_vsx_registers (struct regcache *regcache, int tid)

fetch_vsx_registers (struct regcache *regcache, int tid)

{

{

  int ret;

  int ret;

  gdb_vsxregset_t regs;

  gdb_vsxregset_t regs;

  ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);

  ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);

  if (ret < 0)

  if (ret < 0)