/* score-inst.h -- Score Instructions Table
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/* score-inst.h -- Score Instructions Table
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Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
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Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
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Contributed by:
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Contributed by:
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Brain.lin (brain.lin@sunplusct.com)
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Brain.lin (brain.lin@sunplusct.com)
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Mei Ligang (ligang@sunnorth.com.cn)
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Mei Ligang (ligang@sunnorth.com.cn)
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Pei-Lin Tsai (pltsai@sunplus.com)
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Pei-Lin Tsai (pltsai@sunplus.com)
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This file is part of GAS, the GNU Assembler.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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GAS is distributed in the hope that it will be useful,
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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02110-1301, USA. */
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#ifndef SCORE_INST_H
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#ifndef SCORE_INST_H
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#define SCORE_INST_H
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#define SCORE_INST_H
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#define LDST_UNALIGN_MASK 0x0000007f
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#define LDST_UNALIGN_MASK 0x0000007f
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#define UA_LCB 0x00000060
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#define UA_LCB 0x00000060
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#define UA_LCW 0x00000062
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#define UA_LCW 0x00000062
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#define UA_LCE 0x00000066
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#define UA_LCE 0x00000066
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#define UA_SCB 0x00000068
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#define UA_SCB 0x00000068
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#define UA_SCW 0x0000006a
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#define UA_SCW 0x0000006a
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#define UA_SCE 0x0000006e
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#define UA_SCE 0x0000006e
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#define UA_LL 0x0000000c
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#define UA_LL 0x0000000c
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#define UA_SC 0x0000000e
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#define UA_SC 0x0000000e
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#define LDST16_RR_MASK 0x0000000f
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#define LDST16_RR_MASK 0x0000000f
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#define N16_LW 8
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#define N16_LW 8
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#define N16_LH 9
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#define N16_LH 9
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#define N16_POP 10
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#define N16_POP 10
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#define N16_LBU 11
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#define N16_LBU 11
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#define N16_SW 12
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#define N16_SW 12
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#define N16_SH 13
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#define N16_SH 13
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#define N16_PUSH 14
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#define N16_PUSH 14
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#define N16_SB 15
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#define N16_SB 15
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#define LDST16_RI_MASK 0x7007
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#define LDST16_RI_MASK 0x7007
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#define N16_LWP 0x7000
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#define N16_LWP 0x7000
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#define N16_LHP 0x7001
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#define N16_LHP 0x7001
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#define N16_LBUP 0x7003
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#define N16_LBUP 0x7003
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#define N16_SWP 0x7004
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#define N16_SWP 0x7004
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#define N16_SHP 0x7005
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#define N16_SHP 0x7005
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#define N16_SBP 0x7007
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#define N16_SBP 0x7007
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#define N16_LIU 0x5000
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#define N16_LIU 0x5000
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#define OPC_PSEUDOLDST_MASK 0x00000007
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#define OPC_PSEUDOLDST_MASK 0x00000007
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enum
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enum
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{
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{
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INSN_LW = 0,
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INSN_LW = 0,
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INSN_LH = 1,
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INSN_LH = 1,
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INSN_LHU = 2,
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INSN_LHU = 2,
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INSN_LB = 3,
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INSN_LB = 3,
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INSN_SW = 4,
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INSN_SW = 4,
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INSN_SH = 5,
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INSN_SH = 5,
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INSN_LBU = 6,
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INSN_LBU = 6,
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INSN_SB = 7,
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INSN_SB = 7,
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};
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};
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/* Sub opcdoe opcode. */
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/* Sub opcdoe opcode. */
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enum
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enum
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{
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{
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INSN16_LBU = 11,
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INSN16_LBU = 11,
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INSN16_LH = 9,
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INSN16_LH = 9,
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INSN16_LW = 8,
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INSN16_LW = 8,
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INSN16_SB = 15,
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INSN16_SB = 15,
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INSN16_SH = 13,
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INSN16_SH = 13,
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INSN16_SW = 12,
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INSN16_SW = 12,
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};
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};
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enum
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enum
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{
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{
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LDST_NOUPDATE = 0,
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LDST_NOUPDATE = 0,
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LDST_PRE = 1,
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LDST_PRE = 1,
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LDST_POST = 2,
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LDST_POST = 2,
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};
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};
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enum score_insn_type
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enum score_insn_type
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{
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{
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Rd_I4,
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Rd_I4,
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Rd_I5,
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Rd_I5,
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Rd_rvalueBP_I5,
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Rd_rvalueBP_I5,
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Rd_lvalueBP_I5,
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Rd_lvalueBP_I5,
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Rd_Rs_I5,
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Rd_Rs_I5,
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x_Rs_I5,
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x_Rs_I5,
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x_I5_x,
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x_I5_x,
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Rd_I8,
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Rd_I8,
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Rd_Rs_I14,
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Rd_Rs_I14,
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I15,
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I15,
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Rd_I16,
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Rd_I16,
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Rd_I30,
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Rd_I30,
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Rd_I32,
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Rd_I32,
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Rd_rvalueRs_SI10,
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Rd_rvalueRs_SI10,
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Rd_lvalueRs_SI10,
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Rd_lvalueRs_SI10,
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Rd_rvalueRs_preSI12,
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Rd_rvalueRs_preSI12,
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Rd_rvalueRs_postSI12,
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Rd_rvalueRs_postSI12,
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Rd_lvalueRs_preSI12,
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Rd_lvalueRs_preSI12,
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Rd_lvalueRs_postSI12,
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Rd_lvalueRs_postSI12,
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Rd_Rs_SI14,
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Rd_Rs_SI14,
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Rd_rvalueRs_SI15,
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Rd_rvalueRs_SI15,
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Rd_lvalueRs_SI15,
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Rd_lvalueRs_SI15,
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Rd_SI5,
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Rd_SI5,
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Rd_SI6,
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Rd_SI6,
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Rd_SI16,
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Rd_SI16,
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PC_DISP8div2,
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PC_DISP8div2,
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PC_DISP11div2,
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PC_DISP11div2,
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PC_DISP19div2,
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PC_DISP19div2,
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PC_DISP24div2,
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PC_DISP24div2,
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Rd_Rs_Rs,
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Rd_Rs_Rs,
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x_Rs_x,
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x_Rs_x,
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x_Rs_Rs,
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x_Rs_Rs,
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Rd_Rs_x,
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Rd_Rs_x,
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Rd_x_Rs,
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Rd_x_Rs,
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Rd_x_x,
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Rd_x_x,
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Rd_Rs,
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Rd_Rs,
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Rd_HighRs,
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Rd_HighRs,
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Rd_lvalueRs,
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Rd_lvalueRs,
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Rd_rvalueRs,
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Rd_rvalueRs,
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Rd_lvalue32Rs,
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Rd_lvalue32Rs,
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Rd_rvalue32Rs,
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Rd_rvalue32Rs,
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x_Rs,
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x_Rs,
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NO_OPD,
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NO_OPD,
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NO16_OPD,
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NO16_OPD,
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OP5_rvalueRs_SI15,
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OP5_rvalueRs_SI15,
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I5_Rs_Rs_I5_OP5,
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I5_Rs_Rs_I5_OP5,
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x_rvalueRs_post4,
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x_rvalueRs_post4,
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Rd_rvalueRs_post4,
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Rd_rvalueRs_post4,
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Rd_x_I5,
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Rd_x_I5,
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Rd_lvalueRs_post4,
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Rd_lvalueRs_post4,
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x_lvalueRs_post4,
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x_lvalueRs_post4,
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Rd_LowRs,
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Rd_LowRs,
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Rd_Rs_Rs_imm,
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Rd_Rs_Rs_imm,
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Insn_Type_PCE,
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Insn_Type_PCE,
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Insn_Type_SYN,
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Insn_Type_SYN,
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Insn_GP,
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Insn_GP,
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Insn_PIC,
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Insn_PIC,
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Insn_internal,
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Insn_internal,
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Insn_BCMP,
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Insn_BCMP,
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Ra_I9_I5,
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Ra_I9_I5,
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};
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};
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enum score_data_type
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enum score_data_type
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{
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{
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_IMM4 = 0,
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_IMM4 = 0,
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_IMM5,
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_IMM5,
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_IMM8,
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_IMM8,
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_IMM14,
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_IMM14,
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_IMM15,
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_IMM15,
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_IMM16,
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_IMM16,
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_SIMM10 = 6,
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_SIMM10 = 6,
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_SIMM12,
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_SIMM12,
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_SIMM14,
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_SIMM14,
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_SIMM15,
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_SIMM15,
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_SIMM16,
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_SIMM16,
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_SIMM14_NEG = 11,
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_SIMM14_NEG = 11,
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_IMM16_NEG,
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_IMM16_NEG,
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_SIMM16_NEG,
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_SIMM16_NEG,
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_IMM20,
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_IMM20,
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_IMM25,
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_IMM25,
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_DISP8div2 = 16,
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_DISP8div2 = 16,
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_DISP11div2,
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_DISP11div2,
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_DISP19div2,
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_DISP19div2,
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_DISP24div2,
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_DISP24div2,
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_VALUE,
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_VALUE,
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_VALUE_HI16,
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_VALUE_HI16,
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_VALUE_LO16,
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_VALUE_LO16,
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_VALUE_LDST_LO16 = 23,
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_VALUE_LDST_LO16 = 23,
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_SIMM16_LA,
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_SIMM16_LA,
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_IMM5_RSHIFT_1,
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_IMM5_RSHIFT_1,
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_IMM5_RSHIFT_2,
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_IMM5_RSHIFT_2,
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_SIMM16_LA_POS,
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_SIMM16_LA_POS,
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_IMM5_RANGE_8_31,
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_IMM5_RANGE_8_31,
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_IMM10_RSHIFT_2,
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_IMM10_RSHIFT_2,
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_GP_IMM15 = 30,
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_GP_IMM15 = 30,
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_GP_IMM14 = 31,
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_GP_IMM14 = 31,
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_SIMM16_pic = 42, /* Index in score_df_range. */
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_SIMM16_pic = 42, /* Index in score_df_range. */
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_IMM16_LO16_pic = 43,
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_IMM16_LO16_pic = 43,
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_IMM16_pic = 44,
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_IMM16_pic = 44,
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_SIMM5 = 45,
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_SIMM5 = 45,
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_SIMM6 = 46,
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_SIMM6 = 46,
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_IMM32 = 47,
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_IMM32 = 47,
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_SIMM32 = 48,
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_SIMM32 = 48,
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_IMM11 = 49,
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_IMM11 = 49,
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_IMM5_MULTI_LOAD = 50,
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_IMM5_MULTI_LOAD = 50,
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};
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};
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#define REG_TMP 1
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#define REG_TMP 1
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#define OP_REG_TYPE (1 << 6)
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#define OP_REG_TYPE (1 << 6)
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#define OP_IMM_TYPE (1 << 7)
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#define OP_IMM_TYPE (1 << 7)
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#define OP_SH_REGD (OP_REG_TYPE |20)
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#define OP_SH_REGD (OP_REG_TYPE |20)
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#define OP_SH_REGS1 (OP_REG_TYPE |15)
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#define OP_SH_REGS1 (OP_REG_TYPE |15)
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#define OP_SH_REGS2 (OP_REG_TYPE |10)
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#define OP_SH_REGS2 (OP_REG_TYPE |10)
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#define OP_SH_I (OP_IMM_TYPE | 1)
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#define OP_SH_I (OP_IMM_TYPE | 1)
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#define OP_SH_RI15 (OP_IMM_TYPE | 0)
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#define OP_SH_RI15 (OP_IMM_TYPE | 0)
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#define OP_SH_I12 (OP_IMM_TYPE | 3)
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#define OP_SH_I12 (OP_IMM_TYPE | 3)
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#define OP_SH_DISP24 (OP_IMM_TYPE | 1)
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#define OP_SH_DISP24 (OP_IMM_TYPE | 1)
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#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15)
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#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15)
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#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1)
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#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1)
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#define OP_SH_I5 (OP_IMM_TYPE |10)
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#define OP_SH_I5 (OP_IMM_TYPE |10)
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#define OP_SH_I10 (OP_IMM_TYPE | 5)
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#define OP_SH_I10 (OP_IMM_TYPE | 5)
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#define OP_SH_COPID (OP_IMM_TYPE | 5)
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#define OP_SH_COPID (OP_IMM_TYPE | 5)
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#define OP_SH_TRAPI5 (OP_IMM_TYPE |15)
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#define OP_SH_TRAPI5 (OP_IMM_TYPE |15)
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#define OP_SH_I15 (OP_IMM_TYPE |10)
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#define OP_SH_I15 (OP_IMM_TYPE |10)
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#define OP16_SH_REGD (OP_REG_TYPE | 8)
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#define OP16_SH_REGD (OP_REG_TYPE | 8)
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#define OP16_SH_REGS1 (OP_REG_TYPE | 4)
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#define OP16_SH_REGS1 (OP_REG_TYPE | 4)
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#define OP16_SH_I45 (OP_IMM_TYPE | 3)
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#define OP16_SH_I45 (OP_IMM_TYPE | 3)
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#define OP16_SH_I8 (OP_IMM_TYPE | 0)
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#define OP16_SH_I8 (OP_IMM_TYPE | 0)
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#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
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#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
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#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
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#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
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enum insn_class
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enum insn_class
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{
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{
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INSN_CLASS_16,
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INSN_CLASS_16,
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INSN_CLASS_32,
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INSN_CLASS_32,
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INSN_CLASS_48,
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INSN_CLASS_48,
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INSN_CLASS_PCE,
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INSN_CLASS_PCE,
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INSN_CLASS_SYN
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INSN_CLASS_SYN
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};
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};
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/* s3_s7: Globals for both tc-score.c and elf32-score.c. */
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/* s3_s7: Globals for both tc-score.c and elf32-score.c. */
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extern int score3;
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extern int score3;
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extern int score7;
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extern int score7;
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#endif
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#endif
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