/* Table of opcodes for the Texas Instruments TMS320C54X
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/* Table of opcodes for the Texas Instruments TMS320C54X
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Copyright 1999, 2000, 2001, 2005, 2007, 2009 Free Software Foundation, Inc.
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Copyright 1999, 2000, 2001, 2005, 2007, 2009 Free Software Foundation, Inc.
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Contributed by Timothy Wall (twall@cygnus.com)
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Contributed by Timothy Wall (twall@cygnus.com)
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This file is part of the GNU opcodes library.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "dis-asm.h"
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#include "opcode/tic54x.h"
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#include "opcode/tic54x.h"
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/* these are the only register names not found in mmregs */
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/* these are the only register names not found in mmregs */
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const symbol regs[] = {
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const symbol regs[] = {
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{ "AR0", 16 }, { "ar0", 16 },
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{ "AR0", 16 }, { "ar0", 16 },
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{ "AR1", 17 }, { "ar1", 17 },
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{ "AR1", 17 }, { "ar1", 17 },
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{ "AR2", 18 }, { "ar2", 18 },
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{ "AR2", 18 }, { "ar2", 18 },
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{ "AR3", 19 }, { "ar3", 19 },
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{ "AR3", 19 }, { "ar3", 19 },
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{ "AR4", 20 }, { "ar4", 20 },
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{ "AR4", 20 }, { "ar4", 20 },
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{ "AR5", 21 }, { "ar5", 21 },
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{ "AR5", 21 }, { "ar5", 21 },
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{ "AR6", 22 }, { "ar6", 22 },
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{ "AR6", 22 }, { "ar6", 22 },
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{ "AR7", 23 }, { "ar7", 23 },
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{ "AR7", 23 }, { "ar7", 23 },
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{ NULL, 0}
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{ NULL, 0}
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};
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};
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/* status bits, MM registers, condition codes, etc */
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/* status bits, MM registers, condition codes, etc */
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/* some symbols are only valid for certain chips... */
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/* some symbols are only valid for certain chips... */
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const symbol mmregs[] = {
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const symbol mmregs[] = {
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{ "IMR", 0 }, { "imr", 0 },
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{ "IMR", 0 }, { "imr", 0 },
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{ "IFR", 1 }, { "ifr", 1 },
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{ "IFR", 1 }, { "ifr", 1 },
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{ "ST0", 6 }, { "st0", 6 },
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{ "ST0", 6 }, { "st0", 6 },
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{ "ST1", 7 }, { "st1", 7 },
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{ "ST1", 7 }, { "st1", 7 },
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{ "AL", 8 }, { "al", 8 },
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{ "AL", 8 }, { "al", 8 },
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{ "AH", 9 }, { "ah", 9 },
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{ "AH", 9 }, { "ah", 9 },
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{ "AG", 10 }, { "ag", 10 },
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{ "AG", 10 }, { "ag", 10 },
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{ "BL", 11 }, { "bl", 11 },
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{ "BL", 11 }, { "bl", 11 },
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{ "BH", 12 }, { "bh", 12 },
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{ "BH", 12 }, { "bh", 12 },
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{ "BG", 13 }, { "bg", 13 },
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{ "BG", 13 }, { "bg", 13 },
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{ "T", 14 }, { "t", 14 },
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{ "T", 14 }, { "t", 14 },
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{ "TRN", 15 }, { "trn", 15 },
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{ "TRN", 15 }, { "trn", 15 },
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{ "AR0", 16 }, { "ar0", 16 },
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{ "AR0", 16 }, { "ar0", 16 },
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{ "AR1", 17 }, { "ar1", 17 },
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{ "AR1", 17 }, { "ar1", 17 },
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{ "AR2", 18 }, { "ar2", 18 },
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{ "AR2", 18 }, { "ar2", 18 },
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{ "AR3", 19 }, { "ar3", 19 },
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{ "AR3", 19 }, { "ar3", 19 },
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{ "AR4", 20 }, { "ar4", 20 },
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{ "AR4", 20 }, { "ar4", 20 },
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{ "AR5", 21 }, { "ar5", 21 },
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{ "AR5", 21 }, { "ar5", 21 },
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{ "AR6", 22 }, { "ar6", 22 },
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{ "AR6", 22 }, { "ar6", 22 },
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{ "AR7", 23 }, { "ar7", 23 },
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{ "AR7", 23 }, { "ar7", 23 },
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{ "SP", 24 }, { "sp", 24 },
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{ "SP", 24 }, { "sp", 24 },
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{ "BK", 25 }, { "bk", 25 },
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{ "BK", 25 }, { "bk", 25 },
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{ "BRC", 26 }, { "brc", 26 },
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{ "BRC", 26 }, { "brc", 26 },
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{ "RSA", 27 }, { "rsa", 27 },
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{ "RSA", 27 }, { "rsa", 27 },
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{ "REA", 28 }, { "rea", 28 },
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{ "REA", 28 }, { "rea", 28 },
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{ "PMST",29 }, { "pmst",29 },
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{ "PMST",29 }, { "pmst",29 },
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{ "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */
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{ "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */
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/* optional peripherals */ /* optional peripherals */
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/* optional peripherals */ /* optional peripherals */
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{ "M1F", 31 }, { "m1f", 31 },
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{ "M1F", 31 }, { "m1f", 31 },
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{ "DRR0",0x20 }, { "drr0",0x20 },
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{ "DRR0",0x20 }, { "drr0",0x20 },
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{ "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */
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{ "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */
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{ "DXR0",0x21 }, { "dxr0",0x21 },
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{ "DXR0",0x21 }, { "dxr0",0x21 },
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{ "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */
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{ "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */
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{ "SPC0",0x22 }, { "spc0",0x22 },
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{ "SPC0",0x22 }, { "spc0",0x22 },
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{ "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */
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{ "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */
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{ "SPCE0",0x23 }, { "spce0",0x23 },
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{ "SPCE0",0x23 }, { "spce0",0x23 },
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{ "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */
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{ "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */
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{ "TIM", 0x24 }, { "tim", 0x24 },
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{ "TIM", 0x24 }, { "tim", 0x24 },
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{ "PRD", 0x25 }, { "prd", 0x25 },
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{ "PRD", 0x25 }, { "prd", 0x25 },
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{ "TCR", 0x26 }, { "tcr", 0x26 },
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{ "TCR", 0x26 }, { "tcr", 0x26 },
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{ "SWWSR",0x28 }, { "swwsr",0x28 },
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{ "SWWSR",0x28 }, { "swwsr",0x28 },
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{ "BSCR",0x29 }, { "bscr",0x29 },
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{ "BSCR",0x29 }, { "bscr",0x29 },
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{ "HPIC",0x2C }, { "hpic",0x2c },
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{ "HPIC",0x2C }, { "hpic",0x2c },
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/* 'c541, 'c545 */ /* 'c541, 'c545 */
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/* 'c541, 'c545 */ /* 'c541, 'c545 */
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{ "DRR1",0x30 }, { "drr1",0x30 },
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{ "DRR1",0x30 }, { "drr1",0x30 },
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{ "DXR1",0x31 }, { "dxr1",0x31 },
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{ "DXR1",0x31 }, { "dxr1",0x31 },
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{ "SPC1",0x32 }, { "spc1",0x32 },
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{ "SPC1",0x32 }, { "spc1",0x32 },
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/* 'c542, 'c543 */ /* 'c542, 'c543 */
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/* 'c542, 'c543 */ /* 'c542, 'c543 */
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{ "TRCV",0x30 }, { "trcv",0x30 },
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{ "TRCV",0x30 }, { "trcv",0x30 },
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{ "TDXR",0x31 }, { "tdxr",0x31 },
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{ "TDXR",0x31 }, { "tdxr",0x31 },
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{ "TSPC",0x32 }, { "tspc",0x32 },
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{ "TSPC",0x32 }, { "tspc",0x32 },
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{ "TCSR",0x33 }, { "tcsr",0x33 },
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{ "TCSR",0x33 }, { "tcsr",0x33 },
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{ "TRTA",0x34 }, { "trta",0x34 },
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{ "TRTA",0x34 }, { "trta",0x34 },
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{ "TRAD",0x35 }, { "trad",0x35 },
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{ "TRAD",0x35 }, { "trad",0x35 },
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{ "AXR0",0x38 }, { "axr0",0x38 },
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{ "AXR0",0x38 }, { "axr0",0x38 },
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{ "BKX0",0x39 }, { "bkx0",0x39 },
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{ "BKX0",0x39 }, { "bkx0",0x39 },
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{ "ARR0",0x3A }, { "arr0",0x3a },
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{ "ARR0",0x3A }, { "arr0",0x3a },
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{ "BKR0",0x3B }, { "bkr0",0x3b },
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{ "BKR0",0x3B }, { "bkr0",0x3b },
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/* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */
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/* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */
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{ "CLKMD",0x58 }, { "clkmd",0x58 },
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{ "CLKMD",0x58 }, { "clkmd",0x58 },
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/* 'c548 */ /* 'c548 */
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/* 'c548 */ /* 'c548 */
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{ "AXR1",0x3C }, { "axr1",0x3c },
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{ "AXR1",0x3C }, { "axr1",0x3c },
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{ "BKX1",0x3D }, { "bkx1",0x3d },
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{ "BKX1",0x3D }, { "bkx1",0x3d },
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{ "ARR1",0x3E }, { "arr1",0x3e },
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{ "ARR1",0x3E }, { "arr1",0x3e },
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{ "BKR1",0x3F }, { "bkr1",0x3f },
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{ "BKR1",0x3F }, { "bkr1",0x3f },
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{ "BDRR1",0x40 }, { "bdrr1",0x40 },
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{ "BDRR1",0x40 }, { "bdrr1",0x40 },
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{ "BDXR1",0x41 }, { "bdxr1",0x41 },
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{ "BDXR1",0x41 }, { "bdxr1",0x41 },
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{ "BSPC1",0x42 }, { "bspc1",0x42 },
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{ "BSPC1",0x42 }, { "bspc1",0x42 },
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{ "BSPCE1",0x43 }, { "bspce1",0x43 },
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{ "BSPCE1",0x43 }, { "bspce1",0x43 },
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{ NULL, 0},
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{ NULL, 0},
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};
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};
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const symbol condition_codes[] = {
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const symbol condition_codes[] = {
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/* condition codes */
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/* condition codes */
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{ "UNC", 0 }, { "unc", 0 },
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{ "UNC", 0 }, { "unc", 0 },
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#define CC1 0x40
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#define CC1 0x40
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#define CCB 0x08
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#define CCB 0x08
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#define CCEQ 0x05
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#define CCEQ 0x05
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#define CCNEQ 0x04
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#define CCNEQ 0x04
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#define CCLT 0x03
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#define CCLT 0x03
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#define CCLEQ 0x07
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#define CCLEQ 0x07
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#define CCGT 0x06
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#define CCGT 0x06
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#define CCGEQ 0x02
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#define CCGEQ 0x02
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#define CCOV 0x70
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#define CCOV 0x70
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#define CCNOV 0x60
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#define CCNOV 0x60
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#define CCBIO 0x03
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#define CCBIO 0x03
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#define CCNBIO 0x02
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#define CCNBIO 0x02
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#define CCTC 0x30
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#define CCTC 0x30
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#define CCNTC 0x20
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#define CCNTC 0x20
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#define CCC 0x0C
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#define CCC 0x0C
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#define CCNC 0x08
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#define CCNC 0x08
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{ "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ },
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{ "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ },
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{ "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ },
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{ "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ },
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{ "alt", CC1|CCLT }, { "ALT", CC1|CCLT },
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{ "alt", CC1|CCLT }, { "ALT", CC1|CCLT },
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{ "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ },
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{ "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ },
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{ "agt", CC1|CCGT }, { "AGT", CC1|CCGT },
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{ "agt", CC1|CCGT }, { "AGT", CC1|CCGT },
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{ "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ },
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{ "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ },
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{ "aov", CC1|CCOV }, { "AOV", CC1|CCOV },
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{ "aov", CC1|CCOV }, { "AOV", CC1|CCOV },
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{ "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV },
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{ "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV },
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{ "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ },
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{ "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ },
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{ "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ },
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{ "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ },
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{ "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT },
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{ "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT },
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{ "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ },
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{ "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ },
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{ "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT },
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{ "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT },
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{ "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ },
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{ "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ },
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{ "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV },
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{ "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV },
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{ "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV },
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{ "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV },
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{ "tc", CCTC }, { "TC", CCTC },
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{ "tc", CCTC }, { "TC", CCTC },
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{ "ntc", CCNTC }, { "NTC", CCNTC },
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{ "ntc", CCNTC }, { "NTC", CCNTC },
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{ "c", CCC }, { "C", CCC },
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{ "c", CCC }, { "C", CCC },
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{ "nc", CCNC }, { "NC", CCNC },
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{ "nc", CCNC }, { "NC", CCNC },
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{ "bio", CCBIO }, { "BIO", CCBIO },
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{ "bio", CCBIO }, { "BIO", CCBIO },
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{ "nbio", CCNBIO }, { "NBIO", CCNBIO },
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{ "nbio", CCNBIO }, { "NBIO", CCNBIO },
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{ NULL, 0 }
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{ NULL, 0 }
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};
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};
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const symbol cc2_codes[] = {
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const symbol cc2_codes[] = {
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{ "UNC", 0 }, { "unc", 0 },
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{ "UNC", 0 }, { "unc", 0 },
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{ "AEQ", 5 }, { "aeq", 5 },
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{ "AEQ", 5 }, { "aeq", 5 },
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{ "ANEQ", 4 }, { "aneq", 4 },
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{ "ANEQ", 4 }, { "aneq", 4 },
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{ "AGT", 6 }, { "agt", 6 },
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{ "AGT", 6 }, { "agt", 6 },
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{ "ALT", 3 }, { "alt", 3 },
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{ "ALT", 3 }, { "alt", 3 },
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{ "ALEQ", 7 }, { "aleq", 7 },
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{ "ALEQ", 7 }, { "aleq", 7 },
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{ "AGEQ", 2 }, { "ageq", 2 },
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{ "AGEQ", 2 }, { "ageq", 2 },
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{ "BEQ", 13 }, { "beq", 13 },
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{ "BEQ", 13 }, { "beq", 13 },
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{ "BNEQ", 12 },{ "bneq", 12 },
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{ "BNEQ", 12 },{ "bneq", 12 },
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{ "BGT", 14 }, { "bgt", 14 },
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{ "BGT", 14 }, { "bgt", 14 },
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{ "BLT", 11 }, { "blt", 11 },
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{ "BLT", 11 }, { "blt", 11 },
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{ "BLEQ", 15 },{ "bleq", 15 },
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{ "BLEQ", 15 },{ "bleq", 15 },
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{ "BGEQ", 10 },{ "bgeq", 10 },
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{ "BGEQ", 10 },{ "bgeq", 10 },
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{ NULL, 0 },
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{ NULL, 0 },
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};
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};
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const symbol cc3_codes[] = {
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const symbol cc3_codes[] = {
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{ "EQ", 0x0000 }, { "eq", 0x0000 },
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{ "EQ", 0x0000 }, { "eq", 0x0000 },
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{ "LT", 0x0100 }, { "lt", 0x0100 },
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{ "LT", 0x0100 }, { "lt", 0x0100 },
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{ "GT", 0x0200 }, { "gt", 0x0200 },
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{ "GT", 0x0200 }, { "gt", 0x0200 },
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{ "NEQ", 0x0300 }, { "neq", 0x0300 },
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{ "NEQ", 0x0300 }, { "neq", 0x0300 },
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{ "0", 0x0000 },
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{ "0", 0x0000 },
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{ "1", 0x0100 },
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{ "1", 0x0100 },
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{ "2", 0x0200 },
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{ "2", 0x0200 },
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{ "3", 0x0300 },
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{ "3", 0x0300 },
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{ "00", 0x0000 },
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{ "00", 0x0000 },
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{ "01", 0x0100 },
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{ "01", 0x0100 },
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{ "10", 0x0200 },
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{ "10", 0x0200 },
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{ "11", 0x0300 },
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{ "11", 0x0300 },
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{ NULL, 0 },
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{ NULL, 0 },
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};
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};
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/* FIXME -- also allow decimal digits */
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/* FIXME -- also allow decimal digits */
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const symbol status_bits[] = {
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const symbol status_bits[] = {
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/* status register 0 */
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/* status register 0 */
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{ "TC", 12 }, { "tc", 12 },
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{ "TC", 12 }, { "tc", 12 },
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{ "C", 11 }, { "c", 11 },
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{ "C", 11 }, { "c", 11 },
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{ "OVA", 10 }, { "ova", 10 },
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{ "OVA", 10 }, { "ova", 10 },
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{ "OVB", 9 }, { "ovb", 9 },
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{ "OVB", 9 }, { "ovb", 9 },
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/* status register 1 */
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/* status register 1 */
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{ "BRAF",15 }, { "braf",15 },
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{ "BRAF",15 }, { "braf",15 },
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{ "CPL", 14 }, { "cpl", 14 },
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{ "CPL", 14 }, { "cpl", 14 },
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{ "XF", 13 }, { "xf", 13 },
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{ "XF", 13 }, { "xf", 13 },
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{ "HM", 12 }, { "hm", 12 },
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{ "HM", 12 }, { "hm", 12 },
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{ "INTM",11 }, { "intm",11 },
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{ "INTM",11 }, { "intm",11 },
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{ "OVM", 9 }, { "ovm", 9 },
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{ "OVM", 9 }, { "ovm", 9 },
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{ "SXM", 8 }, { "sxm", 8 },
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{ "SXM", 8 }, { "sxm", 8 },
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{ "C16", 7 }, { "c16", 7 },
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{ "C16", 7 }, { "c16", 7 },
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{ "FRCT", 6 }, { "frct", 6 },
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{ "FRCT", 6 }, { "frct", 6 },
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{ "CMPT", 5 }, { "cmpt", 5 },
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{ "CMPT", 5 }, { "cmpt", 5 },
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{ NULL, 0 },
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{ NULL, 0 },
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};
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};
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const char *misc_symbols[] = {
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const char *misc_symbols[] = {
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"ARP", "arp",
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"ARP", "arp",
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"DP", "dp",
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"DP", "dp",
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"ASM", "asm",
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"ASM", "asm",
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"TS", "ts",
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"TS", "ts",
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NULL
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NULL
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};
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};
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/* Due to the way instructions are hashed and scanned in
|
/* Due to the way instructions are hashed and scanned in
|
gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively
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gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively
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placed
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placed
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Items marked with "PREFER" have been moved prior to a more costly
|
Items marked with "PREFER" have been moved prior to a more costly
|
instruction with a similar operand format.
|
instruction with a similar operand format.
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|
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Mnemonics which can take either a predefined symbol or a memory reference
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Mnemonics which can take either a predefined symbol or a memory reference
|
as an argument are arranged so that the more restrictive (predefined
|
as an argument are arranged so that the more restrictive (predefined
|
symbol) version is checked first (marked "SRC").
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symbol) version is checked first (marked "SRC").
|
*/
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*/
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#define ZPAR 0,{OP_None}
|
#define ZPAR 0,{OP_None}
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#define REST 0,0,ZPAR
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#define REST 0,0,ZPAR
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#define XREST ZPAR
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#define XREST ZPAR
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const insn_template tic54x_unknown_opcode =
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const insn_template tic54x_unknown_opcode =
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{ "???", 1,0,0,0x0000, 0x0000, {0}, 0, REST};
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{ "???", 1,0,0,0x0000, 0x0000, {0}, 0, REST};
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const insn_template tic54x_optab[] = {
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const insn_template tic54x_optab[] = {
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/* these must precede bc/bcd, cc/ccd to avoid misinterpretation */
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/* these must precede bc/bcd, cc/ccd to avoid misinterpretation */
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{ "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
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{ "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
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{ "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
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{ "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
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{ "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
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|
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{ "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
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{ "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
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{ "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
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{ "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
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{ "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
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{ "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
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{ "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
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{ "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
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{ "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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{ "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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{ "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
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{ "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
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{ "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
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{ "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
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{ "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/
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{ "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/
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{ "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
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{ "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
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FL_EXT|FL_SMR, 0x0C00, 0xFCE0, XREST},
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FL_EXT|FL_SMR, 0x0C00, 0xFCE0, XREST},
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{ "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
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{ "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
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{ "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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{ "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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{ "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
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{ "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
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{ "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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{ "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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{ "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},
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{ "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},
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{ "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST },
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{ "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST },
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{ "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, REST},
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{ "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, REST},
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{ "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
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{ "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
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{ "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
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{ "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
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{ "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
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{ "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
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{ "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
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{ "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
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{ "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, REST},
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{ "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, REST},
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{ "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, REST},
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{ "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, REST},
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{ "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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{ "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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B_BRANCH|FL_NR, REST},
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B_BRANCH|FL_NR, REST},
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{ "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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{ "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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B_BRANCH|FL_DELAY|FL_NR, REST},
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B_BRANCH|FL_DELAY|FL_NR, REST},
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{ "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, REST},
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{ "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, REST},
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{ "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
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{ "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
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{ "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, REST},
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{ "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, REST},
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{ "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
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{ "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
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{ "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
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{ "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
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{ "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
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{ "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
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{ "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
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{ "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
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{ "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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{ "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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B_BRANCH|FL_NR, REST},
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B_BRANCH|FL_NR, REST},
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{ "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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{ "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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B_BRANCH|FL_DELAY|FL_NR, REST},
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B_BRANCH|FL_DELAY|FL_NR, REST},
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{ "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
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{ "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
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{ "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
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{ "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
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{ "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, REST},
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{ "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, REST},
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{ "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
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{ "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
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{ "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, REST},
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{ "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
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{ "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
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{ "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, REST},
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{ "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, REST},
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{ "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
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{ "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
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{ "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
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{ "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
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{ "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
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{ "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
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{ "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST},
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{ "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST},
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{ "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
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{ "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
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{ "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
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{ "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
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{ "estop", 1,0,0,0xF4F0, 0xFFFF, {OP_None}, 0, REST}, /* undocumented */
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{ "estop", 1,0,0,0xF4F0, 0xFFFF, {OP_None}, 0, REST}, /* undocumented */
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{ "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST},
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{ "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST},
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{ "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
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{ "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
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{ "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
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{ "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
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{ "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, REST},
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{ "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, REST},
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{ "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, REST},
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{ "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, REST},
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{ "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
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{ "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
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{ "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
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{ "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
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{ "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
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{ "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, REST},
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{ "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, REST},
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{ "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
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{ "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
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{ "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
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{ "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
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{ "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, REST},/*SRC*/
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{ "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, REST},/*SRC*/
|
/* alternate syntax */
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/* alternate syntax */
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{ "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
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{ "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
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{ "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, REST},/*SRC*/
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{ "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, REST},/*SRC*/
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{ "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, REST},/*SRC*/
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{ "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, REST},/*SRC*/
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{ "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, REST},/*SRC*/
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{ "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, REST},/*SRC*/
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{ "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, REST},/*PREFER */
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{ "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, REST},/*PREFER */
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{ "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, REST},/*SRC*/
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{ "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, REST},/*SRC*/
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{ "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, REST},/*SRC*/
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{ "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, REST},/*SRC*/
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{ "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, REST},/*SRC*/
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{ "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, REST},/*SRC*/
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{ "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
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{ "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
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{ "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, REST},
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{ "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, REST},
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{ "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, REST},
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{ "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, REST},
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{ "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, REST},/*PREFER*/
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{ "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, REST},/*PREFER*/
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{ "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST},
|
{ "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST},
|
FL_EXT|FL_SMR, 0x0C40, 0xFEE0, XREST},
|
FL_EXT|FL_SMR, 0x0C40, 0xFEE0, XREST},
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{ "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, REST},
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{ "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, REST},
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{ "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, REST},
|
{ "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, REST},
|
{ "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, REST},
|
{ "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, REST},
|
{ "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, REST},/*pseudo-op*/
|
{ "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, REST},/*pseudo-op*/
|
{ "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
|
{ "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
|
{ "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
|
{ "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
|
{ "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, REST},
|
{ "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, REST},
|
{ "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
|
{ "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
|
{ "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
|
{ "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
|
{ "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
|
{ "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
|
{ "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
|
{ "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
|
{ "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
|
{ "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
|
{ "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
|
{ "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
|
{ "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST},
|
{ "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST},
|
{ "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, REST},
|
{ "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, REST},
|
{ "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
|
{ "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
|
{ "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, REST},
|
{ "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, REST},
|
{ "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, REST},
|
{ "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, REST},
|
{ "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
|
{ "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
|
{ "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, REST},
|
{ "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, REST},
|
{ "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, REST},
|
{ "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, REST},
|
{ "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, REST}, /*SRC*/
|
{ "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, REST}, /*SRC*/
|
{ "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
|
{ "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
|
{ "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, REST},
|
{ "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, REST},
|
{ "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, REST},
|
{ "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, REST},
|
{ "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, REST},
|
{ "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, REST},
|
{ "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, REST},
|
{ "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, REST},
|
{ "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, REST},
|
{ "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, REST},
|
{ "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, REST},
|
{ "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, REST},
|
{ "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, REST},
|
{ "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, REST},
|
{ "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, REST},
|
{ "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, REST},
|
{ "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
|
{ "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
|
{ "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, REST},
|
{ "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, REST},
|
{ "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, REST},
|
{ "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, REST},
|
{ "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, REST},
|
{ "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, REST},
|
{ "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, REST},
|
{ "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, REST},
|
{ "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, REST},
|
{ "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, REST},
|
{ "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
|
{ "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
|
{ "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
|
{ "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
|
{ "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
|
{ "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
|
B_RET|FL_NR, REST},
|
B_RET|FL_NR, REST},
|
{ "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
|
{ "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
|
B_RET|FL_DELAY|FL_NR, REST},
|
B_RET|FL_DELAY|FL_NR, REST},
|
{ "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, REST},
|
{ "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, REST},
|
{ "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, REST},
|
{ "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, REST},
|
{ "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
|
{ "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
|
{ "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
|
{ "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
|
{ "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
|
{ "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
|
{ "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
|
{ "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
|
{ "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, REST},
|
{ "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, REST},
|
{ "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, REST},
|
{ "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, REST},
|
{ "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, REST},
|
{ "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, REST},
|
{ "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, REST},
|
{ "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, REST},
|
{ "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, REST},
|
{ "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, REST},
|
{ "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, REST},
|
{ "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, REST},
|
{ "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, REST},
|
{ "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, REST},
|
{ "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
|
{ "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
|
{ "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST},
|
{ "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST},
|
{ "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
|
{ "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
|
{ "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST},
|
{ "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
|
{ "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
|
{ "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
|
{ "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
|
{ "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, REST},/*SRC*/
|
{ "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, REST},/*SRC*/
|
{ "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
{ "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
|
{ "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
|
{ "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
|
{ "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
|
{ "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, REST},
|
{ "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, REST},
|
{ "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, REST},
|
{ "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, REST},
|
{ "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, REST},
|
{ "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, REST},
|
{ "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
|
{ "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
|
{ "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
|
{ "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
|
{ "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
|
{ "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
|
{ "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
|
{ "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
|
FL_EXT, 0x0C60, 0xFEE0, XREST},
|
FL_EXT, 0x0C60, 0xFEE0, XREST},
|
{ "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
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{ "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
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{ "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
|
{ "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
|
{ "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
|
{ "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
|
{ "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
|
{ "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
|
FL_EXT, 0x0C80, 0xFEE0, XREST },
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FL_EXT, 0x0C80, 0xFEE0, XREST },
|
{ "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST},
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{ "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST},
|
{ "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, REST},
|
{ "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, REST},
|
{ "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
|
{ "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
|
{ "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
|
{ "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
|
{ "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
|
{ "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
|
{ "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/
|
{ "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/
|
{ "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
|
{ "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
|
FL_EXT|FL_SMR, 0x0C20, 0xFCE0, XREST},
|
FL_EXT|FL_SMR, 0x0C20, 0xFCE0, XREST},
|
{ "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
|
{ "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
|
{ "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
|
{ "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
|
{ "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
{ "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, REST},
|
{ "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, REST},
|
{ "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
|
{ "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
{ "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
|
{ "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, REST},
|
{ "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, REST},
|
{ NULL, 0,0,0,0,0, {}, 0, REST},
|
{ NULL, 0,0,0,0,0, {}, 0, REST},
|
};
|
};
|
|
|
/* assume all parallel instructions have at least three operands */
|
/* assume all parallel instructions have at least three operands */
|
const insn_template tic54x_paroptab[] = {
|
const insn_template tic54x_paroptab[] = {
|
{ "ld",1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
|
{ "ld",1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
|
"mac", {OP_Ymem,OPT|OP_RND},},
|
"mac", {OP_Ymem,OPT|OP_RND},},
|
{ "ld",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
|
{ "ld",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
|
"macr", {OP_Ymem,OPT|OP_RND},},
|
"macr", {OP_Ymem,OPT|OP_RND},},
|
{ "ld",1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
|
{ "ld",1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
|
"mas", {OP_Ymem,OPT|OP_RND},},
|
"mas", {OP_Ymem,OPT|OP_RND},},
|
{ "ld",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
|
{ "ld",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
|
"masr", {OP_Ymem,OPT|OP_RND},},
|
"masr", {OP_Ymem,OPT|OP_RND},},
|
{ "st",1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
{ "st",1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
"add", {OP_Xmem,OP_DST}, },
|
"add", {OP_Xmem,OP_DST}, },
|
{ "st",1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
{ "st",1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
"ld", {OP_Xmem,OP_DST}, },
|
"ld", {OP_Xmem,OP_DST}, },
|
{ "st",1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
{ "st",1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
"ld", {OP_Xmem,OP_T}, },
|
"ld", {OP_Xmem,OP_T}, },
|
{ "st",1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
{ "st",1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
"mac", {OP_Xmem,OP_DST}, },
|
"mac", {OP_Xmem,OP_DST}, },
|
{ "st",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
{ "st",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
"macr", {OP_Xmem,OP_DST}, },
|
"macr", {OP_Xmem,OP_DST}, },
|
{ "st",1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
{ "st",1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
"mas", {OP_Xmem,OP_DST}, },
|
"mas", {OP_Xmem,OP_DST}, },
|
{ "st",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
{ "st",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
"masr", {OP_Xmem,OP_DST}, },
|
"masr", {OP_Xmem,OP_DST}, },
|
{ "st",1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
{ "st",1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
"mpy", {OP_Xmem,OP_DST}, },
|
"mpy", {OP_Xmem,OP_DST}, },
|
{ "st",1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
{ "st",1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
"sub", {OP_Xmem,OP_DST}, },
|
"sub", {OP_Xmem,OP_DST}, },
|
{ NULL, 0, 0, 0, 0, 0, {0,0,0,0}, 0, REST },
|
{ NULL, 0, 0, 0, 0, 0, {0,0,0,0}, 0, REST },
|
};
|
};
|
|
|
