/* Generic register read/write.
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/* Generic register read/write.
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Copyright (C) 1998, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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Copyright (C) 1998, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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Contributed by Cygnus Solutions.
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This file is part of GDB, the GNU debugger.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "sim-main.h"
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#include "sim-main.h"
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#include "sim-assert.h"
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#include "sim-assert.h"
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/* Generic implementation of sim_fetch_register for simulators using
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/* Generic implementation of sim_fetch_register for simulators using
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CPU_REG_FETCH.
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CPU_REG_FETCH.
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The contents of BUF are in target byte order. */
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The contents of BUF are in target byte order. */
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/* ??? Obviously the interface needs to be extended to handle multiple
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/* ??? Obviously the interface needs to be extended to handle multiple
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cpus. */
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cpus. */
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int
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int
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sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
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sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
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{
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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return (* CPU_REG_FETCH (cpu)) (cpu, rn, buf, length);
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return (* CPU_REG_FETCH (cpu)) (cpu, rn, buf, length);
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}
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}
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/* Generic implementation of sim_store_register for simulators using
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/* Generic implementation of sim_store_register for simulators using
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CPU_REG_STORE.
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CPU_REG_STORE.
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The contents of BUF are in target byte order. */
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The contents of BUF are in target byte order. */
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/* ??? Obviously the interface needs to be extended to handle multiple
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/* ??? Obviously the interface needs to be extended to handle multiple
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cpus. */
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cpus. */
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int
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int
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sim_store_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
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sim_store_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
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{
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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return (* CPU_REG_STORE (cpu)) (cpu, rn, buf, length);
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return (* CPU_REG_STORE (cpu)) (cpu, rn, buf, length);
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}
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}
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