/* Generic simulator run.
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/* Generic simulator run.
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Copyright (C) 1997, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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Copyright (C) 1997, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "sim-main.h"
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#include "sim-main.h"
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#include "sim-assert.h"
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#include "sim-assert.h"
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/* Generic implementation of sim_engine_run that works within the
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/* Generic implementation of sim_engine_run that works within the
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sim_engine setjmp/longjmp framework. */
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sim_engine setjmp/longjmp framework. */
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#define IMEM XCONCAT
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#define IMEM XCONCAT
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void
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void
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sim_engine_run (SIM_DESC sd,
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sim_engine_run (SIM_DESC sd,
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int next_cpu_nr, /* ignore */
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int next_cpu_nr, /* ignore */
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int nr_cpus, /* ignore */
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int nr_cpus, /* ignore */
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int siggnal) /* ignore */
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int siggnal) /* ignore */
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{
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{
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sim_cia cia;
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sim_cia cia;
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sim_cpu *cpu;
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sim_cpu *cpu;
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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cpu = STATE_CPU (sd, 0);
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cpu = STATE_CPU (sd, 0);
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cia = CIA_GET (cpu);
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cia = CIA_GET (cpu);
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while (1)
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while (1)
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{
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{
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instruction_word insn = IMEM32 (cia);
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instruction_word insn = IMEM32 (cia);
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cia = idecode_issue (sd, insn, cia);
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cia = idecode_issue (sd, insn, cia);
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/* process any events */
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/* process any events */
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if (sim_events_tick (sd))
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if (sim_events_tick (sd))
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{
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{
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CIA_SET (cpu, cia);
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CIA_SET (cpu, cia);
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sim_events_process (sd);
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sim_events_process (sd);
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}
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}
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}
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}
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}
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}
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