/* Cache support for the FRV simulator
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/* Cache support for the FRV simulator
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Copyright (C) 1999, 2000, 2003, 2007, 2008, 2009, 2010
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Copyright (C) 1999, 2000, 2003, 2007, 2008, 2009, 2010
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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Contributed by Red Hat.
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Contributed by Red Hat.
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This file is part of the GNU Simulators.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef CACHE_H
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#ifndef CACHE_H
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#define CACHE_H
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#define CACHE_H
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/* A representation of a set-associative cache with LRU replacement,
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/* A representation of a set-associative cache with LRU replacement,
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cache line locking, non-blocking support and multiple read ports. */
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cache line locking, non-blocking support and multiple read ports. */
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/* An enumeration of cache pipeline request kinds. */
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/* An enumeration of cache pipeline request kinds. */
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typedef enum
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typedef enum
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{
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{
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req_load,
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req_load,
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req_store,
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req_store,
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req_invalidate,
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req_invalidate,
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req_flush,
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req_flush,
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req_preload,
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req_preload,
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req_unlock,
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req_unlock,
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req_WAR
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req_WAR
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} FRV_CACHE_REQUEST_KIND;
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} FRV_CACHE_REQUEST_KIND;
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/* The cache pipeline requests. */
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/* The cache pipeline requests. */
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typedef struct {
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typedef struct {
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int preload;
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int preload;
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int lock;
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int lock;
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} FRV_CACHE_WAR_REQUEST;
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} FRV_CACHE_WAR_REQUEST;
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typedef struct {
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typedef struct {
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char *data;
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char *data;
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int length;
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int length;
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} FRV_CACHE_STORE_REQUEST;
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} FRV_CACHE_STORE_REQUEST;
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typedef struct {
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typedef struct {
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int flush;
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int flush;
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int all;
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int all;
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} FRV_CACHE_INVALIDATE_REQUEST;
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} FRV_CACHE_INVALIDATE_REQUEST;
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typedef struct {
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typedef struct {
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int lock;
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int lock;
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int length;
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int length;
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} FRV_CACHE_PRELOAD_REQUEST;
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} FRV_CACHE_PRELOAD_REQUEST;
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/* A cache pipeline request. */
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/* A cache pipeline request. */
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typedef struct frv_cache_request
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typedef struct frv_cache_request
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{
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{
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struct frv_cache_request *next;
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struct frv_cache_request *next;
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struct frv_cache_request *prev;
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struct frv_cache_request *prev;
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FRV_CACHE_REQUEST_KIND kind;
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FRV_CACHE_REQUEST_KIND kind;
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unsigned reqno;
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unsigned reqno;
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unsigned priority;
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unsigned priority;
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SI address;
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SI address;
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union {
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union {
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FRV_CACHE_STORE_REQUEST store;
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FRV_CACHE_STORE_REQUEST store;
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FRV_CACHE_INVALIDATE_REQUEST invalidate;
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FRV_CACHE_INVALIDATE_REQUEST invalidate;
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FRV_CACHE_PRELOAD_REQUEST preload;
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FRV_CACHE_PRELOAD_REQUEST preload;
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FRV_CACHE_WAR_REQUEST WAR;
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FRV_CACHE_WAR_REQUEST WAR;
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} u;
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} u;
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} FRV_CACHE_REQUEST;
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} FRV_CACHE_REQUEST;
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/* The buffer for returning data to the caller. */
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/* The buffer for returning data to the caller. */
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typedef struct {
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typedef struct {
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unsigned reqno;
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unsigned reqno;
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SI address;
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SI address;
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char *data;
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char *data;
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int valid;
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int valid;
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} FRV_CACHE_RETURN_BUFFER;
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} FRV_CACHE_RETURN_BUFFER;
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/* The status of flush requests. */
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/* The status of flush requests. */
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typedef struct {
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typedef struct {
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unsigned reqno;
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unsigned reqno;
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SI address;
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SI address;
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int valid;
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int valid;
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} FRV_CACHE_FLUSH_STATUS;
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} FRV_CACHE_FLUSH_STATUS;
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/* Communicate status of requests to the caller. */
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/* Communicate status of requests to the caller. */
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typedef struct {
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typedef struct {
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FRV_CACHE_FLUSH_STATUS flush;
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FRV_CACHE_FLUSH_STATUS flush;
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FRV_CACHE_RETURN_BUFFER return_buffer;
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FRV_CACHE_RETURN_BUFFER return_buffer;
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} FRV_CACHE_STATUS;
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} FRV_CACHE_STATUS;
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/* A cache pipeline stage. */
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/* A cache pipeline stage. */
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typedef struct {
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typedef struct {
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FRV_CACHE_REQUEST *request;
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FRV_CACHE_REQUEST *request;
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} FRV_CACHE_STAGE;
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} FRV_CACHE_STAGE;
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enum {
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enum {
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FIRST_STAGE,
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FIRST_STAGE,
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A_STAGE = FIRST_STAGE, /* Addressing stage */
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A_STAGE = FIRST_STAGE, /* Addressing stage */
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I_STAGE, /* Interference stage */
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I_STAGE, /* Interference stage */
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LAST_STAGE = I_STAGE,
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LAST_STAGE = I_STAGE,
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FRV_CACHE_STAGES
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FRV_CACHE_STAGES
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};
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};
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/* Representation of the WAR register. */
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/* Representation of the WAR register. */
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typedef struct {
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typedef struct {
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unsigned reqno;
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unsigned reqno;
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unsigned priority;
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unsigned priority;
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SI address;
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SI address;
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int preload;
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int preload;
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int lock;
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int lock;
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int latency;
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int latency;
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int valid;
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int valid;
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} FRV_CACHE_WAR;
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} FRV_CACHE_WAR;
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/* A cache pipeline. */
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/* A cache pipeline. */
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#define NUM_WARS 2
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#define NUM_WARS 2
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typedef struct {
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typedef struct {
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FRV_CACHE_REQUEST *requests;
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FRV_CACHE_REQUEST *requests;
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FRV_CACHE_STAGE stages[FRV_CACHE_STAGES];
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FRV_CACHE_STAGE stages[FRV_CACHE_STAGES];
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FRV_CACHE_WAR WAR[NUM_WARS];
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FRV_CACHE_WAR WAR[NUM_WARS];
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FRV_CACHE_STATUS status;
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FRV_CACHE_STATUS status;
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} FRV_CACHE_PIPELINE;
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} FRV_CACHE_PIPELINE;
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enum {LS, LD, FRV_CACHE_PIPELINES};
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enum {LS, LD, FRV_CACHE_PIPELINES};
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/* Representation of the xARS registers. */
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/* Representation of the xARS registers. */
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typedef struct {
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typedef struct {
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int pipe;
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int pipe;
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unsigned reqno;
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unsigned reqno;
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unsigned priority;
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unsigned priority;
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SI address;
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SI address;
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int preload;
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int preload;
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int lock;
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int lock;
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int valid;
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int valid;
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} FRV_CACHE_ARS;
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} FRV_CACHE_ARS;
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/* A cache tag. */
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/* A cache tag. */
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typedef struct {
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typedef struct {
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USI tag; /* Address tag. */
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USI tag; /* Address tag. */
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int lru; /* Lower values indicates less recently used. */
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int lru; /* Lower values indicates less recently used. */
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char *line; /* Points to storage for line in data_storage. */
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char *line; /* Points to storage for line in data_storage. */
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char dirty; /* line has been written to since last stored? */
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char dirty; /* line has been written to since last stored? */
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char locked; /* line is locked? */
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char locked; /* line is locked? */
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char valid; /* tag is valid? */
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char valid; /* tag is valid? */
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} FRV_CACHE_TAG;
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} FRV_CACHE_TAG;
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/* Cache statistics. */
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/* Cache statistics. */
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typedef struct {
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typedef struct {
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unsigned long accesses; /* number of cache accesses. */
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unsigned long accesses; /* number of cache accesses. */
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unsigned long hits; /* number of cache hits. */
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unsigned long hits; /* number of cache hits. */
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} FRV_CACHE_STATISTICS;
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} FRV_CACHE_STATISTICS;
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/* The cache itself.
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/* The cache itself.
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Notes:
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Notes:
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- line_size must be a power of 2
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- line_size must be a power of 2
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- sets must be a power of 2
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- sets must be a power of 2
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- ways must be a power of 2
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- ways must be a power of 2
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*/
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*/
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typedef struct {
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typedef struct {
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SIM_CPU *cpu;
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SIM_CPU *cpu;
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unsigned configured_ways; /* Number of ways configured in each set. */
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unsigned configured_ways; /* Number of ways configured in each set. */
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unsigned configured_sets; /* Number of sets configured in the cache. */
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unsigned configured_sets; /* Number of sets configured in the cache. */
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unsigned ways; /* Number of ways in each set. */
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unsigned ways; /* Number of ways in each set. */
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unsigned sets; /* Number of sets in the cache. */
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unsigned sets; /* Number of sets in the cache. */
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unsigned line_size; /* Size of each cache line. */
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unsigned line_size; /* Size of each cache line. */
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unsigned memory_latency; /* Latency of main memory in cycles. */
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unsigned memory_latency; /* Latency of main memory in cycles. */
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FRV_CACHE_TAG *tag_storage; /* Storage for tags. */
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FRV_CACHE_TAG *tag_storage; /* Storage for tags. */
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char *data_storage; /* Storage for data (cache lines). */
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char *data_storage; /* Storage for data (cache lines). */
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FRV_CACHE_PIPELINE pipeline[2]; /* Cache pipelines. */
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FRV_CACHE_PIPELINE pipeline[2]; /* Cache pipelines. */
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FRV_CACHE_ARS BARS; /* BARS register. */
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FRV_CACHE_ARS BARS; /* BARS register. */
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FRV_CACHE_ARS NARS; /* BARS register. */
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FRV_CACHE_ARS NARS; /* BARS register. */
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FRV_CACHE_STATISTICS statistics; /* Operation statistics. */
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FRV_CACHE_STATISTICS statistics; /* Operation statistics. */
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} FRV_CACHE;
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} FRV_CACHE;
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/* The tags are stored by ways within sets in order to make computations
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/* The tags are stored by ways within sets in order to make computations
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easier. */
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easier. */
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#define CACHE_TAG(cache, set, way) ( \
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#define CACHE_TAG(cache, set, way) ( \
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& ((cache)->tag_storage[(set) * (cache)->ways + (way)]) \
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& ((cache)->tag_storage[(set) * (cache)->ways + (way)]) \
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)
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)
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/* Compute the address tag corresponding to the given address. */
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/* Compute the address tag corresponding to the given address. */
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#define CACHE_ADDRESS_TAG(cache, address) ( \
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#define CACHE_ADDRESS_TAG(cache, address) ( \
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(address) & ~(((cache)->line_size * (cache)->sets) - 1) \
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(address) & ~(((cache)->line_size * (cache)->sets) - 1) \
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)
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)
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/* Determine the index at which the set containing this tag starts. */
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/* Determine the index at which the set containing this tag starts. */
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#define CACHE_TAG_SET_START(cache, tag) ( \
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#define CACHE_TAG_SET_START(cache, tag) ( \
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((tag) - (cache)->tag_storage) & ~((cache)->ways - 1) \
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((tag) - (cache)->tag_storage) & ~((cache)->ways - 1) \
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)
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)
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/* Determine the number of the set which this cache tag is in. */
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/* Determine the number of the set which this cache tag is in. */
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#define CACHE_TAG_SET_NUMBER(cache, tag) ( \
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#define CACHE_TAG_SET_NUMBER(cache, tag) ( \
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CACHE_TAG_SET_START ((cache), (tag)) / (cache)->ways \
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CACHE_TAG_SET_START ((cache), (tag)) / (cache)->ways \
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)
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)
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#define CACHE_RETURN_DATA(cache, slot, address, mode, N) ( \
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#define CACHE_RETURN_DATA(cache, slot, address, mode, N) ( \
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T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \
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T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \
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[((address) & ((cache)->line_size - 1))])) \
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[((address) & ((cache)->line_size - 1))])) \
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)
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)
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#define CACHE_RETURN_DATA_ADDRESS(cache, slot, address, N) ( \
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#define CACHE_RETURN_DATA_ADDRESS(cache, slot, address, N) ( \
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((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address) \
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((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address) \
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& ((cache)->line_size - 1)]) \
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& ((cache)->line_size - 1)]) \
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)
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)
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#define DATA_CROSSES_CACHE_LINE(cache, address, size) ( \
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#define DATA_CROSSES_CACHE_LINE(cache, address, size) ( \
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((address) & ((cache)->line_size - 1)) + (size) > (cache)->line_size \
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((address) & ((cache)->line_size - 1)) + (size) > (cache)->line_size \
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)
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)
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#define CACHE_INITIALIZED(cache) ((cache)->data_storage != NULL)
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#define CACHE_INITIALIZED(cache) ((cache)->data_storage != NULL)
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/* These functions are used to initialize and terminate a cache. */
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/* These functions are used to initialize and terminate a cache. */
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void
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void
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frv_cache_init (SIM_CPU *, FRV_CACHE *);
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frv_cache_init (SIM_CPU *, FRV_CACHE *);
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void
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void
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frv_cache_term (FRV_CACHE *);
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frv_cache_term (FRV_CACHE *);
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void
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void
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frv_cache_reconfigure (SIM_CPU *, FRV_CACHE *);
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frv_cache_reconfigure (SIM_CPU *, FRV_CACHE *);
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int
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int
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frv_cache_enabled (FRV_CACHE *);
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frv_cache_enabled (FRV_CACHE *);
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/* These functions are used to operate the cache in non-cycle-accurate mode.
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/* These functions are used to operate the cache in non-cycle-accurate mode.
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Each request is handled individually and immediately using the current
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Each request is handled individually and immediately using the current
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cache internal state. */
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cache internal state. */
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int
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int
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frv_cache_read (FRV_CACHE *, int, SI);
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frv_cache_read (FRV_CACHE *, int, SI);
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int
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int
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frv_cache_write (FRV_CACHE *, SI, char *, unsigned);
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frv_cache_write (FRV_CACHE *, SI, char *, unsigned);
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int
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int
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frv_cache_preload (FRV_CACHE *, SI, USI, int);
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frv_cache_preload (FRV_CACHE *, SI, USI, int);
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int
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int
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frv_cache_invalidate (FRV_CACHE *, SI, int);
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frv_cache_invalidate (FRV_CACHE *, SI, int);
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int
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int
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frv_cache_invalidate_all (FRV_CACHE *, int);
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frv_cache_invalidate_all (FRV_CACHE *, int);
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/* These functions are used to operate the cache in cycle-accurate mode.
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/* These functions are used to operate the cache in cycle-accurate mode.
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The internal operation of the cache is simulated down to the cycle level. */
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The internal operation of the cache is simulated down to the cycle level. */
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#define NO_REQNO 0xffffffff
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#define NO_REQNO 0xffffffff
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void
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void
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frv_cache_request_load (FRV_CACHE *, unsigned, SI, int);
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frv_cache_request_load (FRV_CACHE *, unsigned, SI, int);
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void
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void
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frv_cache_request_store (FRV_CACHE *, SI, int, char *, unsigned);
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frv_cache_request_store (FRV_CACHE *, SI, int, char *, unsigned);
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void
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void
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frv_cache_request_invalidate (FRV_CACHE *, unsigned, SI, int, int, int);
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frv_cache_request_invalidate (FRV_CACHE *, unsigned, SI, int, int, int);
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void
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void
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frv_cache_request_preload (FRV_CACHE *, SI, int, int, int);
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frv_cache_request_preload (FRV_CACHE *, SI, int, int, int);
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void
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void
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frv_cache_request_unlock (FRV_CACHE *, SI, int);
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frv_cache_request_unlock (FRV_CACHE *, SI, int);
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void
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void
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frv_cache_run (FRV_CACHE *, int);
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frv_cache_run (FRV_CACHE *, int);
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int
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int
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frv_cache_data_in_buffer (FRV_CACHE*, int, SI, unsigned);
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frv_cache_data_in_buffer (FRV_CACHE*, int, SI, unsigned);
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int
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int
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frv_cache_data_flushed (FRV_CACHE*, int, SI, unsigned);
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frv_cache_data_flushed (FRV_CACHE*, int, SI, unsigned);
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int
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int
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frv_cache_read_passive_SI (FRV_CACHE *, SI, SI *);
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frv_cache_read_passive_SI (FRV_CACHE *, SI, SI *);
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#endif /* CACHE_H */
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#endif /* CACHE_H */
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