/* Header for GDB Simulator wrapper for Or1ksim
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/* Header for GDB Simulator wrapper for Or1ksim
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Copyright 1988-2008, Free Software Foundation, Inc.
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Copyright 1988-2008, Free Software Foundation, Inc.
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Copyright (C) 2010 Embecosm Limited
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Copyright (C) 2010 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of GDB.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* This is a wrapper for Or1ksim, suitable for use as a GDB simulator.
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/* This is a wrapper for Or1ksim, suitable for use as a GDB simulator.
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The code tries to follow the GDB coding style.
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The code tries to follow the GDB coding style.
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Commenting is Doxygen compatible. */
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Commenting is Doxygen compatible. */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* GDB signal numbers */
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/* GDB signal numbers */
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#define TARGET_SIGNAL_NONE 0 /*!< No signal */
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#define TARGET_SIGNAL_NONE 0 /*!< No signal */
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#define TARGET_SIGNAL_TRAP 5 /*!< Breakpoint hit */
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#define TARGET_SIGNAL_TRAP 5 /*!< Breakpoint hit */
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/*! Number of registers */
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/*! Number of registers */
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#define OR32_MAX_GPRS 32
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#define OR32_MAX_GPRS 32
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/* Particular registers */
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/* Particular registers */
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#define OR32_FIRST_ARG_REGNUM 3 /*!< First arg reg */
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#define OR32_FIRST_ARG_REGNUM 3 /*!< First arg reg */
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#define OR32_PPC_REGNUM (OR32_MAX_GPRS + 0) /*!< Previous PC */
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#define OR32_PPC_REGNUM (OR32_MAX_GPRS + 0) /*!< Previous PC */
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#define OR32_NPC_REGNUM (OR32_MAX_GPRS + 1) /*!< Next PC */
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#define OR32_NPC_REGNUM (OR32_MAX_GPRS + 1) /*!< Next PC */
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#define OR32_SR_REGNUM (OR32_MAX_GPRS + 2) /*!< Supervision Reg */
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#define OR32_SR_REGNUM (OR32_MAX_GPRS + 2) /*!< Supervision Reg */
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/* Debug SPRs */
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/* Debug SPRs */
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#define OR32_SPR_NPC 0x0010 /*!< Next Program Counter */
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#define OR32_SPR_NPC 0x0010 /*!< Next Program Counter */
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#define OR32_SPR_SR 0x0011 /*!< Supervision Register */
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#define OR32_SPR_SR 0x0011 /*!< Supervision Register */
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#define OR32_SPR_PPC 0x0012 /*!< Previous Program Counter */
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#define OR32_SPR_PPC 0x0012 /*!< Previous Program Counter */
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#define OR32_SPR_DMR1 0x3010 /*!< Debug Mode Register 1 */
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#define OR32_SPR_DMR1 0x3010 /*!< Debug Mode Register 1 */
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#define OR32_SPR_DMR2 0x3011 /*!< Debug Mode Register 2 */
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#define OR32_SPR_DMR2 0x3011 /*!< Debug Mode Register 2 */
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#define OR32_SPR_DSR 0x3014 /*!< Debug Stop Register */
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#define OR32_SPR_DSR 0x3014 /*!< Debug Stop Register */
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#define OR32_SPR_DRR 0x3015 /*!< Debug Reason Register */
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#define OR32_SPR_DRR 0x3015 /*!< Debug Reason Register */
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/* Debug SPR bit fields */
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/* Debug SPR bit fields */
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#define OR32_SPR_DMR1_ST 0x00400000 /*!< Single-step trace*/
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#define OR32_SPR_DMR1_ST 0x00400000 /*!< Single-step trace*/
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#define OR32_SPR_DMR2_WGB 0x003ff000 /*!< Watchpoints which breakpoint */
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#define OR32_SPR_DMR2_WGB 0x003ff000 /*!< Watchpoints which breakpoint */
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#define OR32_SPR_DSR_TE 0x00002000 /*!< Trap exception bit */
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#define OR32_SPR_DSR_TE 0x00002000 /*!< Trap exception bit */
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/* OR1K exception vector addresses */
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/* OR1K exception vector addresses */
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#define OR32_RESET_EXCEPTION 0x100 /*!< Reset exception vector */
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#define OR32_RESET_EXCEPTION 0x100 /*!< Reset exception vector */
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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/*!A structure to hold the state of a simulation instance.
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/*!A structure to hold the state of a simulation instance.
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This is the typedef SIM_DESC.
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This is the typedef SIM_DESC.
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The entries are
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The entries are
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- A flag which is true if we are used for debug rather than standalone (i.e
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- A flag which is true if we are used for debug rather than standalone (i.e
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we were opened with type SIM_OPEN_DEBUG)
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we were opened with type SIM_OPEN_DEBUG)
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- The callback function supplied to the sim_open () function
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- The callback function supplied to the sim_open () function
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- This simulator's name (argv[0] supplied to sim_open ()
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- This simulator's name (argv[0] supplied to sim_open ()
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- A flag to indicate the simulator has been opened.
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- A flag to indicate the simulator has been opened.
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- The last reason the simulator stopped
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- The last reason the simulator stopped
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- The signal associated with the last stop, or the exit code from the last
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- The signal associated with the last stop, or the exit code from the last
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exit.
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exit.
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- The entry point to the program if available, otherwise the reset
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- The entry point to the program if available, otherwise the reset
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exception vector address.
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exception vector address.
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- The NPC with which to resume. So as not to destroy the pipeline, this is
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- The NPC with which to resume. So as not to destroy the pipeline, this is
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only written immediately before unstalling. */
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only written immediately before unstalling. */
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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struct sim_state
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struct sim_state
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{
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{
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int is_debug;
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int is_debug;
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struct host_callback_struct *callback;
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struct host_callback_struct *callback;
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char *myname;
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char *myname;
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int sim_open;
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int sim_open;
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enum sim_stop last_reason;
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enum sim_stop last_reason;
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unsigned int last_rc;
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unsigned int last_rc;
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unsigned long int entry_point;
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unsigned long int entry_point;
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unsigned long int resume_npc;
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unsigned long int resume_npc;
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};
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};
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