URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-7.1/] [sim/] [sh/] [tconfig.in] - Diff between revs 834 and 842

Rev 834	Rev 842
`/* sh target config file */`	`/* sh target config file */`

`/* Define this if the simulator supports profiling.`	`/* Define this if the simulator supports profiling.`
`See the mips simulator for an example.`	`See the mips simulator for an example.`
This enables the `-p foo' and `-s bar' options.	This enables the `-p foo' and `-s bar' options.
`The target is required to provide sim_set_profile{,_size}. */`	`The target is required to provide sim_set_profile{,_size}. */`
`/* #define SIM_HAVE_PROFILE */`	`/* #define SIM_HAVE_PROFILE */`

`/* Define this if the simulator uses an instruction cache.`	`/* Define this if the simulator uses an instruction cache.`
`See the h8/300 simulator for an example.`	`See the h8/300 simulator for an example.`
This enables the `-c size' option to set the size of the cache.	This enables the `-c size' option to set the size of the cache.
`The target is required to provide sim_set_simcache_size. */`	`The target is required to provide sim_set_simcache_size. */`
`/* #define SIM_HAVE_SIMCACHE */`	`/* #define SIM_HAVE_SIMCACHE */`

`/* Define this if the target cpu is bi-endian`	`/* Define this if the target cpu is bi-endian`
`and the simulator supports it. */`	`and the simulator supports it. */`
`#define SIM_HAVE_BIENDIAN`	`#define SIM_HAVE_BIENDIAN`