/* Main header for the Hitachi SH64 architecture. */
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/* Main header for the Hitachi SH64 architecture. */
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#ifndef SIM_MAIN_H
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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#define SIM_MAIN_H
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#define USING_SIM_BASE_H /* FIXME: quick hack */
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#define USING_SIM_BASE_H /* FIXME: quick hack */
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struct _sim_cpu; /* FIXME: should be in sim-basics.h */
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struct _sim_cpu; /* FIXME: should be in sim-basics.h */
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typedef struct _sim_cpu SIM_CPU;
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typedef struct _sim_cpu SIM_CPU;
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/* sim-basics.h includes config.h but cgen-types.h must be included before
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/* sim-basics.h includes config.h but cgen-types.h must be included before
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sim-basics.h and cgen-types.h needs config.h. */
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sim-basics.h and cgen-types.h needs config.h. */
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#include "config.h"
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#include "config.h"
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#include "symcat.h"
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#include "symcat.h"
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#include "sim-basics.h"
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#include "sim-basics.h"
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#include "cgen-types.h"
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#include "cgen-types.h"
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#include "sh-desc.h"
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#include "sh-desc.h"
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#include "sh-opc.h"
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#include "sh-opc.h"
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#include "arch.h"
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#include "arch.h"
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/* These must be defined before sim-base.h. */
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/* These must be defined before sim-base.h. */
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typedef UDI sim_cia;
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typedef UDI sim_cia;
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#define CIA_GET(cpu) CPU_PC_GET (cpu)
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#define CIA_GET(cpu) CPU_PC_GET (cpu)
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#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val) | (sh64_h_ism_get (cpu)))
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#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val) | (sh64_h_ism_get (cpu)))
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#include "sim-base.h"
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#include "sim-base.h"
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#include "cgen-sim.h"
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#include "cgen-sim.h"
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#include "sh64-sim.h"
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#include "sh64-sim.h"
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/* The _sim_cpu struct. */
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/* The _sim_cpu struct. */
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struct _sim_cpu {
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struct _sim_cpu {
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/* sim/common cpu base. */
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/* sim/common cpu base. */
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sim_cpu_base base;
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sim_cpu_base base;
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/* Static parts of cgen. */
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/* Static parts of cgen. */
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CGEN_CPU cgen_cpu;
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CGEN_CPU cgen_cpu;
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/* CPU specific parts go here.
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/* CPU specific parts go here.
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Note that in files that don't need to access these pieces WANT_CPU_FOO
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Note that in files that don't need to access these pieces WANT_CPU_FOO
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won't be defined and thus these parts won't appear. This is ok in the
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won't be defined and thus these parts won't appear. This is ok in the
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sense that things work. It is a source of bugs though.
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sense that things work. It is a source of bugs though.
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One has to of course be careful to not take the size of this
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One has to of course be careful to not take the size of this
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struct and no structure members accessed in non-cpu specific files can
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struct and no structure members accessed in non-cpu specific files can
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go after here. Oh for a better language. */
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go after here. Oh for a better language. */
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#if defined (WANT_CPU_SH64)
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#if defined (WANT_CPU_SH64)
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SH64_CPU_DATA cpu_data;
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SH64_CPU_DATA cpu_data;
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#endif
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#endif
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};
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};
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/* The sim_state struct. */
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/* The sim_state struct. */
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struct sim_state {
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struct sim_state {
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sim_cpu *cpu;
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sim_cpu *cpu;
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#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
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#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
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CGEN_STATE cgen_state;
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CGEN_STATE cgen_state;
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sim_state_base base;
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sim_state_base base;
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};
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};
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/* Misc. */
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/* Misc. */
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/* Catch address exceptions. */
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/* Catch address exceptions. */
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extern SIM_CORE_SIGNAL_FN sh64_core_signal;
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extern SIM_CORE_SIGNAL_FN sh64_core_signal;
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#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
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#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
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sh64_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
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sh64_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
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(TRANSFER), (ERROR))
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(TRANSFER), (ERROR))
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/* Default memory size. */
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/* Default memory size. */
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#define SH64_DEFAULT_MEM_SIZE 0x800000 /* 8M */
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#define SH64_DEFAULT_MEM_SIZE 0x800000 /* 8M */
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#endif /* SIM_MAIN_H */
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#endif /* SIM_MAIN_H */
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