URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
Rev 227 |
Rev 816 |
# frv testcase for andicc $GRi,$s10,$GRk,$ICCi_1
|
# frv testcase for andicc $GRi,$s10,$GRk,$ICCi_1
|
# mach: all
|
# mach: all
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
|
|
start
|
start
|
|
|
.global andicc
|
.global andicc
|
andicc:
|
andicc:
|
set_gr_limmed 0xaaaa,0xaaaa,gr7
|
set_gr_limmed 0xaaaa,0xaaaa,gr7
|
set_icc 0x0b,0 ; Set mask opposite of expected
|
set_icc 0x0b,0 ; Set mask opposite of expected
|
andicc gr7,0x155,gr8,icc0
|
andicc gr7,0x155,gr8,icc0
|
test_icc 0 1 1 1 icc0
|
test_icc 0 1 1 1 icc0
|
test_gr_immed 0,gr8
|
test_gr_immed 0,gr8
|
|
|
set_icc 0x04,0 ; Set mask opposite of expected
|
set_icc 0x04,0 ; Set mask opposite of expected
|
andicc gr7,-512,gr8,icc0
|
andicc gr7,-512,gr8,icc0
|
test_icc 1 0 0 0 icc0
|
test_icc 1 0 0 0 icc0
|
test_gr_limmed 0xaaaa,0xaa00,gr8
|
test_gr_limmed 0xaaaa,0xaa00,gr8
|
|
|
set_icc 0x05,0 ; Set mask opposite of expected
|
set_icc 0x05,0 ; Set mask opposite of expected
|
andicc gr7,-1,gr8,icc0
|
andicc gr7,-1,gr8,icc0
|
test_icc 1 0 0 1 icc0
|
test_icc 1 0 0 1 icc0
|
test_gr_limmed 0xaaaa,0xaaaa,gr8
|
test_gr_limmed 0xaaaa,0xaaaa,gr8
|
|
|
pass
|
pass
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.