# Hitachi H8 testcase 'shll'
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# Hitachi H8 testcase 'shll'
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# mach(): all
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.data
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.data
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byte_dest: .byte 0xa5
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byte_dest: .byte 0xa5
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.align 2
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.align 2
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word_dest: .word 0xa5a5
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word_dest: .word 0xa5a5
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.align 4
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.align 4
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long_dest: .long 0xa5a5a5a5
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long_dest: .long 0xa5a5a5a5
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.text
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.text
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shll_b_reg8_1:
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shll_b_reg8_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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shll.b r0l ; shift left logical by one
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shll.b r0l ; shift left logical by one
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;;; .word 0x1008
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;;; .word 0x1008
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
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test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
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.if (sim_cpu)
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.if (sim_cpu)
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test_h_gr32 0xa5a5a54a er0
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test_h_gr32 0xa5a5a54a er0
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.endif
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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shll_b_reg8_2:
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shll_b_reg8_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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shll.b #2, r0l ; shift left logical by two
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shll.b #2, r0l ; shift left logical by two
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;;; .word 0x1048
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;;; .word 0x1048
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_set
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test_neg_set
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test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100
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test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100
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.if (sim_cpu)
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.if (sim_cpu)
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test_h_gr32 0xa5a5a594 er0
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test_h_gr32 0xa5a5a594 er0
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.endif
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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.if (sim_cpu == h8sx)
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shll_b_reg8_4:
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shll_b_reg8_4:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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shll.b #4, r0l ; shift left logical by four
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shll.b #4, r0l ; shift left logical by four
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;;; .word 0x10a8
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;;; .word 0x10a8
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000
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test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000
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test_h_gr32 0xa5a5a550 er0
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test_h_gr32 0xa5a5a550 er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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shll_b_reg8_reg8:
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shll_b_reg8_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov #5, r0h
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mov #5, r0h
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shll.b r0h, r0l ; shift left logical by register value
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shll.b r0h, r0l ; shift left logical by register value
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_set
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test_neg_set
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test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000
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test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000
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test_h_gr32 0xa5a505a0 er0
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test_h_gr32 0xa5a505a0 er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.endif
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.endif
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.if (sim_cpu) ; Not available in h8300 mode
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.if (sim_cpu) ; Not available in h8300 mode
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shll_w_reg16_1:
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shll_w_reg16_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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shll.w r0 ; shift left logical by one
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shll.w r0 ; shift left logical by one
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;;; .word 0x1010
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;;; .word 0x1010
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
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test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
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test_h_gr32 0xa5a54b4a er0
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test_h_gr32 0xa5a54b4a er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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shll_w_reg16_2:
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shll_w_reg16_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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shll.w #2, r0 ; shift left logical by two
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shll.w #2, r0 ; shift left logical by two
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;;; .word 0x1050
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;;; .word 0x1050
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_set
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test_neg_set
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test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
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test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
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test_h_gr32 0xa5a59694 er0
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test_h_gr32 0xa5a59694 er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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.if (sim_cpu == h8sx)
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shll_w_reg16_4:
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shll_w_reg16_4:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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shll.w #4, r0 ; shift left logical by four
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shll.w #4, r0 ; shift left logical by four
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;;; .word 0x1020
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;;; .word 0x1020
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000
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test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000
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test_h_gr32 0xa5a55a50 er0
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test_h_gr32 0xa5a55a50 er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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shll_w_reg16_8:
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shll_w_reg16_8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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shll.w #8, r0 ; shift left logical by eight
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shll.w #8, r0 ; shift left logical by eight
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;;; .word 0x1060
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;;; .word 0x1060
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test_carry_set ; H=0 N=1 Z=0 V=0 C=1
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test_carry_set ; H=0 N=1 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_set
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test_neg_set
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test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000
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test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000
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test_h_gr32 0xa5a5a500 er0
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test_h_gr32 0xa5a5a500 er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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shll_w_reg16_reg8:
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shll_w_reg16_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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mov #5, r0h
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mov #5, r0h
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shll.w r0h, r0 ; shift left logical by register value
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shll.w r0h, r0 ; shift left logical by register value
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_set
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test_neg_set
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test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000
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test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000
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test_h_gr32 0xa5a5b4a0 er0
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test_h_gr32 0xa5a5b4a0 er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.endif
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.endif
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shll_l_reg32_1:
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shll_l_reg32_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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shll.l er0 ; shift left logical by one
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shll.l er0 ; shift left logical by one
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;;; .word 1030
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;;; .word 1030
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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; 1010 0101 1010 0101 1010 0101 1010 0101
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; 1010 0101 1010 0101 1010 0101 1010 0101
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; -> 0100 1011 0100 1011 0100 1011 0100 1010
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; -> 0100 1011 0100 1011 0100 1011 0100 1010
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test_h_gr32 0x4b4b4b4a er0
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test_h_gr32 0x4b4b4b4a er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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shll_l_reg32_2:
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shll_l_reg32_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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shll.l #2, er0 ; shift left logical by two
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shll.l #2, er0 ; shift left logical by two
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;;; .word 0x1070
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;;; .word 0x1070
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_set
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test_neg_set
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; 1010 0101 1010 0101 1010 0101 1010 0101
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; 1010 0101 1010 0101 1010 0101 1010 0101
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; -> 1001 0110 1001 0110 1001 0110 1001 0100
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; -> 1001 0110 1001 0110 1001 0110 1001 0100
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test_h_gr32 0x96969694 er0
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test_h_gr32 0x96969694 er0
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|
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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.if (sim_cpu == h8sx)
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shll_l_reg32_4:
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shll_l_reg32_4:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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|
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shll.l #4, er0 ; shift left logical by four
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shll.l #4, er0 ; shift left logical by four
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;;; .word 0x1038
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;;; .word 0x1038
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|
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_zero_clear
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test_zero_clear
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test_ovf_clear
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test_ovf_clear
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test_neg_clear
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test_neg_clear
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; 1010 0101 1010 0101 1010 0101 1010 0101
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; 1010 0101 1010 0101 1010 0101 1010 0101
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; -> 0101 1010 0101 1010 0101 1010 0101 0000
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; -> 0101 1010 0101 1010 0101 1010 0101 0000
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test_h_gr32 0x5a5a5a50 er0
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test_h_gr32 0x5a5a5a50 er0
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|
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
shll_l_reg32_8:
|
shll_l_reg32_8:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
shll.l #8, er0 ; shift left logical by eight
|
shll.l #8, er0 ; shift left logical by eight
|
;;; .word 0x1078
|
;;; .word 0x1078
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
test_h_gr16 0xa500 r0
|
test_h_gr16 0xa500 r0
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 1010 0101 1010 0101 1010 0101 0000 0000
|
; -> 1010 0101 1010 0101 1010 0101 0000 0000
|
test_h_gr32 0xa5a5a500 er0
|
test_h_gr32 0xa5a5a500 er0
|
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
shll_l_reg32_16:
|
shll_l_reg32_16:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
shll.l #16, er0 ; shift left logical by sixteen
|
shll.l #16, er0 ; shift left logical by sixteen
|
;;; .word 0x10f8
|
;;; .word 0x10f8
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
;; -> 1010 0101 1010 0101 0000 0000 0000 0000
|
;; -> 1010 0101 1010 0101 0000 0000 0000 0000
|
test_h_gr32 0xa5a50000 er0
|
test_h_gr32 0xa5a50000 er0
|
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
shll_l_reg32_reg8:
|
shll_l_reg32_reg8:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov #5, r1l
|
mov #5, r1l
|
shll.l r1l, er0 ; shift left logical by register value
|
shll.l r1l, er0 ; shift left logical by register value
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_zero_clear
|
test_zero_clear
|
test_ovf_clear
|
test_ovf_clear
|
test_neg_set
|
test_neg_set
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; 1010 0101 1010 0101 1010 0101 1010 0101
|
; -> 1011 0100 1011 0100 1011 0100 1010 0000
|
; -> 1011 0100 1011 0100 1011 0100 1010 0000
|
test_h_gr32 0xb4b4b4a0 er0
|
test_h_gr32 0xb4b4b4a0 er0
|
|
|
test_h_gr32 0xa5a5a505 er1
|
test_h_gr32 0xa5a5a505 er1
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
.endif
|
.endif
|
.endif
|
.endif
|
|
|
pass
|
pass
|
|
|
exit 0
|
exit 0
|
|
|
|
|
