# Hitachi H8 testcase 'sub.l'
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# Hitachi H8 testcase 'sub.l'
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# mach(): h8300h h8300s h8sx
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# mach(): h8300h h8300s h8sx
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# as(h8300): --defsym sim_cpu=0
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.if (sim_cpu == h8sx) ;
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.if (sim_cpu == h8sx) ;
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sub_l_imm3: ; 3-bit immediate mode only for h8sx
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sub_l_imm3: ; 3-bit immediate mode only for h8sx
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; sub.l #xx:3,eRd ; Immediate 3-bit operand
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;; sub.l #xx:3,eRd ; Immediate 3-bit operand
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sub.l #7:3, er0
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sub.l #7:3, er0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
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test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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sub_l_imm16: ; sub immediate 16-bit value
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sub_l_imm16: ; sub immediate 16-bit value
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; sub.l #xx:16,eRd ; Immediate 16-bit operand
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;; sub.l #xx:16,eRd ; Immediate 16-bit operand
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sub.l #0x1111:16, er0
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sub.l #0x1111:16, er0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111
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test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111
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test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111
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test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.endif
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.endif
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sub_l_imm32:
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sub_l_imm32:
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;; sub.l immediate not available in h8300 mode.
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;; sub.l immediate not available in h8300 mode.
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; sub.l #xx:32,Rd
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;; sub.l #xx:32,Rd
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sub.l #0x11111111, er0 ; Immediate 32-bit operand
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sub.l #0x11111111, er0 ; Immediate 32-bit operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
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test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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sub.l.reg:
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sub.l.reg:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; add.l Rs,Rd
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;; add.l Rs,Rd
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mov.l #0x11111111, er1
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mov.l #0x11111111, er1
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sub.l er1, er0 ; Register operand
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sub.l er1, er0 ; Register operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
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test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
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test_h_gr32 0x11111111 er1
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test_h_gr32 0x11111111 er1
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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pass
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pass
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exit 0
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exit 0
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