/****************************************************************************
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/****************************************************************************
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THIS SOFTWARE IS NOT COPYRIGHTED
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THIS SOFTWARE IS NOT COPYRIGHTED
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HP offers the following for use in the public domain. HP makes no
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HP offers the following for use in the public domain. HP makes no
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warranty with regard to the software or it's performance and the
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warranty with regard to the software or it's performance and the
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user accepts the software "AS IS" with all faults.
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user accepts the software "AS IS" with all faults.
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HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
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HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
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TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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****************************************************************************/
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****************************************************************************/
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/* Diagnose register definitions */
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/* Diagnose register definitions */
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#ifdef PCXL
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#ifdef PCXL
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#define CPU_DIAG_0_L2IHPMC_BIT 6 /* Level 2 I-cache error flag */
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#define CPU_DIAG_0_L2IHPMC_BIT 6 /* Level 2 I-cache error flag */
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#define CPU_DIAG_0_L2DHPMC_BIT 8 /* Level 2 D-cache error flag */
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#define CPU_DIAG_0_L2DHPMC_BIT 8 /* Level 2 D-cache error flag */
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#define CPU_DIAG_0_L1IHPMC_BIT 10 /* Level 1 I-cache error flag */
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#define CPU_DIAG_0_L1IHPMC_BIT 10 /* Level 1 I-cache error flag */
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#define CPU_DIAG_0_L2PARERR_BIT 15 /* rightmost bit */
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#define CPU_DIAG_0_L2PARERR_BIT 15 /* rightmost bit */
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#define CPU_DIAG_0_PREV_HPMC_PREP_BIT 16 /* Previous HPMC finished */
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#define CPU_DIAG_0_PREV_HPMC_PREP_BIT 16 /* Previous HPMC finished */
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#define CPU_DIAG_0_PWR_FAIL_BIT 17
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#define CPU_DIAG_0_PWR_FAIL_BIT 17
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#define CPU_DIAG_0_EXPECT_HPMC_BIT 18 /* Expecting HPMC */
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#define CPU_DIAG_0_EXPECT_HPMC_BIT 18 /* Expecting HPMC */
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/* Mask for Read/clear bits in CPU diagnose register 0 */
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/* Mask for Read/clear bits in CPU diagnose register 0 */
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#define CPU0_MASK 0x02AF0000
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#define CPU0_MASK 0x02AF0000
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#else /* PCXT */
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#else /* PCXT */
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#define CPU_DIAG_0_PREV_HPMC_PREP_BIT 3 /* Previous HPMC finished */
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#define CPU_DIAG_0_PREV_HPMC_PREP_BIT 3 /* Previous HPMC finished */
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#define CPU_DIAG_0_BOOTING_BIT 4
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#define CPU_DIAG_0_BOOTING_BIT 4
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#define CPU_DIAG_0_EXPECT_HPMC_BIT 5 /* Expecting HPMC */
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#define CPU_DIAG_0_EXPECT_HPMC_BIT 5 /* Expecting HPMC */
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#define CPU_DIAG_0_DHPMC_BIT 10
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#define CPU_DIAG_0_DHPMC_BIT 10
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#define CPU_DIAG_0_ILPMC_BIT 14
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#define CPU_DIAG_0_ILPMC_BIT 14
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#define CPU_DIAG_0_HTOC_BIT 23
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#define CPU_DIAG_0_HTOC_BIT 23
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/* Mask for Read/clear bits in CPU diagnose register 0 */
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/* Mask for Read/clear bits in CPU diagnose register 0 */
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#define CPU0_MASK 0x00220100
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#define CPU0_MASK 0x00220100
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#endif
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#endif
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/* Diagnose instruction macros */
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/* Diagnose instruction macros */
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#ifdef PCXL
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#ifdef PCXL
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/*** Different PCXL diagnose commands ***/
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/*** Different PCXL diagnose commands ***/
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/* Original mfcpu replaced with the two commands mfcpu_t & mfcpu_c */
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/* Original mfcpu replaced with the two commands mfcpu_t & mfcpu_c */
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mfcpu_t .macro diag_reg,gen_reg
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mfcpu_t .macro diag_reg,gen_reg
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{19 .. 26} = 0xa0 {24 .. 31}
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{19 .. 26} = 0xa0 {24 .. 31}
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{27 .. 31} = gen_reg {27 .. 31}
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{27 .. 31} = gen_reg {27 .. 31}
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.endm
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.endm
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mfcpu_c .macro diag_reg,gen_reg
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mfcpu_c .macro diag_reg,gen_reg
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{11 .. 15} = gen_reg {27 .. 31}
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{11 .. 15} = gen_reg {27 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{19 .. 26} = 0x30 {24 .. 31}
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{19 .. 26} = 0x30 {24 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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.endm
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.endm
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mtcpu .macro gen_reg,diag_reg
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mtcpu .macro gen_reg,diag_reg
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{11 .. 15} = gen_reg {27 .. 31}
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{11 .. 15} = gen_reg {27 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{19 .. 26} = 0x12 {24 .. 31}
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{19 .. 26} = 0x12 {24 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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.endm
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.endm
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shdw_gr .macro
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shdw_gr .macro
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 6 .. 10} = 0x0 {27 .. 31}
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{ 6 .. 10} = 0x0 {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{19 .. 26} = 0xd0 {24 .. 31}
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{19 .. 26} = 0xd0 {24 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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.endm
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.endm
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gr_shdw .macro
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gr_shdw .macro
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 6 .. 10} = 0x0 {27 .. 31}
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{ 6 .. 10} = 0x0 {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{19 .. 26} = 0xd2 {24 .. 31}
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{19 .. 26} = 0xd2 {24 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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.endm
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.endm
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#else
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#else
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/*** original PCXT version ***/
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/*** original PCXT version ***/
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/* Originally was mfcpu without the _c */
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/* Originally was mfcpu without the _c */
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mfcpu_c .macro diag_reg,gen_reg
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mfcpu_c .macro diag_reg,gen_reg
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{11 .. 15} = gen_reg {27 .. 31}
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{11 .. 15} = gen_reg {27 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{19 .. 26} = 0xd0 {24 .. 31}
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{19 .. 26} = 0xd0 {24 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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.endm
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.endm
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mtcpu .macro gen_reg,diag_reg
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mtcpu .macro gen_reg,diag_reg
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{ 6 .. 10} = diag_reg {27 .. 31}
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{11 .. 15} = gen_reg {27 .. 31}
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{11 .. 15} = gen_reg {27 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{19 .. 26} = 0xb0 {24 .. 31}
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{19 .. 26} = 0xb0 {24 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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.endm
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.endm
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shdw_gr .macro
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shdw_gr .macro
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 6 .. 10} = 0x2 {27 .. 31}
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{ 6 .. 10} = 0x2 {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{16 .. 18} = 0x1 {29 .. 31}
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{16 .. 18} = 0x1 {29 .. 31}
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{19 .. 26} = 0x30 {24 .. 31}
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{19 .. 26} = 0x30 {24 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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.endm
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.endm
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gr_shdw .macro
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gr_shdw .macro
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 0 .. 5} = 0x5 {26 .. 31}
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{ 6 .. 10} = 0x2 {27 .. 31}
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{ 6 .. 10} = 0x2 {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{11 .. 15} = 0x0 {27 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{16 .. 18} = 0x0 {29 .. 31}
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{19 .. 26} = 0x31 {24 .. 31}
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{19 .. 26} = 0x31 {24 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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{27 .. 31} = 0x0 {27 .. 31}
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.endm
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.endm
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#endif
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#endif
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/* Actual commands used doubled instructions for cpu timing */
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/* Actual commands used doubled instructions for cpu timing */
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#define SHDW_GR shdw_gr ! \
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#define SHDW_GR shdw_gr ! \
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shdw_gr
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shdw_gr
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/* Break instruction definitions */
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/* Break instruction definitions */
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#define i13BREAK 0xa5a /* im13 field for specified functions */
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#define i13BREAK 0xa5a /* im13 field for specified functions */
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#define i5REG 0x06 /* Init registers */
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#define i5REG 0x06 /* Init registers */
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#define i5BP 0x09 /* GDB breakpoint */
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#define i5BP 0x09 /* GDB breakpoint */
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#define i5PSW 0x0b /* Get PSW */
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#define i5PSW 0x0b /* Get PSW */
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#define i5INLINE 0x0e /* Get INLINE */
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#define i5INLINE 0x0e /* Get INLINE */
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BR_INIT_REGS .macro
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BR_INIT_REGS .macro
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break i5REG,i13BREAK
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break i5REG,i13BREAK
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.endm
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.endm
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BR_GET_PSW .macro
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BR_GET_PSW .macro
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break i5PSW,i13BREAK
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break i5PSW,i13BREAK
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.endm
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.endm
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BR_INLINE .macro
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BR_INLINE .macro
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break i5INLINE,i13BREAK
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break i5INLINE,i13BREAK
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.endm
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.endm
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