/* Cache code for SPARClite
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/* Cache code for SPARClite
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*
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*
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* Copyright (c) 1998 Cygnus Support
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* Copyright (c) 1998 Cygnus Support
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*
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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* they apply.
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*/
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*/
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#include "sparclite.h"
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#include "sparclite.h"
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/* Ancillary registers on the DANlite */
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/* Ancillary registers on the DANlite */
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#define DIAG 30
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#define DIAG 30
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#define ICCR 31
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#define ICCR 31
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/* Bits in the DIAG register */
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/* Bits in the DIAG register */
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#define ICD 0x40000000 /* ICACHE disable */
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#define ICD 0x40000000 /* ICACHE disable */
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#define DCD 0x20000000 /* DCACHE disable */
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#define DCD 0x20000000 /* DCACHE disable */
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/* Bits in the ICCR register */
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/* Bits in the ICCR register */
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#define CE 1 /* cache enable*/
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#define CE 1 /* cache enable*/
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/* Forward declarations. */
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/* Forward declarations. */
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void flush_i_cache ();
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void flush_i_cache ();
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/* Determine if this is a DANlite (MB8686x), as opposed to an earlier
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/* Determine if this is a DANlite (MB8686x), as opposed to an earlier
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SPARClite (MB8683x). This is done by examining the impl and ver
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SPARClite (MB8683x). This is done by examining the impl and ver
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fields in the PSR:
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fields in the PSR:
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MB8683x: impl(bit31-28)=0x0; ver(bit27-24)=0xf;
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MB8683x: impl(bit31-28)=0x0; ver(bit27-24)=0xf;
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MB8686x: impl(bit31-28)=0x1; ver(bit27-24)=0xe;
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MB8686x: impl(bit31-28)=0x1; ver(bit27-24)=0xe;
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*/
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*/
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static int
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static int
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is_danlite ()
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is_danlite ()
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{
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{
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static int checked = 0;
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static int checked = 0;
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static int danlite = 0;
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static int danlite = 0;
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if (!checked)
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if (!checked)
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{
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{
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int psr = read_psr ();
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int psr = read_psr ();
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danlite = (psr & 0xff000000) == 0x1e000000;
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danlite = (psr & 0xff000000) == 0x1e000000;
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checked = 1;
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checked = 1;
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}
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}
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return danlite;
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return danlite;
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}
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}
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/* This cache code is known to work on both the 930 & 932 processors. It just
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/* This cache code is known to work on both the 930 & 932 processors. It just
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cheats and clears the all of the address space that could contain tags, as
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cheats and clears the all of the address space that could contain tags, as
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opposed to striding the tags at 8 or 16 word intervals, or using the cache
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opposed to striding the tags at 8 or 16 word intervals, or using the cache
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flush registers, which don't exist on all processors. */
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flush registers, which don't exist on all processors. */
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void
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void
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cache_off ()
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cache_off ()
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{
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{
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if (is_danlite ())
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if (is_danlite ())
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{
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{
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/* Disable the ICACHE. Disabling the DCACHE crashes the machine. */
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/* Disable the ICACHE. Disabling the DCACHE crashes the machine. */
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unsigned int diag = read_asr (DIAG);
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unsigned int diag = read_asr (DIAG);
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write_asr (DIAG, diag | ICD);
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write_asr (DIAG, diag | ICD);
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}
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}
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else
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else
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{
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{
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write_asi (1, 0, 0);
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write_asi (1, 0, 0);
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}
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}
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}
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}
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void
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void
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cache_on ()
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cache_on ()
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{
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{
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if (is_danlite ())
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if (is_danlite ())
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{
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{
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unsigned int diag;
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unsigned int diag;
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/* Flush the caches. */
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/* Flush the caches. */
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flush_i_cache ();
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flush_i_cache ();
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/* Enable the ICACHE and DCACHE */
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/* Enable the ICACHE and DCACHE */
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diag = read_asr (DIAG);
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diag = read_asr (DIAG);
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write_asr (DIAG, diag & ~ (ICD | DCD));
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write_asr (DIAG, diag & ~ (ICD | DCD));
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}
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}
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else
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else
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{
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{
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unsigned long addr;
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unsigned long addr;
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cache_off (); /* Make sure the cache is off */
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cache_off (); /* Make sure the cache is off */
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/* Reset all of the cache line valid bits */
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/* Reset all of the cache line valid bits */
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for (addr = 0; addr < 0x1000; addr += 8)
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for (addr = 0; addr < 0x1000; addr += 8)
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{
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{
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write_asi (0xc, addr, 0); /* Clear bank 1, icache */
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write_asi (0xc, addr, 0); /* Clear bank 1, icache */
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write_asi (0xc, addr + 0x80000000, 0); /* Clear bank 2, icache */
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write_asi (0xc, addr + 0x80000000, 0); /* Clear bank 2, icache */
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write_asi (0xe, addr, 0); /* Clear bank 1, dcache */
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write_asi (0xe, addr, 0); /* Clear bank 1, dcache */
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write_asi (0xe, addr + 0x80000000, 0); /* Clear bank 2, dcache */
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write_asi (0xe, addr + 0x80000000, 0); /* Clear bank 2, dcache */
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}
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}
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/* turn on the cache */
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/* turn on the cache */
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write_asi (1, 0, 0x35); /* Write buf ena, prefetch buf ena, data
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write_asi (1, 0, 0x35); /* Write buf ena, prefetch buf ena, data
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& inst caches enab */
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& inst caches enab */
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}
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}
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}
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}
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/* Flush the instruction cache. We need to do this for the debugger stub so
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/* Flush the instruction cache. We need to do this for the debugger stub so
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that breakpoints, et. al. become visible to the instruction stream after
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that breakpoints, et. al. become visible to the instruction stream after
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storing them in memory.
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storing them in memory.
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*/
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*/
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void
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void
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flush_i_cache ()
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flush_i_cache ()
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{
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{
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if (is_danlite ())
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if (is_danlite ())
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{
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{
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write_asi (0x31, 0, 0); /* Flush entire i/d caches */
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write_asi (0x31, 0, 0); /* Flush entire i/d caches */
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}
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}
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else
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else
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{
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{
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int cache_reg;
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int cache_reg;
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unsigned long addr;
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unsigned long addr;
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cache_reg = read_asi (1, 0); /* Read cache/bus interface reg */
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cache_reg = read_asi (1, 0); /* Read cache/bus interface reg */
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if (!(cache_reg & 1))
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if (!(cache_reg & 1))
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return; /* Just return if cache is already off */
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return; /* Just return if cache is already off */
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for (addr = 0; addr < 0x1000; addr += 8)
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for (addr = 0; addr < 0x1000; addr += 8)
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{
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{
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write_asi (0xc, addr, 0); /* Clear bank 1, icache */
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write_asi (0xc, addr, 0); /* Clear bank 1, icache */
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write_asi (0xc, addr + 0x80000000, 0); /* Clear bank 2, icache */
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write_asi (0xc, addr + 0x80000000, 0); /* Clear bank 2, icache */
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}
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}
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}
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}
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}
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}
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