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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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| Rev 38 |
Rev 156 |
#source: greg-1.s
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#source: greg-1.s
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#source: gregpsj1.s
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#source: gregpsj1.s
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#source: start.s
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#source: start.s
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#source: a.s
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#source: a.s
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#as: -x
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#as: -x
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#ld: -m elf64mmix
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#ld: -m elf64mmix
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#objdump: -dt
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#objdump: -dt
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# Like greg-3, but a different expanding insn.
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# Like greg-3, but a different expanding insn.
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.*: file format elf64-mmix
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.*: file format elf64-mmix
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SYMBOL TABLE:
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SYMBOL TABLE:
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0+ l d \.text 0+ (|\.text)
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0+ l d \.text 0+ (|\.text)
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0+7f0 l d \.MMIX\.reg_contents 0+ (|\.MMIX\.reg_contents)
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0+7f0 l d \.MMIX\.reg_contents 0+ (|\.MMIX\.reg_contents)
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0+4 g \.text 0+ _start
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0+4 g \.text 0+ _start
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0+fe g \*REG\* 0+ areg
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0+fe g \*REG\* 0+ areg
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#...
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#...
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0+8 g \.text 0+ a
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0+8 g \.text 0+ a
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Disassembly of section \.text:
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Disassembly of section \.text:
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0+ <_start-0x4>:
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0+ <_start-0x4>:
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0: f2fe0002 pushj \$254,8
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0: f2fe0002 pushj \$254,8
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0+4 <_start>:
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0+4 <_start>:
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4: e3fd0001 setl \$253,0x1
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4: e3fd0001 setl \$253,0x1
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0+8 :
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0+8 :
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8: e3fd0004 setl \$253,0x4
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8: e3fd0004 setl \$253,0x4
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