;; GCC machine description for Alpha synchronization instructions.
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;; GCC machine description for Alpha synchronization instructions.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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(define_mode_macro I12MODE [QI HI])
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(define_mode_macro I12MODE [QI HI])
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(define_mode_macro I48MODE [SI DI])
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(define_mode_macro I48MODE [SI DI])
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(define_mode_attr modesuffix [(SI "l") (DI "q")])
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(define_mode_attr modesuffix [(SI "l") (DI "q")])
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(define_code_macro FETCHOP [plus minus ior xor and])
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(define_code_macro FETCHOP [plus minus ior xor and])
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(define_code_attr fetchop_name
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(define_code_attr fetchop_name
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[(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
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[(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
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(define_code_attr fetchop_pred
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(define_code_attr fetchop_pred
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[(plus "add_operand") (minus "reg_or_8bit_operand")
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[(plus "add_operand") (minus "reg_or_8bit_operand")
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(ior "or_operand") (xor "or_operand") (and "and_operand")])
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(ior "or_operand") (xor "or_operand") (and "and_operand")])
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(define_code_attr fetchop_constr
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(define_code_attr fetchop_constr
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[(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNHM")])
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[(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNHM")])
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(define_expand "memory_barrier"
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(define_expand "memory_barrier"
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[(set (mem:BLK (match_dup 0))
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[(set (mem:BLK (match_dup 0))
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(unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MB))]
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(unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MB))]
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""
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""
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{
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
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MEM_VOLATILE_P (operands[0]) = 1;
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MEM_VOLATILE_P (operands[0]) = 1;
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})
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})
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(define_insn "*mb_internal"
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(define_insn "*mb_internal"
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[(set (match_operand:BLK 0 "" "")
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MB))]
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(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MB))]
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""
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""
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"mb"
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"mb"
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[(set_attr "type" "mb")])
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[(set_attr "type" "mb")])
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(define_insn "load_locked_"
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(define_insn "load_locked_"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(unspec_volatile:I48MODE
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(unspec_volatile:I48MODE
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[(match_operand:I48MODE 1 "memory_operand" "m")]
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[(match_operand:I48MODE 1 "memory_operand" "m")]
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UNSPECV_LL))]
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UNSPECV_LL))]
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""
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""
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"ld_l %0,%1"
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"ld_l %0,%1"
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[(set_attr "type" "ld_l")])
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[(set_attr "type" "ld_l")])
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(define_insn "store_conditional_"
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(define_insn "store_conditional_"
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[(set (match_operand:DI 0 "register_operand" "=r")
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec_volatile:DI [(const_int 0)] UNSPECV_SC))
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(unspec_volatile:DI [(const_int 0)] UNSPECV_SC))
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(set (match_operand:I48MODE 1 "memory_operand" "=m")
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(set (match_operand:I48MODE 1 "memory_operand" "=m")
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(match_operand:I48MODE 2 "reg_or_0_operand" "0"))]
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(match_operand:I48MODE 2 "reg_or_0_operand" "0"))]
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""
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""
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"st_c %0,%1"
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"st_c %0,%1"
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[(set_attr "type" "st_c")])
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[(set_attr "type" "st_c")])
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;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
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;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
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;; the lock is cleared by a TAKEN branch. If we were to honor that, it
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;; the lock is cleared by a TAKEN branch. If we were to honor that, it
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;; would mean that we could not expand a ll/sc sequence until after the
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;; would mean that we could not expand a ll/sc sequence until after the
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;; final basic-block reordering pass. Fortunately, it appears that no
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;; final basic-block reordering pass. Fortunately, it appears that no
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;; Alpha implementation ever built actually clears the lock on branches,
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;; Alpha implementation ever built actually clears the lock on branches,
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;; taken or not.
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;; taken or not.
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(define_insn_and_split "sync_"
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(define_insn_and_split "sync_"
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[(set (match_operand:I48MODE 0 "memory_operand" "+m")
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[(set (match_operand:I48MODE 0 "memory_operand" "+m")
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(unspec:I48MODE
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(unspec:I48MODE
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[(FETCHOP:I48MODE (match_dup 0)
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[(FETCHOP:I48MODE (match_dup 0)
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(match_operand:I48MODE 1 "" ""))]
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(match_operand:I48MODE 1 "" ""))]
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UNSPEC_ATOMIC))
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 2 "=&r"))]
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(clobber (match_scratch:I48MODE 2 "=&r"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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{
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{
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alpha_split_atomic_op (, operands[0], operands[1],
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alpha_split_atomic_op (, operands[0], operands[1],
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NULL, NULL, operands[2]);
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NULL, NULL, operands[2]);
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DONE;
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DONE;
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}
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}
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[(set_attr "type" "multi")])
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[(set_attr "type" "multi")])
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(define_insn_and_split "sync_nand"
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(define_insn_and_split "sync_nand"
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[(set (match_operand:I48MODE 0 "memory_operand" "+m")
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[(set (match_operand:I48MODE 0 "memory_operand" "+m")
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(unspec:I48MODE
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(unspec:I48MODE
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[(and:I48MODE (not:I48MODE (match_dup 0))
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[(and:I48MODE (not:I48MODE (match_dup 0))
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(match_operand:I48MODE 1 "register_operand" "r"))]
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(match_operand:I48MODE 1 "register_operand" "r"))]
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UNSPEC_ATOMIC))
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 2 "=&r"))]
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(clobber (match_scratch:I48MODE 2 "=&r"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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{
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{
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alpha_split_atomic_op (NOT, operands[0], operands[1],
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alpha_split_atomic_op (NOT, operands[0], operands[1],
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NULL, NULL, operands[2]);
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NULL, NULL, operands[2]);
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DONE;
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DONE;
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}
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}
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[(set_attr "type" "multi")])
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[(set_attr "type" "multi")])
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(define_insn_and_split "sync_old_"
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(define_insn_and_split "sync_old_"
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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(match_operand:I48MODE 1 "memory_operand" "+m"))
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(match_operand:I48MODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec:I48MODE
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(unspec:I48MODE
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[(FETCHOP:I48MODE (match_dup 1)
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[(FETCHOP:I48MODE (match_dup 1)
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(match_operand:I48MODE 2 "" ""))]
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(match_operand:I48MODE 2 "" ""))]
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UNSPEC_ATOMIC))
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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{
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{
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alpha_split_atomic_op (, operands[1], operands[2],
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alpha_split_atomic_op (, operands[1], operands[2],
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operands[0], NULL, operands[3]);
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operands[0], NULL, operands[3]);
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DONE;
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DONE;
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}
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}
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[(set_attr "type" "multi")])
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[(set_attr "type" "multi")])
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(define_insn_and_split "sync_old_nand"
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(define_insn_and_split "sync_old_nand"
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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(match_operand:I48MODE 1 "memory_operand" "+m"))
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(match_operand:I48MODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec:I48MODE
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(unspec:I48MODE
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[(and:I48MODE (not:I48MODE (match_dup 1))
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[(and:I48MODE (not:I48MODE (match_dup 1))
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(match_operand:I48MODE 2 "register_operand" "r"))]
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(match_operand:I48MODE 2 "register_operand" "r"))]
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UNSPEC_ATOMIC))
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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{
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{
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alpha_split_atomic_op (NOT, operands[1], operands[2],
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alpha_split_atomic_op (NOT, operands[1], operands[2],
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operands[0], NULL, operands[3]);
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operands[0], NULL, operands[3]);
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DONE;
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DONE;
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}
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}
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[(set_attr "type" "multi")])
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[(set_attr "type" "multi")])
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(define_insn_and_split "sync_new_"
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(define_insn_and_split "sync_new_"
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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(FETCHOP:I48MODE
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(FETCHOP:I48MODE
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(match_operand:I48MODE 1 "memory_operand" "+m")
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(match_operand:I48MODE 1 "memory_operand" "+m")
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(match_operand:I48MODE 2 "" "")))
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(match_operand:I48MODE 2 "" "")))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec:I48MODE
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(unspec:I48MODE
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[(FETCHOP:I48MODE (match_dup 1) (match_dup 2))]
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[(FETCHOP:I48MODE (match_dup 1) (match_dup 2))]
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UNSPEC_ATOMIC))
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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{
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{
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alpha_split_atomic_op (, operands[1], operands[2],
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alpha_split_atomic_op (, operands[1], operands[2],
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NULL, operands[0], operands[3]);
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NULL, operands[0], operands[3]);
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DONE;
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DONE;
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}
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}
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[(set_attr "type" "multi")])
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[(set_attr "type" "multi")])
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(define_insn_and_split "sync_new_nand"
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(define_insn_and_split "sync_new_nand"
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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(and:I48MODE
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(and:I48MODE
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(not:I48MODE (match_operand:I48MODE 1 "memory_operand" "+m"))
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(not:I48MODE (match_operand:I48MODE 1 "memory_operand" "+m"))
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(match_operand:I48MODE 2 "register_operand" "r")))
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(match_operand:I48MODE 2 "register_operand" "r")))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec:I48MODE
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(unspec:I48MODE
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[(and:I48MODE (not:I48MODE (match_dup 1)) (match_dup 2))]
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[(and:I48MODE (not:I48MODE (match_dup 1)) (match_dup 2))]
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UNSPEC_ATOMIC))
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UNSPEC_ATOMIC))
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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(clobber (match_scratch:I48MODE 3 "=&r"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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{
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{
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alpha_split_atomic_op (NOT, operands[1], operands[2],
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alpha_split_atomic_op (NOT, operands[1], operands[2],
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NULL, operands[0], operands[3]);
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NULL, operands[0], operands[3]);
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DONE;
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DONE;
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}
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}
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[(set_attr "type" "multi")])
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[(set_attr "type" "multi")])
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(define_expand "sync_compare_and_swap"
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(define_expand "sync_compare_and_swap"
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[(match_operand:I12MODE 0 "register_operand" "")
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[(match_operand:I12MODE 0 "register_operand" "")
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(match_operand:I12MODE 1 "memory_operand" "")
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(match_operand:I12MODE 1 "memory_operand" "")
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(match_operand:I12MODE 2 "register_operand" "")
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(match_operand:I12MODE 2 "register_operand" "")
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(match_operand:I12MODE 3 "add_operand" "")]
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(match_operand:I12MODE 3 "add_operand" "")]
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""
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""
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{
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{
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alpha_expand_compare_and_swap_12 (operands[0], operands[1],
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alpha_expand_compare_and_swap_12 (operands[0], operands[1],
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operands[2], operands[3]);
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operands[2], operands[3]);
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DONE;
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DONE;
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})
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})
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(define_insn_and_split "sync_compare_and_swap_1"
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(define_insn_and_split "sync_compare_and_swap_1"
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[(set (match_operand:DI 0 "register_operand" "=&r,&r")
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[(set (match_operand:DI 0 "register_operand" "=&r,&r")
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(zero_extend:DI
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(zero_extend:DI
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(mem:I12MODE (match_operand:DI 1 "register_operand" "r,r"))))
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(mem:I12MODE (match_operand:DI 1 "register_operand" "r,r"))))
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(set (mem:I12MODE (match_dup 1))
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(set (mem:I12MODE (match_dup 1))
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(unspec:I12MODE
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(unspec:I12MODE
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[(match_operand:DI 2 "reg_or_8bit_operand" "J,rI")
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[(match_operand:DI 2 "reg_or_8bit_operand" "J,rI")
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(match_operand:DI 3 "register_operand" "r,r")
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(match_operand:DI 3 "register_operand" "r,r")
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(match_operand:DI 4 "register_operand" "r,r")]
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(match_operand:DI 4 "register_operand" "r,r")]
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UNSPEC_CMPXCHG))
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UNSPEC_CMPXCHG))
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(clobber (match_scratch:DI 5 "=&r,&r"))
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(clobber (match_scratch:DI 5 "=&r,&r"))
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(clobber (match_scratch:DI 6 "=X,&r"))]
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(clobber (match_scratch:DI 6 "=X,&r"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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{
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{
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alpha_split_compare_and_swap_12 (mode, operands[0], operands[1],
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alpha_split_compare_and_swap_12 (mode, operands[0], operands[1],
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operands[2], operands[3], operands[4],
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operands[2], operands[3], operands[4],
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operands[5], operands[6]);
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operands[5], operands[6]);
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DONE;
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DONE;
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}
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}
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[(set_attr "type" "multi")])
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[(set_attr "type" "multi")])
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|
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(define_expand "sync_compare_and_swap"
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(define_expand "sync_compare_and_swap"
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[(parallel
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[(parallel
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[(set (match_operand:I48MODE 0 "register_operand" "")
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[(set (match_operand:I48MODE 0 "register_operand" "")
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(match_operand:I48MODE 1 "memory_operand" ""))
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(match_operand:I48MODE 1 "memory_operand" ""))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec:I48MODE
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(unspec:I48MODE
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[(match_operand:I48MODE 2 "reg_or_8bit_operand" "")
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[(match_operand:I48MODE 2 "reg_or_8bit_operand" "")
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(match_operand:I48MODE 3 "add_operand" "rKL")]
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(match_operand:I48MODE 3 "add_operand" "rKL")]
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UNSPEC_CMPXCHG))
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UNSPEC_CMPXCHG))
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(clobber (match_scratch:I48MODE 4 "=&r"))])]
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(clobber (match_scratch:I48MODE 4 "=&r"))])]
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""
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""
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{
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{
|
if (mode == SImode)
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if (mode == SImode)
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operands[2] = convert_modes (DImode, SImode, operands[2], 0);
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operands[2] = convert_modes (DImode, SImode, operands[2], 0);
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})
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})
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|
|
(define_insn_and_split "*sync_compare_and_swap"
|
(define_insn_and_split "*sync_compare_and_swap"
|
[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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[(set (match_operand:I48MODE 0 "register_operand" "=&r")
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(match_operand:I48MODE 1 "memory_operand" "+m"))
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(match_operand:I48MODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec:I48MODE
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(unspec:I48MODE
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[(match_operand:DI 2 "reg_or_8bit_operand" "rI")
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[(match_operand:DI 2 "reg_or_8bit_operand" "rI")
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(match_operand:I48MODE 3 "add_operand" "rKL")]
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(match_operand:I48MODE 3 "add_operand" "rKL")]
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UNSPEC_CMPXCHG))
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UNSPEC_CMPXCHG))
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(clobber (match_scratch:I48MODE 4 "=&r"))]
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(clobber (match_scratch:I48MODE 4 "=&r"))]
|
""
|
""
|
"#"
|
"#"
|
"reload_completed"
|
"reload_completed"
|
[(const_int 0)]
|
[(const_int 0)]
|
{
|
{
|
alpha_split_compare_and_swap (operands[0], operands[1], operands[2],
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alpha_split_compare_and_swap (operands[0], operands[1], operands[2],
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operands[3], operands[4]);
|
operands[3], operands[4]);
|
DONE;
|
DONE;
|
}
|
}
|
[(set_attr "type" "multi")])
|
[(set_attr "type" "multi")])
|
|
|
(define_expand "sync_lock_test_and_set"
|
(define_expand "sync_lock_test_and_set"
|
[(match_operand:I12MODE 0 "register_operand" "")
|
[(match_operand:I12MODE 0 "register_operand" "")
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(match_operand:I12MODE 1 "memory_operand" "")
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(match_operand:I12MODE 1 "memory_operand" "")
|
(match_operand:I12MODE 2 "register_operand" "")]
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(match_operand:I12MODE 2 "register_operand" "")]
|
""
|
""
|
{
|
{
|
alpha_expand_lock_test_and_set_12 (operands[0], operands[1], operands[2]);
|
alpha_expand_lock_test_and_set_12 (operands[0], operands[1], operands[2]);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn_and_split "sync_lock_test_and_set_1"
|
(define_insn_and_split "sync_lock_test_and_set_1"
|
[(set (match_operand:DI 0 "register_operand" "=&r")
|
[(set (match_operand:DI 0 "register_operand" "=&r")
|
(zero_extend:DI
|
(zero_extend:DI
|
(mem:I12MODE (match_operand:DI 1 "register_operand" "r"))))
|
(mem:I12MODE (match_operand:DI 1 "register_operand" "r"))))
|
(set (mem:I12MODE (match_dup 1))
|
(set (mem:I12MODE (match_dup 1))
|
(unspec:I12MODE
|
(unspec:I12MODE
|
[(match_operand:DI 2 "reg_or_8bit_operand" "rI")
|
[(match_operand:DI 2 "reg_or_8bit_operand" "rI")
|
(match_operand:DI 3 "register_operand" "r")]
|
(match_operand:DI 3 "register_operand" "r")]
|
UNSPEC_XCHG))
|
UNSPEC_XCHG))
|
(clobber (match_scratch:DI 4 "=&r"))]
|
(clobber (match_scratch:DI 4 "=&r"))]
|
""
|
""
|
"#"
|
"#"
|
"reload_completed"
|
"reload_completed"
|
[(const_int 0)]
|
[(const_int 0)]
|
{
|
{
|
alpha_split_lock_test_and_set_12 (mode, operands[0], operands[1],
|
alpha_split_lock_test_and_set_12 (mode, operands[0], operands[1],
|
operands[2], operands[3], operands[4]);
|
operands[2], operands[3], operands[4]);
|
DONE;
|
DONE;
|
}
|
}
|
[(set_attr "type" "multi")])
|
[(set_attr "type" "multi")])
|
|
|
(define_insn_and_split "sync_lock_test_and_set"
|
(define_insn_and_split "sync_lock_test_and_set"
|
[(set (match_operand:I48MODE 0 "register_operand" "=&r")
|
[(set (match_operand:I48MODE 0 "register_operand" "=&r")
|
(match_operand:I48MODE 1 "memory_operand" "+m"))
|
(match_operand:I48MODE 1 "memory_operand" "+m"))
|
(set (match_dup 1)
|
(set (match_dup 1)
|
(unspec:I48MODE
|
(unspec:I48MODE
|
[(match_operand:I48MODE 2 "add_operand" "rKL")]
|
[(match_operand:I48MODE 2 "add_operand" "rKL")]
|
UNSPEC_XCHG))
|
UNSPEC_XCHG))
|
(clobber (match_scratch:I48MODE 3 "=&r"))]
|
(clobber (match_scratch:I48MODE 3 "=&r"))]
|
""
|
""
|
"#"
|
"#"
|
"reload_completed"
|
"reload_completed"
|
[(const_int 0)]
|
[(const_int 0)]
|
{
|
{
|
alpha_split_lock_test_and_set (operands[0], operands[1],
|
alpha_split_lock_test_and_set (operands[0], operands[1],
|
operands[2], operands[3]);
|
operands[2], operands[3]);
|
DONE;
|
DONE;
|
}
|
}
|
[(set_attr "type" "multi")])
|
[(set_attr "type" "multi")])
|
|
|
