;; Constraint definitions for ARM and Thumb
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;; Constraint definitions for ARM and Thumb
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;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
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;; Contributed by ARM Ltd.
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;; Contributed by ARM Ltd.
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;; This file is part of GCC.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; The following register constraints have been used:
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;; The following register constraints have been used:
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;; - in ARM state: f, v, w, y, z
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;; - in ARM state: f, v, w, y, z
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;; - in Thumb state: h, k, b
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;; - in Thumb state: h, k, b
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;; - in both states: l, c
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;; - in both states: l, c
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;; In ARM state, 'l' is an alias for 'r'
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;; In ARM state, 'l' is an alias for 'r'
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;; The following normal constraints have been used:
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;; The following normal constraints have been used:
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;; in ARM state: G, H, I, J, K, L, M
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;; in ARM state: G, H, I, J, K, L, M
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;; in Thumb state: I, J, K, L, M, N, O
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;; in Thumb state: I, J, K, L, M, N, O
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;; The following multi-letter normal constraints have been used:
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;; The following multi-letter normal constraints have been used:
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;; in ARM state: Da, Db, Dc
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;; in ARM state: Da, Db, Dc
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;; The following memory constraints have been used:
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;; The following memory constraints have been used:
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;; in ARM state: Q, Uq, Uv, Uy
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;; in ARM state: Q, Uq, Uv, Uy
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(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
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(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
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"Legacy FPA registers @code{f0}-@code{f7}.")
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"Legacy FPA registers @code{f0}-@code{f7}.")
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(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
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(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
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"The Cirrus Maverick co-processor registers.")
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"The Cirrus Maverick co-processor registers.")
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(define_register_constraint "w" "TARGET_ARM ? VFP_REGS : NO_REGS"
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(define_register_constraint "w" "TARGET_ARM ? VFP_REGS : NO_REGS"
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"The VFP registers @code{s0}-@code{s31}.")
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"The VFP registers @code{s0}-@code{s31}.")
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(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
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(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
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"The Intel iWMMX co-processor registers.")
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"The Intel iWMMX co-processor registers.")
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(define_register_constraint "z"
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(define_register_constraint "z"
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"TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
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"TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
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"The Intel iWMMX GR registers.")
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"The Intel iWMMX GR registers.")
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(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
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(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
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"In Thumb state the core registers @code{r0}-@code{r7}.")
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"In Thumb state the core registers @code{r0}-@code{r7}.")
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(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
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(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
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"In Thumb state the core registers @code{r8}-@code{r15}.")
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"In Thumb state the core registers @code{r8}-@code{r15}.")
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(define_register_constraint "k" "TARGET_THUMB ? STACK_REG : NO_REGS"
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(define_register_constraint "k" "TARGET_THUMB ? STACK_REG : NO_REGS"
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"@internal
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"@internal
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Thumb only. The stack register.")
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Thumb only. The stack register.")
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(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
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(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
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"@internal
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"@internal
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Thumb only. The union of the low registers and the stack register.")
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Thumb only. The union of the low registers and the stack register.")
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(define_register_constraint "c" "CC_REG"
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(define_register_constraint "c" "CC_REG"
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"@internal The condition code register.")
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"@internal The condition code register.")
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(define_constraint "I"
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(define_constraint "I"
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"In ARM state a constant that can be used as an immediate value in a Data
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"In ARM state a constant that can be used as an immediate value in a Data
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Processing instruction. In Thumb state a constant in the range 0-255."
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Processing instruction. In Thumb state a constant in the range 0-255."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_ARM ? const_ok_for_arm (ival)
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(match_test "TARGET_ARM ? const_ok_for_arm (ival)
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: ival >= 0 && ival <= 255")))
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: ival >= 0 && ival <= 255")))
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(define_constraint "J"
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(define_constraint "J"
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"In ARM state a constant in the range @minus{}4095-4095. In Thumb state
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"In ARM state a constant in the range @minus{}4095-4095. In Thumb state
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a constant in the range @minus{}255-@minus{}1."
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a constant in the range @minus{}255-@minus{}1."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_ARM ? (ival >= -4095 && ival <= 4095)
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(match_test "TARGET_ARM ? (ival >= -4095 && ival <= 4095)
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: (ival >= -255 && ival <= -1)")))
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: (ival >= -255 && ival <= -1)")))
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(define_constraint "K"
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(define_constraint "K"
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"In ARM state a constant that satisfies the @code{I} constraint if inverted.
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"In ARM state a constant that satisfies the @code{I} constraint if inverted.
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In Thumb state a constant that satisfies the @code{I} constraint multiplied
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In Thumb state a constant that satisfies the @code{I} constraint multiplied
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by any power of 2."
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by any power of 2."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_ARM ? const_ok_for_arm (~ival)
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(match_test "TARGET_ARM ? const_ok_for_arm (~ival)
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: thumb_shiftable_const (ival)")))
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: thumb_shiftable_const (ival)")))
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(define_constraint "L"
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(define_constraint "L"
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"In ARM state a constant that satisfies the @code{I} constraint if negated.
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"In ARM state a constant that satisfies the @code{I} constraint if negated.
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In Thumb state a constant in the range @minus{}7-7."
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In Thumb state a constant in the range @minus{}7-7."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_ARM ? const_ok_for_arm (-ival)
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(match_test "TARGET_ARM ? const_ok_for_arm (-ival)
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: (ival >= -7 && ival <= 7)")))
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: (ival >= -7 && ival <= 7)")))
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;; The ARM state version is internal...
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;; The ARM state version is internal...
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;; @internal In ARM state a constant in the range 0-32 or any power of 2.
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;; @internal In ARM state a constant in the range 0-32 or any power of 2.
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(define_constraint "M"
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(define_constraint "M"
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"In Thumb state a constant that is a multiple of 4 in the range 0-1020."
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"In Thumb state a constant that is a multiple of 4 in the range 0-1020."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_ARM ? ((ival >= 0 && ival <= 32)
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(match_test "TARGET_ARM ? ((ival >= 0 && ival <= 32)
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|| ((ival & (ival - 1)) == 0))
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|| ((ival & (ival - 1)) == 0))
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: ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))")))
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: ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))")))
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(define_constraint "N"
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(define_constraint "N"
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"In Thumb state a constant in the range 0-31."
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"In Thumb state a constant in the range 0-31."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB && ival >= 0 && ival <= 31")))
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(match_test "TARGET_THUMB && ival >= 0 && ival <= 31")))
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(define_constraint "O"
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(define_constraint "O"
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"In Thumb state a constant that is a multiple of 4 in the range
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"In Thumb state a constant that is a multiple of 4 in the range
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@minus{}508-508."
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@minus{}508-508."
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "TARGET_THUMB && ival >= -508 && ival <= 508
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(match_test "TARGET_THUMB && ival >= -508 && ival <= 508
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&& ((ival & 3) == 0)")))
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&& ((ival & 3) == 0)")))
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(define_constraint "G"
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(define_constraint "G"
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"In ARM state a valid FPA immediate constant."
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"In ARM state a valid FPA immediate constant."
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(and (match_code "const_double")
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(and (match_code "const_double")
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(match_test "TARGET_ARM && arm_const_double_rtx (op)")))
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(match_test "TARGET_ARM && arm_const_double_rtx (op)")))
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(define_constraint "H"
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(define_constraint "H"
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"In ARM state a valid FPA immediate constant when negated."
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"In ARM state a valid FPA immediate constant when negated."
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(and (match_code "const_double")
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(and (match_code "const_double")
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(match_test "TARGET_ARM && neg_const_double_rtx_ok_for_fpa (op)")))
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(match_test "TARGET_ARM && neg_const_double_rtx_ok_for_fpa (op)")))
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(define_constraint "Da"
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(define_constraint "Da"
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"@internal
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"@internal
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In ARM state a const_int, const_double or const_vector that can
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In ARM state a const_int, const_double or const_vector that can
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be generated with two Data Processing insns."
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be generated with two Data Processing insns."
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(and (match_code "const_double,const_int,const_vector")
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(and (match_code "const_double,const_int,const_vector")
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(match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 2")))
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(match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 2")))
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(define_constraint "Db"
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(define_constraint "Db"
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"@internal
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"@internal
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In ARM state a const_int, const_double or const_vector that can
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In ARM state a const_int, const_double or const_vector that can
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be generated with three Data Processing insns."
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be generated with three Data Processing insns."
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(and (match_code "const_double,const_int,const_vector")
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(and (match_code "const_double,const_int,const_vector")
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(match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 3")))
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(match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 3")))
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(define_constraint "Dc"
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(define_constraint "Dc"
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"@internal
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"@internal
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In ARM state a const_int, const_double or const_vector that can
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In ARM state a const_int, const_double or const_vector that can
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be generated with four Data Processing insns. This pattern is disabled
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be generated with four Data Processing insns. This pattern is disabled
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if optimizing for space or when we have load-delay slots to fill."
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if optimizing for space or when we have load-delay slots to fill."
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(and (match_code "const_double,const_int,const_vector")
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(and (match_code "const_double,const_int,const_vector")
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(match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 4
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(match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 4
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&& !(optimize_size || arm_ld_sched)")))
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&& !(optimize_size || arm_ld_sched)")))
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(define_memory_constraint "Uv"
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(define_memory_constraint "Uv"
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"@internal
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"@internal
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In ARM state a valid VFP load/store address."
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In ARM state a valid VFP load/store address."
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(and (match_code "mem")
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(and (match_code "mem")
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(match_test "TARGET_ARM && arm_coproc_mem_operand (op, FALSE)")))
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(match_test "TARGET_ARM && arm_coproc_mem_operand (op, FALSE)")))
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(define_memory_constraint "Uy"
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(define_memory_constraint "Uy"
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"@internal
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"@internal
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In ARM state a valid iWMMX load/store address."
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In ARM state a valid iWMMX load/store address."
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(and (match_code "mem")
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(and (match_code "mem")
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(match_test "TARGET_ARM && arm_coproc_mem_operand (op, TRUE)")))
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(match_test "TARGET_ARM && arm_coproc_mem_operand (op, TRUE)")))
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(define_memory_constraint "Uq"
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(define_memory_constraint "Uq"
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"@internal
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"@internal
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In ARM state an address valid in ldrsb instructions."
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In ARM state an address valid in ldrsb instructions."
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(and (match_code "mem")
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(and (match_code "mem")
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(match_test "TARGET_ARM
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(match_test "TARGET_ARM
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&& arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
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&& arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
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SIGN_EXTEND, 0)")))
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SIGN_EXTEND, 0)")))
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(define_memory_constraint "Q"
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(define_memory_constraint "Q"
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"@internal
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"@internal
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In ARM state an address that is a single base register."
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In ARM state an address that is a single base register."
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(and (match_code "mem")
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(and (match_code "mem")
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(match_test "REG_P (XEXP (op, 0))")))
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(match_test "REG_P (XEXP (op, 0))")))
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;; We used to have constraint letters for S and R in ARM state, but
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;; We used to have constraint letters for S and R in ARM state, but
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;; all uses of these now appear to have been removed.
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;; all uses of these now appear to have been removed.
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;; Additionally, we used to have a Q constraint in Thumb state, but
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;; Additionally, we used to have a Q constraint in Thumb state, but
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;; this wasn't really a valid memory constraint. Again, all uses of
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;; this wasn't really a valid memory constraint. Again, all uses of
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;; this now seem to have been removed.
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;; this now seem to have been removed.
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