OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [arm/] [libunwind.S] - Diff between revs 38 and 154

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 38 Rev 154
/* Support functions for the unwinder.
/* Support functions for the unwinder.
   Copyright (C) 2003, 2004, 2005  Free Software Foundation, Inc.
   Copyright (C) 2003, 2004, 2005  Free Software Foundation, Inc.
   Contributed by Paul Brook
   Contributed by Paul Brook
   This file is free software; you can redistribute it and/or modify it
   This file is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the
   under the terms of the GNU General Public License as published by the
   Free Software Foundation; either version 2, or (at your option) any
   Free Software Foundation; either version 2, or (at your option) any
   later version.
   later version.
   In addition to the permissions in the GNU General Public License, the
   In addition to the permissions in the GNU General Public License, the
   Free Software Foundation gives you unlimited permission to link the
   Free Software Foundation gives you unlimited permission to link the
   compiled version of this file into combinations with other programs,
   compiled version of this file into combinations with other programs,
   and to distribute those combinations without any restriction coming
   and to distribute those combinations without any restriction coming
   from the use of this file.  (The General Public License restrictions
   from the use of this file.  (The General Public License restrictions
   do apply in other respects; for example, they cover modification of
   do apply in other respects; for example, they cover modification of
   the file, and distribution when not linked into a combine
   the file, and distribution when not linked into a combine
   executable.)
   executable.)
   This file is distributed in the hope that it will be useful, but
   This file is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   General Public License for more details.
   General Public License for more details.
   You should have received a copy of the GNU General Public License
   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING.  If not, write to
   along with this program; see the file COPYING.  If not, write to
   the Free Software Foundation, 51 Franklin Street, Fifth Floor,
   the Free Software Foundation, 51 Franklin Street, Fifth Floor,
   Boston, MA 02110-1301, USA.  */
   Boston, MA 02110-1301, USA.  */
#ifndef __symbian__
#ifndef __symbian__
#include "lib1funcs.asm"
#include "lib1funcs.asm"
.macro UNPREFIX name
.macro UNPREFIX name
        .global SYM (\name)
        .global SYM (\name)
        EQUIV SYM (\name), SYM (__\name)
        EQUIV SYM (\name), SYM (__\name)
.endm
.endm
/* r0 points to a 16-word block.  Upload these values to the actual core
/* r0 points to a 16-word block.  Upload these values to the actual core
   state.  */
   state.  */
ARM_FUNC_START restore_core_regs
ARM_FUNC_START restore_core_regs
        /* We must use sp as the base register when restoring sp.  Push the
        /* We must use sp as the base register when restoring sp.  Push the
           last 3 registers onto the top of the current stack to achieve
           last 3 registers onto the top of the current stack to achieve
           this.  */
           this.  */
        add r1, r0, #52
        add r1, r0, #52
        ldmia r1, {r3, r4, r5}  /* {sp, lr, pc}.  */
        ldmia r1, {r3, r4, r5}  /* {sp, lr, pc}.  */
#ifdef __INTERWORKING__
#ifdef __INTERWORKING__
        /* Restore pc into ip.  */
        /* Restore pc into ip.  */
        mov r2, r5
        mov r2, r5
        stmfd sp!, {r2, r3, r4}
        stmfd sp!, {r2, r3, r4}
#else
#else
        stmfd sp!, {r3, r4, r5}
        stmfd sp!, {r3, r4, r5}
#endif
#endif
        /* Don't bother restoring ip.  */
        /* Don't bother restoring ip.  */
        ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp}
        ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp}
        /* Pop the three registers we pushed earlier.  */
        /* Pop the three registers we pushed earlier.  */
#ifdef __INTERWORKING__
#ifdef __INTERWORKING__
        ldmfd sp, {ip, sp, lr}
        ldmfd sp, {ip, sp, lr}
        bx ip
        bx ip
#else
#else
        ldmfd sp, {sp, lr, pc}
        ldmfd sp, {sp, lr, pc}
#endif
#endif
        FUNC_END restore_core_regs
        FUNC_END restore_core_regs
        UNPREFIX restore_core_regs
        UNPREFIX restore_core_regs
/* Load VFP registers d0-d15 from the address in r0.  */
/* Load VFP registers d0-d15 from the address in r0.  */
ARM_FUNC_START gnu_Unwind_Restore_VFP
ARM_FUNC_START gnu_Unwind_Restore_VFP
        /* Use the generic coprocessor form so that gas doesn't complain
        /* Use the generic coprocessor form so that gas doesn't complain
           on soft-float targets.  */
           on soft-float targets.  */
        ldc   p11,cr0,[r0],{0x21} /* fldmiax r0, {d0-d15} */
        ldc   p11,cr0,[r0],{0x21} /* fldmiax r0, {d0-d15} */
        RET
        RET
/* Store VFR regsters d0-d15 to the address in r0.  */
/* Store VFR regsters d0-d15 to the address in r0.  */
ARM_FUNC_START gnu_Unwind_Save_VFP
ARM_FUNC_START gnu_Unwind_Save_VFP
        /* Use the generic coprocessor form so that gas doesn't complain
        /* Use the generic coprocessor form so that gas doesn't complain
           on soft-float targets.  */
           on soft-float targets.  */
        stc   p11,cr0,[r0],{0x21} /* fstmiax r0, {d0-d15} */
        stc   p11,cr0,[r0],{0x21} /* fstmiax r0, {d0-d15} */
        RET
        RET
/* Wrappers to save core registers, then call the real routine.   */
/* Wrappers to save core registers, then call the real routine.   */
.macro  UNWIND_WRAPPER name nargs
.macro  UNWIND_WRAPPER name nargs
        ARM_FUNC_START \name
        ARM_FUNC_START \name
        /* Create a phase2_vrs structure.  */
        /* Create a phase2_vrs structure.  */
        /* Split reg push in two to ensure the correct value for sp.  */
        /* Split reg push in two to ensure the correct value for sp.  */
        stmfd sp!, {sp, lr, pc}
        stmfd sp!, {sp, lr, pc}
        stmfd sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
        stmfd sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
        /* Demand-save flags, plus an extra word for alignment.  */
        /* Demand-save flags, plus an extra word for alignment.  */
        mov r3, #0
        mov r3, #0
        stmfd sp!, {r2, r3}
        stmfd sp!, {r2, r3}
        /* Point r1 at the block.  Pass r[0..nargs) unchanged.  */
        /* Point r1 at the block.  Pass r[0..nargs) unchanged.  */
        add r\nargs, sp, #4
        add r\nargs, sp, #4
#if defined(__thumb__)
#if defined(__thumb__)
        /* Switch back to thumb mode to avoid interworking hassle.  */
        /* Switch back to thumb mode to avoid interworking hassle.  */
        adr ip, .L1_\name
        adr ip, .L1_\name
        orr ip, ip, #1
        orr ip, ip, #1
        bx ip
        bx ip
        .thumb
        .thumb
.L1_\name:
.L1_\name:
        bl SYM (__gnu\name) __PLT__
        bl SYM (__gnu\name) __PLT__
        ldr r3, [sp, #64]
        ldr r3, [sp, #64]
        add sp, #72
        add sp, #72
        bx r3
        bx r3
#else
#else
        bl SYM (__gnu\name) __PLT__
        bl SYM (__gnu\name) __PLT__
        ldr lr, [sp, #64]
        ldr lr, [sp, #64]
        add sp, sp, #72
        add sp, sp, #72
        RET
        RET
#endif
#endif
        FUNC_END \name
        FUNC_END \name
        UNPREFIX \name
        UNPREFIX \name
.endm
.endm
UNWIND_WRAPPER _Unwind_RaiseException 1
UNWIND_WRAPPER _Unwind_RaiseException 1
UNWIND_WRAPPER _Unwind_Resume 1
UNWIND_WRAPPER _Unwind_Resume 1
UNWIND_WRAPPER _Unwind_Resume_or_Rethrow 1
UNWIND_WRAPPER _Unwind_Resume_or_Rethrow 1
UNWIND_WRAPPER _Unwind_ForcedUnwind 3
UNWIND_WRAPPER _Unwind_ForcedUnwind 3
#endif  /* __symbian__ */
#endif  /* __symbian__ */
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.