/* Definitions of target machine for GNU compiler. TMS320C[34]x
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/* Definitions of target machine for GNU compiler. TMS320C[34]x
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Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
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Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
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2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
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Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
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and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
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and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
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This file is part of GCC.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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GCC is distributed in the hope that it will be useful,
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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<http://www.gnu.org/licenses/>. */
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/* RUN-TIME TARGET SPECIFICATION. */
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/* RUN-TIME TARGET SPECIFICATION. */
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#define C4x 1
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#define C4x 1
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#define TARGET_CPU_CPP_BUILTINS() \
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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do \
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{ \
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{ \
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extern int flag_inline_trees; \
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extern int flag_inline_trees; \
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if (!TARGET_SMALL) \
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if (!TARGET_SMALL) \
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builtin_define ("_BIGMODEL"); \
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builtin_define ("_BIGMODEL"); \
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if (!TARGET_MEMPARM) \
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if (!TARGET_MEMPARM) \
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builtin_define ("_REGPARM"); \
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builtin_define ("_REGPARM"); \
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if (flag_inline_functions) \
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if (flag_inline_functions) \
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builtin_define ("_INLINE"); \
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builtin_define ("_INLINE"); \
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if (TARGET_C3X) \
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if (TARGET_C3X) \
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{ \
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{ \
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builtin_define ("_TMS320C3x"); \
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builtin_define ("_TMS320C3x"); \
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builtin_define ("_C3x"); \
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builtin_define ("_C3x"); \
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if (TARGET_C30) \
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if (TARGET_C30) \
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{ \
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{ \
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builtin_define ("_TMS320C30"); \
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builtin_define ("_TMS320C30"); \
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builtin_define ("_C30"); \
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builtin_define ("_C30"); \
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} \
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} \
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else if (TARGET_C31) \
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else if (TARGET_C31) \
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{ \
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{ \
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builtin_define ("_TMS320C31"); \
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builtin_define ("_TMS320C31"); \
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builtin_define ("_C31"); \
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builtin_define ("_C31"); \
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} \
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} \
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else if (TARGET_C32) \
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else if (TARGET_C32) \
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{ \
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{ \
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builtin_define ("_TMS320C32"); \
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builtin_define ("_TMS320C32"); \
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builtin_define ("_C32"); \
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builtin_define ("_C32"); \
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} \
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} \
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else if (TARGET_C33) \
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else if (TARGET_C33) \
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{ \
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{ \
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builtin_define ("_TMS320C33"); \
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builtin_define ("_TMS320C33"); \
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builtin_define ("_C33"); \
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builtin_define ("_C33"); \
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} \
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} \
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} \
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} \
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else \
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else \
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{ \
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{ \
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builtin_define ("_TMS320C4x"); \
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builtin_define ("_TMS320C4x"); \
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builtin_define ("_C4x"); \
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builtin_define ("_C4x"); \
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if (TARGET_C40) \
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if (TARGET_C40) \
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{ \
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{ \
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builtin_define ("_TMS320C40"); \
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builtin_define ("_TMS320C40"); \
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builtin_define ("_C40"); \
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builtin_define ("_C40"); \
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} \
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} \
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else if (TARGET_C44) \
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else if (TARGET_C44) \
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{ \
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{ \
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builtin_define ("_TMS320C44"); \
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builtin_define ("_TMS320C44"); \
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builtin_define ("_C44"); \
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builtin_define ("_C44"); \
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} \
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} \
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} \
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} \
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} \
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} \
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while (0)
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while (0)
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/* Define assembler options. */
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/* Define assembler options. */
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#define ASM_SPEC "\
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#define ASM_SPEC "\
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%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
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%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
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%{!m30:%{!m31:%{!m32:%{!m33:%{!m40:%{!m44:-m40}}}}}}}}}}}} \
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%{!m30:%{!m31:%{!m32:%{!m33:%{!m40:%{!m44:-m40}}}}}}}}}}}} \
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%{mcpu=30} \
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%{mcpu=30} \
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%{mcpu=31} \
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%{mcpu=31} \
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%{mcpu=32} \
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%{mcpu=32} \
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%{mcpu=33} \
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%{mcpu=33} \
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%{mcpu=40} \
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%{mcpu=40} \
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%{mcpu=44} \
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%{mcpu=44} \
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%{m30} \
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%{m30} \
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%{m31} \
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%{m31} \
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%{m32} \
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%{m32} \
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%{m33} \
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%{m33} \
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%{m40} \
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%{m40} \
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%{m44} \
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%{m44} \
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%{mmemparm} %{mregparm} %{!mmemparm:%{!mregparm:-mregparm}} \
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%{mmemparm} %{mregparm} %{!mmemparm:%{!mregparm:-mregparm}} \
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%{mbig} %{msmall} %{!msmall:%{!mbig:-mbig}}"
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%{mbig} %{msmall} %{!msmall:%{!mbig:-mbig}}"
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/* Define linker options. */
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/* Define linker options. */
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#define LINK_SPEC "\
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#define LINK_SPEC "\
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%{m30:--architecture c3x} \
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%{m30:--architecture c3x} \
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%{m31:--architecture c3x} \
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%{m31:--architecture c3x} \
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%{m32:--architecture c3x} \
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%{m32:--architecture c3x} \
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%{m33:--architecture c3x} \
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%{m33:--architecture c3x} \
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%{mcpu=30:--architecture c3x} \
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%{mcpu=30:--architecture c3x} \
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%{mcpu=31:--architecture c3x} \
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%{mcpu=31:--architecture c3x} \
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%{mcpu=32:--architecture c3x} \
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%{mcpu=32:--architecture c3x} \
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%{mcpu=33:--architecture c3x}"
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%{mcpu=33:--architecture c3x}"
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/* Specify the end file to link with. */
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/* Specify the end file to link with. */
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#define ENDFILE_SPEC ""
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#define ENDFILE_SPEC ""
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/* Caveats:
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/* Caveats:
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Max iteration count for RPTB/RPTS is 2^31 + 1.
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Max iteration count for RPTB/RPTS is 2^31 + 1.
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Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
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Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
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RPTS blocks interrupts. */
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RPTS blocks interrupts. */
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extern int c4x_cpu_version; /* Cpu version C30/31/32/33/40/44. */
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extern int c4x_cpu_version; /* Cpu version C30/31/32/33/40/44. */
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#define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
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#define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
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#define TARGET_SMALL_REG_CLASS 0
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#define TARGET_SMALL_REG_CLASS 0
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#define TARGET_C3X (c4x_cpu_version >= 30 \
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#define TARGET_C3X (c4x_cpu_version >= 30 \
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&& c4x_cpu_version <= 39)
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&& c4x_cpu_version <= 39)
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#define TARGET_C30 (c4x_cpu_version == 30)
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#define TARGET_C30 (c4x_cpu_version == 30)
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#define TARGET_C31 (c4x_cpu_version == 31)
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#define TARGET_C31 (c4x_cpu_version == 31)
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#define TARGET_C32 (c4x_cpu_version == 32)
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#define TARGET_C32 (c4x_cpu_version == 32)
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#define TARGET_C33 (c4x_cpu_version == 33)
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#define TARGET_C33 (c4x_cpu_version == 33)
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#define TARGET_C40 (c4x_cpu_version == 40)
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#define TARGET_C40 (c4x_cpu_version == 40)
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#define TARGET_C44 (c4x_cpu_version == 44)
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#define TARGET_C44 (c4x_cpu_version == 44)
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/* Nonzero to use load_immed_addr pattern rather than forcing memory
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/* Nonzero to use load_immed_addr pattern rather than forcing memory
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addresses into memory. */
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addresses into memory. */
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#define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
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#define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
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/* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
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/* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
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during RTL generation. */
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during RTL generation. */
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#define TARGET_EXPOSE_LDP 0
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#define TARGET_EXPOSE_LDP 0
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/* Nonzero to force loading of direct memory references into a register. */
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/* Nonzero to force loading of direct memory references into a register. */
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#define TARGET_LOAD_DIRECT_MEMS 0
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#define TARGET_LOAD_DIRECT_MEMS 0
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/* -mrpts allows the use of the RPTS instruction irregardless.
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/* -mrpts allows the use of the RPTS instruction irregardless.
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-mrpts=max-cycles will use RPTS if the number of cycles is constant
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-mrpts=max-cycles will use RPTS if the number of cycles is constant
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and less than max-cycles. */
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and less than max-cycles. */
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#define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
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#define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
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/* Sometimes certain combinations of command options do not make sense
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/* Sometimes certain combinations of command options do not make sense
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on a particular target machine. You can define a macro
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on a particular target machine. You can define a macro
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`OVERRIDE_OPTIONS' to take account of this. This macro, if
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`OVERRIDE_OPTIONS' to take account of this. This macro, if
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defined, is executed once just after all the command options have
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defined, is executed once just after all the command options have
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been parsed. */
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been parsed. */
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#define OVERRIDE_OPTIONS c4x_override_options ()
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#define OVERRIDE_OPTIONS c4x_override_options ()
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/* Define this to change the optimizations performed by default. */
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/* Define this to change the optimizations performed by default. */
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#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
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#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
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/* Run Time Target Specification. */
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/* Run Time Target Specification. */
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#define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
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#define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
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/* Storage Layout. */
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/* Storage Layout. */
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#define BITS_BIG_ENDIAN 0
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#define BITS_BIG_ENDIAN 0
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#define BYTES_BIG_ENDIAN 0
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#define BYTES_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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/* Technically, we are little endian, but we put the floats out as
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/* Technically, we are little endian, but we put the floats out as
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whole longs and this makes GCC put them out in the right order. */
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whole longs and this makes GCC put them out in the right order. */
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#define FLOAT_WORDS_BIG_ENDIAN 1
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#define FLOAT_WORDS_BIG_ENDIAN 1
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/* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
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/* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
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all integral and floating point data types are stored in memory as
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all integral and floating point data types are stored in memory as
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32-bits (floating point types can be stored as 40-bits in the
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32-bits (floating point types can be stored as 40-bits in the
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extended precision registers), so sizeof(char) = sizeof(short) =
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extended precision registers), so sizeof(char) = sizeof(short) =
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sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
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sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
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#define BITS_PER_UNIT 32
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#define BITS_PER_UNIT 32
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#define UNITS_PER_WORD 1
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#define UNITS_PER_WORD 1
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#define PARM_BOUNDARY 32
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#define PARM_BOUNDARY 32
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#define STACK_BOUNDARY 32
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#define STACK_BOUNDARY 32
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#define FUNCTION_BOUNDARY 32
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#define FUNCTION_BOUNDARY 32
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#define BIGGEST_ALIGNMENT 32
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#define BIGGEST_ALIGNMENT 32
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#define EMPTY_FIELD_BOUNDARY 32
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#define EMPTY_FIELD_BOUNDARY 32
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#define STRICT_ALIGNMENT 0
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#define STRICT_ALIGNMENT 0
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#define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
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#define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
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#define MAX_FIXED_MODE_SIZE 64 /* HImode. */
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#define MAX_FIXED_MODE_SIZE 64 /* HImode. */
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/* If a structure has a floating point field then force structure
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/* If a structure has a floating point field then force structure
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to have BLKMODE, unless it is the only field. */
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to have BLKMODE, unless it is the only field. */
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#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
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#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
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(TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode)
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(TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode)
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/* Number of bits in the high and low parts of a two stage
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/* Number of bits in the high and low parts of a two stage
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load of an immediate constant. */
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load of an immediate constant. */
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#define BITS_PER_HIGH 16
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#define BITS_PER_HIGH 16
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#define BITS_PER_LO_SUM 16
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#define BITS_PER_LO_SUM 16
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/* Define register numbers. */
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/* Define register numbers. */
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/* Extended-precision registers. */
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/* Extended-precision registers. */
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#define R0_REGNO 0
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#define R0_REGNO 0
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#define R1_REGNO 1
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#define R1_REGNO 1
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#define R2_REGNO 2
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#define R2_REGNO 2
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#define R3_REGNO 3
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#define R3_REGNO 3
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#define R4_REGNO 4
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#define R4_REGNO 4
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#define R5_REGNO 5
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#define R5_REGNO 5
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#define R6_REGNO 6
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#define R6_REGNO 6
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#define R7_REGNO 7
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#define R7_REGNO 7
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/* Auxiliary (address) registers. */
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/* Auxiliary (address) registers. */
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#define AR0_REGNO 8
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#define AR0_REGNO 8
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#define AR1_REGNO 9
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#define AR1_REGNO 9
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#define AR2_REGNO 10
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#define AR2_REGNO 10
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#define AR3_REGNO 11
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#define AR3_REGNO 11
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#define AR4_REGNO 12
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#define AR4_REGNO 12
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#define AR5_REGNO 13
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#define AR5_REGNO 13
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#define AR6_REGNO 14
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#define AR6_REGNO 14
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#define AR7_REGNO 15
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#define AR7_REGNO 15
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/* Data page register. */
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/* Data page register. */
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#define DP_REGNO 16
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#define DP_REGNO 16
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/* Index registers. */
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/* Index registers. */
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#define IR0_REGNO 17
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#define IR0_REGNO 17
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#define IR1_REGNO 18
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#define IR1_REGNO 18
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/* Block size register. */
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/* Block size register. */
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#define BK_REGNO 19
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#define BK_REGNO 19
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/* Stack pointer. */
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/* Stack pointer. */
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#define SP_REGNO 20
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#define SP_REGNO 20
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/* Status register. */
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/* Status register. */
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#define ST_REGNO 21
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#define ST_REGNO 21
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/* Misc. interrupt registers. */
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/* Misc. interrupt registers. */
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#define DIE_REGNO 22 /* C4x only. */
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#define DIE_REGNO 22 /* C4x only. */
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#define IE_REGNO 22 /* C3x only. */
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#define IE_REGNO 22 /* C3x only. */
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#define IIE_REGNO 23 /* C4x only. */
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#define IIE_REGNO 23 /* C4x only. */
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#define IF_REGNO 23 /* C3x only. */
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#define IF_REGNO 23 /* C3x only. */
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#define IIF_REGNO 24 /* C4x only. */
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#define IIF_REGNO 24 /* C4x only. */
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#define IOF_REGNO 24 /* C3x only. */
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#define IOF_REGNO 24 /* C3x only. */
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/* Repeat block registers. */
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/* Repeat block registers. */
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#define RS_REGNO 25
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#define RS_REGNO 25
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#define RE_REGNO 26
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#define RE_REGNO 26
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#define RC_REGNO 27
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#define RC_REGNO 27
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/* Additional extended-precision registers. */
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/* Additional extended-precision registers. */
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#define R8_REGNO 28 /* C4x only. */
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#define R8_REGNO 28 /* C4x only. */
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#define R9_REGNO 29 /* C4x only. */
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#define R9_REGNO 29 /* C4x only. */
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#define R10_REGNO 30 /* C4x only. */
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#define R10_REGNO 30 /* C4x only. */
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#define R11_REGNO 31 /* C4x only. */
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#define R11_REGNO 31 /* C4x only. */
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#define FIRST_PSEUDO_REGISTER 32
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#define FIRST_PSEUDO_REGISTER 32
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/* Extended precision registers (low set). */
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/* Extended precision registers (low set). */
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#define IS_R0R1_REGNO(r) \
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#define IS_R0R1_REGNO(r) \
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((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
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((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
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#define IS_R2R3_REGNO(r) \
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#define IS_R2R3_REGNO(r) \
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((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
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((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
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#define IS_EXT_LOW_REGNO(r) \
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#define IS_EXT_LOW_REGNO(r) \
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((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
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((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
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|
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/* Extended precision registers (high set). */
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/* Extended precision registers (high set). */
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#define IS_EXT_HIGH_REGNO(r) \
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#define IS_EXT_HIGH_REGNO(r) \
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(! TARGET_C3X \
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(! TARGET_C3X \
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&& ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
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&& ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
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|
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/* Address registers. */
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/* Address registers. */
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#define IS_AUX_REGNO(r) \
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#define IS_AUX_REGNO(r) \
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((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
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((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
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#define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
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#define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
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#define IS_DP_REGNO(r) ((r) == DP_REGNO)
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#define IS_DP_REGNO(r) ((r) == DP_REGNO)
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#define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
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#define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
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#define IS_SP_REGNO(r) ((r) == SP_REGNO)
|
#define IS_SP_REGNO(r) ((r) == SP_REGNO)
|
#define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
|
#define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
|
|
|
/* Misc registers. */
|
/* Misc registers. */
|
|
|
#define IS_ST_REGNO(r) ((r) == ST_REGNO)
|
#define IS_ST_REGNO(r) ((r) == ST_REGNO)
|
#define IS_RC_REGNO(r) ((r) == RC_REGNO)
|
#define IS_RC_REGNO(r) ((r) == RC_REGNO)
|
#define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
|
#define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
|
|
|
/* Composite register sets. */
|
/* Composite register sets. */
|
|
|
#define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
|
#define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
|
#define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
|
#define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
|
#define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
|
#define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
|
|| IS_REPEAT_REGNO(r) \
|
|| IS_REPEAT_REGNO(r) \
|
|| IS_SP_REGNO(r) \
|
|| IS_SP_REGNO(r) \
|
|| IS_BK_REGNO(r))
|
|| IS_BK_REGNO(r))
|
#define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
|
#define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
|
#define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
|
#define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
|
#define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \
|
#define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \
|
|| ((r) == R8_REGNO))
|
|| ((r) == R8_REGNO))
|
#define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO))
|
#define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO))
|
|
|
#define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
|
#define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
|
#define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
|
#define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
|
|| IS_PSEUDO_REGNO(r))
|
|| IS_PSEUDO_REGNO(r))
|
#define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
|
#define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
|
|
|
#define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
|
#define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
|
#define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
|
#define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
|
#define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
|
#define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
|
#define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
|
#define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
|
#define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
|
#define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
|
#define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
|
#define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
|
#define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
|
#define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
|
|
|
#define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
|
|
|
#define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
|
#define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
|
|
|
/* 1 for registers that have pervasive standard uses
|
/* 1 for registers that have pervasive standard uses
|
and are not available for the register allocator. */
|
and are not available for the register allocator. */
|
|
|
#define FIXED_REGISTERS \
|
#define FIXED_REGISTERS \
|
{ \
|
{ \
|
/* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
|
/* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
/* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
|
/* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
|
1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
|
1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
|
}
|
}
|
|
|
/* 1 for registers not available across function calls.
|
/* 1 for registers not available across function calls.
|
These must include the FIXED_REGISTERS and also any
|
These must include the FIXED_REGISTERS and also any
|
registers that can be used without being saved.
|
registers that can be used without being saved.
|
The latter must include the registers where values are returned
|
The latter must include the registers where values are returned
|
and the register where structure-value addresses are passed.
|
and the register where structure-value addresses are passed.
|
Aside from that, you can include as many other registers as you like.
|
Aside from that, you can include as many other registers as you like.
|
|
|
Note that the extended precision registers are only saved in some
|
Note that the extended precision registers are only saved in some
|
modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
|
modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
|
get clobbered for a given regno. */
|
get clobbered for a given regno. */
|
|
|
#define CALL_USED_REGISTERS \
|
#define CALL_USED_REGISTERS \
|
{ \
|
{ \
|
/* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
|
/* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
|
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
|
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
|
/* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
|
/* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
|
}
|
}
|
|
|
/* Macro to conditionally modify fixed_regs/call_used_regs. */
|
/* Macro to conditionally modify fixed_regs/call_used_regs. */
|
|
|
#define CONDITIONAL_REGISTER_USAGE \
|
#define CONDITIONAL_REGISTER_USAGE \
|
{ \
|
{ \
|
if (! TARGET_BK) \
|
if (! TARGET_BK) \
|
{ \
|
{ \
|
fixed_regs[BK_REGNO] = 1; \
|
fixed_regs[BK_REGNO] = 1; \
|
call_used_regs[BK_REGNO] = 1; \
|
call_used_regs[BK_REGNO] = 1; \
|
c4x_regclass_map[BK_REGNO] = NO_REGS; \
|
c4x_regclass_map[BK_REGNO] = NO_REGS; \
|
} \
|
} \
|
if (TARGET_C3X) \
|
if (TARGET_C3X) \
|
{ \
|
{ \
|
int i; \
|
int i; \
|
\
|
\
|
reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \
|
reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \
|
reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \
|
reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \
|
reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \
|
reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \
|
\
|
\
|
for (i = R8_REGNO; i <= R11_REGNO; i++) \
|
for (i = R8_REGNO; i <= R11_REGNO; i++) \
|
{ \
|
{ \
|
fixed_regs[i] = call_used_regs[i] = 1; \
|
fixed_regs[i] = call_used_regs[i] = 1; \
|
c4x_regclass_map[i] = NO_REGS; \
|
c4x_regclass_map[i] = NO_REGS; \
|
} \
|
} \
|
} \
|
} \
|
if (TARGET_PRESERVE_FLOAT) \
|
if (TARGET_PRESERVE_FLOAT) \
|
{ \
|
{ \
|
c4x_caller_save_map[R6_REGNO] = HFmode; \
|
c4x_caller_save_map[R6_REGNO] = HFmode; \
|
c4x_caller_save_map[R7_REGNO] = HFmode; \
|
c4x_caller_save_map[R7_REGNO] = HFmode; \
|
} \
|
} \
|
}
|
}
|
|
|
/* Order of Allocation of Registers. */
|
/* Order of Allocation of Registers. */
|
|
|
/* List the order in which to allocate registers. Each register must be
|
/* List the order in which to allocate registers. Each register must be
|
listed once, even those in FIXED_REGISTERS.
|
listed once, even those in FIXED_REGISTERS.
|
|
|
First allocate registers that don't need preservation across calls,
|
First allocate registers that don't need preservation across calls,
|
except index and address registers. Then allocate data registers
|
except index and address registers. Then allocate data registers
|
that require preservation across calls (even though this invokes an
|
that require preservation across calls (even though this invokes an
|
extra overhead of having to save/restore these registers). Next
|
extra overhead of having to save/restore these registers). Next
|
allocate the address and index registers, since using these
|
allocate the address and index registers, since using these
|
registers for arithmetic can cause pipeline stalls. Finally
|
registers for arithmetic can cause pipeline stalls. Finally
|
allocated the fixed registers which won't be allocated anyhow. */
|
allocated the fixed registers which won't be allocated anyhow. */
|
|
|
#define REG_ALLOC_ORDER \
|
#define REG_ALLOC_ORDER \
|
{R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
|
{R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
|
R9_REGNO, R10_REGNO, R11_REGNO, \
|
R9_REGNO, R10_REGNO, R11_REGNO, \
|
RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
|
RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
|
R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
|
R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
|
AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
|
AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
|
AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
|
AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
|
IR0_REGNO, IR1_REGNO, \
|
IR0_REGNO, IR1_REGNO, \
|
SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
|
SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
|
|
|
/* A C expression that is nonzero if hard register number REGNO2 can be
|
/* A C expression that is nonzero if hard register number REGNO2 can be
|
considered for use as a rename register for REGNO1 */
|
considered for use as a rename register for REGNO1 */
|
|
|
#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
|
#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
|
c4x_hard_regno_rename_ok((REGNO1), (REGNO2))
|
c4x_hard_regno_rename_ok((REGNO1), (REGNO2))
|
|
|
/* Determine which register classes are very likely used by spill registers.
|
/* Determine which register classes are very likely used by spill registers.
|
local-alloc.c won't allocate pseudos that have these classes as their
|
local-alloc.c won't allocate pseudos that have these classes as their
|
preferred class unless they are "preferred or nothing". */
|
preferred class unless they are "preferred or nothing". */
|
|
|
#define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
|
#define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
|
|
|
/* CCmode is wrongly defined in machmode.def. It should have a size
|
/* CCmode is wrongly defined in machmode.def. It should have a size
|
of UNITS_PER_WORD. HFmode is 40-bits and thus fits within a single
|
of UNITS_PER_WORD. HFmode is 40-bits and thus fits within a single
|
extended precision register. Similarly, HCmode fits within two
|
extended precision register. Similarly, HCmode fits within two
|
extended precision registers. */
|
extended precision registers. */
|
|
|
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
(((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \
|
(((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \
|
((MODE) == HFmode) ? 1 : \
|
((MODE) == HFmode) ? 1 : \
|
((MODE) == HCmode) ? 2 : \
|
((MODE) == HCmode) ? 2 : \
|
((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
|
((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
|
|
|
|
|
/* A C expression that is nonzero if the hard register REGNO is preserved
|
/* A C expression that is nonzero if the hard register REGNO is preserved
|
across a call in mode MODE. This does not have to include the call used
|
across a call in mode MODE. This does not have to include the call used
|
registers. */
|
registers. */
|
|
|
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
|
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
|
((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \
|
((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \
|
|| (IS_INT_CALL_SAVED_REGNO (REGNO) \
|
|| (IS_INT_CALL_SAVED_REGNO (REGNO) \
|
&& ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
|
&& ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
|
|
|
/* Specify the modes required to caller save a given hard regno. */
|
/* Specify the modes required to caller save a given hard regno. */
|
|
|
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO])
|
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO])
|
|
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
|
|
|
/* A C expression that is nonzero if it is desirable to choose
|
/* A C expression that is nonzero if it is desirable to choose
|
register allocation so as to avoid move instructions between a
|
register allocation so as to avoid move instructions between a
|
value of mode MODE1 and a value of mode MODE2.
|
value of mode MODE1 and a value of mode MODE2.
|
|
|
Value is 1 if it is a good idea to tie two pseudo registers
|
Value is 1 if it is a good idea to tie two pseudo registers
|
when one has mode MODE1 and one has mode MODE2.
|
when one has mode MODE1 and one has mode MODE2.
|
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
|
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
|
for any hard reg, then this must be 0 for correct output. */
|
for any hard reg, then this must be 0 for correct output. */
|
|
|
#define MODES_TIEABLE_P(MODE1, MODE2) 0
|
#define MODES_TIEABLE_P(MODE1, MODE2) 0
|
|
|
|
|
/* Define the classes of registers for register constraints in the
|
/* Define the classes of registers for register constraints in the
|
machine description. Also define ranges of constants.
|
machine description. Also define ranges of constants.
|
|
|
One of the classes must always be named ALL_REGS and include all hard regs.
|
One of the classes must always be named ALL_REGS and include all hard regs.
|
If there is more than one class, another class must be named NO_REGS
|
If there is more than one class, another class must be named NO_REGS
|
and contain no registers.
|
and contain no registers.
|
|
|
The name GENERAL_REGS must be the name of a class (or an alias for
|
The name GENERAL_REGS must be the name of a class (or an alias for
|
another name such as ALL_REGS). This is the class of registers
|
another name such as ALL_REGS). This is the class of registers
|
that is allowed by "g" or "r" in a register constraint.
|
that is allowed by "g" or "r" in a register constraint.
|
Also, registers outside this class are allocated only when
|
Also, registers outside this class are allocated only when
|
instructions express preferences for them.
|
instructions express preferences for them.
|
|
|
The classes must be numbered in nondecreasing order; that is,
|
The classes must be numbered in nondecreasing order; that is,
|
a larger-numbered class must never be contained completely
|
a larger-numbered class must never be contained completely
|
in a smaller-numbered class.
|
in a smaller-numbered class.
|
|
|
For any two classes, it is very desirable that there be another
|
For any two classes, it is very desirable that there be another
|
class that represents their union. */
|
class that represents their union. */
|
|
|
enum reg_class
|
enum reg_class
|
{
|
{
|
NO_REGS,
|
NO_REGS,
|
R0R1_REGS, /* 't'. */
|
R0R1_REGS, /* 't'. */
|
R2R3_REGS, /* 'u'. */
|
R2R3_REGS, /* 'u'. */
|
EXT_LOW_REGS, /* 'q'. */
|
EXT_LOW_REGS, /* 'q'. */
|
EXT_REGS, /* 'f'. */
|
EXT_REGS, /* 'f'. */
|
ADDR_REGS, /* 'a'. */
|
ADDR_REGS, /* 'a'. */
|
INDEX_REGS, /* 'x'. */
|
INDEX_REGS, /* 'x'. */
|
BK_REG, /* 'k'. */
|
BK_REG, /* 'k'. */
|
SP_REG, /* 'b'. */
|
SP_REG, /* 'b'. */
|
RC_REG, /* 'v'. */
|
RC_REG, /* 'v'. */
|
COUNTER_REGS, /* */
|
COUNTER_REGS, /* */
|
INT_REGS, /* 'c'. */
|
INT_REGS, /* 'c'. */
|
GENERAL_REGS, /* 'r'. */
|
GENERAL_REGS, /* 'r'. */
|
DP_REG, /* 'z'. */
|
DP_REG, /* 'z'. */
|
ST_REG, /* 'y'. */
|
ST_REG, /* 'y'. */
|
ALL_REGS,
|
ALL_REGS,
|
LIM_REG_CLASSES
|
LIM_REG_CLASSES
|
};
|
};
|
|
|
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
|
|
#define REG_CLASS_NAMES \
|
#define REG_CLASS_NAMES \
|
{ \
|
{ \
|
"NO_REGS", \
|
"NO_REGS", \
|
"R0R1_REGS", \
|
"R0R1_REGS", \
|
"R2R3_REGS", \
|
"R2R3_REGS", \
|
"EXT_LOW_REGS", \
|
"EXT_LOW_REGS", \
|
"EXT_REGS", \
|
"EXT_REGS", \
|
"ADDR_REGS", \
|
"ADDR_REGS", \
|
"INDEX_REGS", \
|
"INDEX_REGS", \
|
"BK_REG", \
|
"BK_REG", \
|
"SP_REG", \
|
"SP_REG", \
|
"RC_REG", \
|
"RC_REG", \
|
"COUNTER_REGS", \
|
"COUNTER_REGS", \
|
"INT_REGS", \
|
"INT_REGS", \
|
"GENERAL_REGS", \
|
"GENERAL_REGS", \
|
"DP_REG", \
|
"DP_REG", \
|
"ST_REG", \
|
"ST_REG", \
|
"ALL_REGS" \
|
"ALL_REGS" \
|
}
|
}
|
|
|
/* Define which registers fit in which classes.
|
/* Define which registers fit in which classes.
|
This is an initializer for a vector of HARD_REG_SET
|
This is an initializer for a vector of HARD_REG_SET
|
of length N_REG_CLASSES. RC is not included in GENERAL_REGS
|
of length N_REG_CLASSES. RC is not included in GENERAL_REGS
|
since the register allocator will often choose a general register
|
since the register allocator will often choose a general register
|
in preference to RC for the decrement_and_branch_on_count pattern. */
|
in preference to RC for the decrement_and_branch_on_count pattern. */
|
|
|
#define REG_CLASS_CONTENTS \
|
#define REG_CLASS_CONTENTS \
|
{ \
|
{ \
|
{0x00000000}, /* No registers. */ \
|
{0x00000000}, /* No registers. */ \
|
{0x00000003}, /* 't' R0-R1 . */ \
|
{0x00000003}, /* 't' R0-R1 . */ \
|
{0x0000000c}, /* 'u' R2-R3 . */ \
|
{0x0000000c}, /* 'u' R2-R3 . */ \
|
{0x000000ff}, /* 'q' R0-R7 . */ \
|
{0x000000ff}, /* 'q' R0-R7 . */ \
|
{0xf00000ff}, /* 'f' R0-R11 */ \
|
{0xf00000ff}, /* 'f' R0-R11 */ \
|
{0x0000ff00}, /* 'a' AR0-AR7. */ \
|
{0x0000ff00}, /* 'a' AR0-AR7. */ \
|
{0x00060000}, /* 'x' IR0-IR1. */ \
|
{0x00060000}, /* 'x' IR0-IR1. */ \
|
{0x00080000}, /* 'k' BK. */ \
|
{0x00080000}, /* 'k' BK. */ \
|
{0x00100000}, /* 'b' SP. */ \
|
{0x00100000}, /* 'b' SP. */ \
|
{0x08000000}, /* 'v' RC. */ \
|
{0x08000000}, /* 'v' RC. */ \
|
{0x0800ff00}, /* RC,AR0-AR7. */ \
|
{0x0800ff00}, /* RC,AR0-AR7. */ \
|
{0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \
|
{0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \
|
{0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\
|
{0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\
|
{0x00010000}, /* 'z' DP. */ \
|
{0x00010000}, /* 'z' DP. */ \
|
{0x00200000}, /* 'y' ST. */ \
|
{0x00200000}, /* 'y' ST. */ \
|
{0xffffffff}, /* All registers. */ \
|
{0xffffffff}, /* All registers. */ \
|
}
|
}
|
|
|
/* The same information, inverted:
|
/* The same information, inverted:
|
Return the class number of the smallest class containing
|
Return the class number of the smallest class containing
|
reg number REGNO. This could be a conditional expression
|
reg number REGNO. This could be a conditional expression
|
or could index an array. */
|
or could index an array. */
|
|
|
#define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
|
#define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
|
|
|
/* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
|
/* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
|
explicitly used in the rtl is kept as short as possible.
|
explicitly used in the rtl is kept as short as possible.
|
|
|
We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
|
We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
|
is defined since the MPY|ADD insns require the classes R0R1_REGS and
|
is defined since the MPY|ADD insns require the classes R0R1_REGS and
|
R2R3_REGS which are used by the function return registers (R0,R1) and
|
R2R3_REGS which are used by the function return registers (R0,R1) and
|
the register arguments (R2,R3), respectively. I'm reluctant to define
|
the register arguments (R2,R3), respectively. I'm reluctant to define
|
this macro since it stomps on many potential optimizations. Ideally
|
this macro since it stomps on many potential optimizations. Ideally
|
it should have a register class argument so that not all the register
|
it should have a register class argument so that not all the register
|
classes gets penalized for the sake of a naughty few... For long
|
classes gets penalized for the sake of a naughty few... For long
|
double arithmetic we need two additional registers that we can use as
|
double arithmetic we need two additional registers that we can use as
|
spill registers. */
|
spill registers. */
|
|
|
#define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
|
#define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
|
|
|
#define BASE_REG_CLASS ADDR_REGS
|
#define BASE_REG_CLASS ADDR_REGS
|
#define INDEX_REG_CLASS INDEX_REGS
|
#define INDEX_REG_CLASS INDEX_REGS
|
|
|
/*
|
/*
|
Register constraints for the C4x
|
Register constraints for the C4x
|
|
|
a - address reg (ar0-ar7)
|
a - address reg (ar0-ar7)
|
b - stack reg (sp)
|
b - stack reg (sp)
|
c - other gp int-only reg
|
c - other gp int-only reg
|
d - data/int reg (equiv. to f)
|
d - data/int reg (equiv. to f)
|
f - data/float reg
|
f - data/float reg
|
h - data/long double reg (equiv. to f)
|
h - data/long double reg (equiv. to f)
|
k - block count (bk)
|
k - block count (bk)
|
q - r0-r7
|
q - r0-r7
|
t - r0-r1
|
t - r0-r1
|
u - r2-r3
|
u - r2-r3
|
v - repeat count (rc)
|
v - repeat count (rc)
|
x - index register (ir0-ir1)
|
x - index register (ir0-ir1)
|
y - status register (st)
|
y - status register (st)
|
z - dp reg (dp)
|
z - dp reg (dp)
|
|
|
Memory/constant constraints for the C4x
|
Memory/constant constraints for the C4x
|
|
|
G - short float 16-bit
|
G - short float 16-bit
|
I - signed 16-bit constant (sign extended)
|
I - signed 16-bit constant (sign extended)
|
J - signed 8-bit constant (sign extended) (C4x only)
|
J - signed 8-bit constant (sign extended) (C4x only)
|
K - signed 5-bit constant (sign extended) (C4x only for stik)
|
K - signed 5-bit constant (sign extended) (C4x only for stik)
|
L - unsigned 16-bit constant
|
L - unsigned 16-bit constant
|
M - unsigned 8-bit constant (C4x only)
|
M - unsigned 8-bit constant (C4x only)
|
N - ones complement of unsigned 16-bit constant
|
N - ones complement of unsigned 16-bit constant
|
Q - indirect arx + 9-bit signed displacement
|
Q - indirect arx + 9-bit signed displacement
|
(a *-arx(n) or *+arx(n) is used to account for the sign bit)
|
(a *-arx(n) or *+arx(n) is used to account for the sign bit)
|
R - indirect arx + 5-bit unsigned displacement (C4x only)
|
R - indirect arx + 5-bit unsigned displacement (C4x only)
|
S - indirect arx + 0, 1, or irn displacement
|
S - indirect arx + 0, 1, or irn displacement
|
T - direct symbol ref
|
T - direct symbol ref
|
> - indirect with autoincrement
|
> - indirect with autoincrement
|
< - indirect with autodecrement
|
< - indirect with autodecrement
|
} - indirect with post-modify
|
} - indirect with post-modify
|
{ - indirect with pre-modify
|
{ - indirect with pre-modify
|
*/
|
*/
|
|
|
#define REG_CLASS_FROM_LETTER(CC) \
|
#define REG_CLASS_FROM_LETTER(CC) \
|
( ((CC) == 'a') ? ADDR_REGS \
|
( ((CC) == 'a') ? ADDR_REGS \
|
: ((CC) == 'b') ? SP_REG \
|
: ((CC) == 'b') ? SP_REG \
|
: ((CC) == 'c') ? INT_REGS \
|
: ((CC) == 'c') ? INT_REGS \
|
: ((CC) == 'd') ? EXT_REGS \
|
: ((CC) == 'd') ? EXT_REGS \
|
: ((CC) == 'f') ? EXT_REGS \
|
: ((CC) == 'f') ? EXT_REGS \
|
: ((CC) == 'h') ? EXT_REGS \
|
: ((CC) == 'h') ? EXT_REGS \
|
: ((CC) == 'k') ? BK_REG \
|
: ((CC) == 'k') ? BK_REG \
|
: ((CC) == 'q') ? EXT_LOW_REGS \
|
: ((CC) == 'q') ? EXT_LOW_REGS \
|
: ((CC) == 't') ? R0R1_REGS \
|
: ((CC) == 't') ? R0R1_REGS \
|
: ((CC) == 'u') ? R2R3_REGS \
|
: ((CC) == 'u') ? R2R3_REGS \
|
: ((CC) == 'v') ? RC_REG \
|
: ((CC) == 'v') ? RC_REG \
|
: ((CC) == 'x') ? INDEX_REGS \
|
: ((CC) == 'x') ? INDEX_REGS \
|
: ((CC) == 'y') ? ST_REG \
|
: ((CC) == 'y') ? ST_REG \
|
: ((CC) == 'z') ? DP_REG \
|
: ((CC) == 'z') ? DP_REG \
|
: NO_REGS )
|
: NO_REGS )
|
|
|
/* These assume that REGNO is a hard or pseudo reg number.
|
/* These assume that REGNO is a hard or pseudo reg number.
|
They give nonzero only if REGNO is a hard reg of the suitable class
|
They give nonzero only if REGNO is a hard reg of the suitable class
|
or a pseudo reg currently allocated to a suitable hard reg.
|
or a pseudo reg currently allocated to a suitable hard reg.
|
Since they use reg_renumber, they are safe only once reg_renumber
|
Since they use reg_renumber, they are safe only once reg_renumber
|
has been allocated, which happens in local-alloc.c. */
|
has been allocated, which happens in local-alloc.c. */
|
|
|
#define REGNO_OK_FOR_BASE_P(REGNO) \
|
#define REGNO_OK_FOR_BASE_P(REGNO) \
|
(IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
|
(IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
|
|
|
#define REGNO_OK_FOR_INDEX_P(REGNO) \
|
#define REGNO_OK_FOR_INDEX_P(REGNO) \
|
(IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
|
(IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
|
|
|
/* If we have to generate framepointer + constant prefer an ADDR_REGS
|
/* If we have to generate framepointer + constant prefer an ADDR_REGS
|
register. This avoids using EXT_REGS in addqi3_noclobber_reload. */
|
register. This avoids using EXT_REGS in addqi3_noclobber_reload. */
|
|
|
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
|
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
|
(GET_CODE (X) == PLUS \
|
(GET_CODE (X) == PLUS \
|
&& GET_MODE (X) == Pmode \
|
&& GET_MODE (X) == Pmode \
|
&& GET_CODE (XEXP ((X), 0)) == REG \
|
&& GET_CODE (XEXP ((X), 0)) == REG \
|
&& GET_MODE (XEXP ((X), 0)) == Pmode \
|
&& GET_MODE (XEXP ((X), 0)) == Pmode \
|
&& REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
|
&& REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
|
&& GET_CODE (XEXP ((X), 1)) == CONST_INT \
|
&& GET_CODE (XEXP ((X), 1)) == CONST_INT \
|
? ADDR_REGS : (CLASS))
|
? ADDR_REGS : (CLASS))
|
|
|
#define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
|
#define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
|
|
|
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
|
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
|
|
|
#define CLASS_MAX_NREGS(CLASS, MODE) \
|
#define CLASS_MAX_NREGS(CLASS, MODE) \
|
(((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
|
(((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
|
((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
|
((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
|
|
|
#define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */
|
#define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */
|
|
|
#define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */
|
#define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */
|
|
|
#define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */
|
#define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */
|
|
|
#define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */
|
#define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */
|
|
|
#define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */
|
#define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */
|
|
|
#define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */
|
#define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */
|
|
|
#define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */
|
#define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */
|
|
|
#define IS_HIGH_CONST(VAL) \
|
#define IS_HIGH_CONST(VAL) \
|
(! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */
|
(! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */
|
|
|
|
|
#define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */
|
#define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */
|
|
|
#define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */
|
#define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */
|
|
|
#define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
|
#define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
|
&& IS_DISP1_CONST (VAL + 1))
|
&& IS_DISP1_CONST (VAL + 1))
|
|
|
#define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
|
#define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
|
&& IS_DISP8_CONST (VAL + 1))
|
&& IS_DISP8_CONST (VAL + 1))
|
|
|
#define CONST_OK_FOR_LETTER_P(VAL, C) \
|
#define CONST_OK_FOR_LETTER_P(VAL, C) \
|
( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
|
( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
|
: ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
|
: ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
|
: ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
|
: ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
|
: ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
|
: ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
|
: ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
|
: ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
|
: ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
|
: ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
|
: ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
|
: ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
|
: 0 )
|
: 0 )
|
|
|
#define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
|
#define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
|
( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
|
( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
|
: ((C) == 'H') ? (c4x_H_constant (OP)) \
|
: ((C) == 'H') ? (c4x_H_constant (OP)) \
|
: 0 )
|
: 0 )
|
|
|
#define EXTRA_CONSTRAINT(OP, C) \
|
#define EXTRA_CONSTRAINT(OP, C) \
|
( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
|
( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
|
: ((C) == 'R') ? (c4x_R_constraint (OP)) \
|
: ((C) == 'R') ? (c4x_R_constraint (OP)) \
|
: ((C) == 'S') ? (c4x_S_constraint (OP)) \
|
: ((C) == 'S') ? (c4x_S_constraint (OP)) \
|
: ((C) == 'T') ? (c4x_T_constraint (OP)) \
|
: ((C) == 'T') ? (c4x_T_constraint (OP)) \
|
: ((C) == 'U') ? (c4x_U_constraint (OP)) \
|
: ((C) == 'U') ? (c4x_U_constraint (OP)) \
|
: 0 )
|
: 0 )
|
|
|
#define SMALL_CONST(VAL, insn) \
|
#define SMALL_CONST(VAL, insn) \
|
( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
|
( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
|
? IS_INT16_CONST (VAL) \
|
? IS_INT16_CONST (VAL) \
|
: ( (get_attr_data (insn) == DATA_NOT_UINT16) \
|
: ( (get_attr_data (insn) == DATA_NOT_UINT16) \
|
? IS_NOT_UINT16_CONST (VAL) \
|
? IS_NOT_UINT16_CONST (VAL) \
|
: ( (get_attr_data (insn) == DATA_HIGH_16) \
|
: ( (get_attr_data (insn) == DATA_HIGH_16) \
|
? IS_HIGH_CONST (VAL) \
|
? IS_HIGH_CONST (VAL) \
|
: IS_UINT16_CONST (VAL) \
|
: IS_UINT16_CONST (VAL) \
|
) \
|
) \
|
) \
|
) \
|
)
|
)
|
|
|
/*
|
/*
|
I. Routine calling with arguments in registers
|
I. Routine calling with arguments in registers
|
----------------------------------------------
|
----------------------------------------------
|
|
|
The TI C3x compiler has a rather unusual register passing algorithm.
|
The TI C3x compiler has a rather unusual register passing algorithm.
|
Data is passed in the following registers (in order):
|
Data is passed in the following registers (in order):
|
|
|
AR2, R2, R3, RC, RS, RE
|
AR2, R2, R3, RC, RS, RE
|
|
|
However, the first and second floating point values are always in R2
|
However, the first and second floating point values are always in R2
|
and R3 (and all other floats are on the stack). Structs are always
|
and R3 (and all other floats are on the stack). Structs are always
|
passed on the stack. If the last argument is an ellipsis, the
|
passed on the stack. If the last argument is an ellipsis, the
|
previous argument is passed on the stack so that its address can be
|
previous argument is passed on the stack so that its address can be
|
taken for the stdargs macros.
|
taken for the stdargs macros.
|
|
|
Because of this, we have to pre-scan the list of arguments to figure
|
Because of this, we have to pre-scan the list of arguments to figure
|
out what goes where in the list.
|
out what goes where in the list.
|
|
|
II. Routine calling with arguments on stack
|
II. Routine calling with arguments on stack
|
-------------------------------------------
|
-------------------------------------------
|
|
|
Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
|
Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
|
variables loc0, loc1, and loc2. After the function prologue has
|
variables loc0, loc1, and loc2. After the function prologue has
|
been executed, the stack frame will look like:
|
been executed, the stack frame will look like:
|
|
|
[stack grows towards increasing addresses]
|
[stack grows towards increasing addresses]
|
I-------------I
|
I-------------I
|
5 I saved reg1 I <= SP points here
|
5 I saved reg1 I <= SP points here
|
I-------------I
|
I-------------I
|
4 I saved reg0 I
|
4 I saved reg0 I
|
I-------------I
|
I-------------I
|
3 I loc2 I
|
3 I loc2 I
|
I-------------I
|
I-------------I
|
2 I loc1 I
|
2 I loc1 I
|
I-------------I
|
I-------------I
|
1 I loc0 I
|
1 I loc0 I
|
I-------------I
|
I-------------I
|
0 I old FP I <= FP (AR3) points here
|
0 I old FP I <= FP (AR3) points here
|
I-------------I
|
I-------------I
|
-1 I return PC I
|
-1 I return PC I
|
I-------------I
|
I-------------I
|
-2 I arg0 I
|
-2 I arg0 I
|
I-------------I
|
I-------------I
|
-3 I arg1 I
|
-3 I arg1 I
|
I-------------I
|
I-------------I
|
-4 I arg2 I
|
-4 I arg2 I
|
I-------------I
|
I-------------I
|
|
|
All local variables (locn) are accessible by means of +FP(n+1)
|
All local variables (locn) are accessible by means of +FP(n+1)
|
addressing, where n is the local variable number.
|
addressing, where n is the local variable number.
|
|
|
All stack arguments (argn) are accessible by means of -FP(n-2).
|
All stack arguments (argn) are accessible by means of -FP(n-2).
|
|
|
The stack pointer (SP) points to the last register saved in the
|
The stack pointer (SP) points to the last register saved in the
|
prologue (regn).
|
prologue (regn).
|
|
|
Note that a push instruction performs a preincrement of the stack
|
Note that a push instruction performs a preincrement of the stack
|
pointer. (STACK_PUSH_CODE == PRE_INC)
|
pointer. (STACK_PUSH_CODE == PRE_INC)
|
|
|
III. Registers used in function calling convention
|
III. Registers used in function calling convention
|
--------------------------------------------------
|
--------------------------------------------------
|
|
|
Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
|
Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
|
R6...R7 (only by PUSHF, i.e. upper 32 bits)
|
R6...R7 (only by PUSHF, i.e. upper 32 bits)
|
AR3...AR7
|
AR3...AR7
|
|
|
(Because of this model, we only assign FP values in R6, R7 and
|
(Because of this model, we only assign FP values in R6, R7 and
|
only assign integer values in R4, R5.)
|
only assign integer values in R4, R5.)
|
|
|
These registers are saved at each function entry and restored at
|
These registers are saved at each function entry and restored at
|
the exit. Also it is expected any of these not affected by any
|
the exit. Also it is expected any of these not affected by any
|
call to user-defined (not service) functions.
|
call to user-defined (not service) functions.
|
|
|
Not preserved across calls: R0...R3
|
Not preserved across calls: R0...R3
|
R4...R5 (upper 8 bits)
|
R4...R5 (upper 8 bits)
|
R6...R7 (lower 8 bits)
|
R6...R7 (lower 8 bits)
|
AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
|
AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
|
|
|
These registers are used arbitrary in a function without being preserved.
|
These registers are used arbitrary in a function without being preserved.
|
It is also expected that any of these can be clobbered by any call.
|
It is also expected that any of these can be clobbered by any call.
|
|
|
Not used by GCC (except for in user "asm" statements):
|
Not used by GCC (except for in user "asm" statements):
|
IE (DIE), IF (IIE), IOF (IIF)
|
IE (DIE), IF (IIE), IOF (IIF)
|
|
|
These registers are never used by GCC for any data, but can be used
|
These registers are never used by GCC for any data, but can be used
|
with "asm" statements. */
|
with "asm" statements. */
|
|
|
#define C4X_ARG0 -2
|
#define C4X_ARG0 -2
|
#define C4X_LOC0 1
|
#define C4X_LOC0 1
|
|
|
/* Basic Stack Layout. */
|
/* Basic Stack Layout. */
|
|
|
/* The stack grows upward, stack frame grows upward, and args grow
|
/* The stack grows upward, stack frame grows upward, and args grow
|
downward. */
|
downward. */
|
|
|
#define STARTING_FRAME_OFFSET C4X_LOC0
|
#define STARTING_FRAME_OFFSET C4X_LOC0
|
#define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
|
#define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
|
#define ARGS_GROW_DOWNWARD
|
#define ARGS_GROW_DOWNWARD
|
#define STACK_POINTER_OFFSET 1
|
#define STACK_POINTER_OFFSET 1
|
|
|
/* Define this if pushing a word on the stack
|
/* Define this if pushing a word on the stack
|
makes the stack pointer a smaller address. */
|
makes the stack pointer a smaller address. */
|
|
|
/* #define STACK_GROWS_DOWNWARD. */
|
/* #define STACK_GROWS_DOWNWARD. */
|
/* Like the dsp16xx, i370, i960, and we32k ports. */
|
/* Like the dsp16xx, i370, i960, and we32k ports. */
|
|
|
/* Define this to nonzero if the nominal address of the stack frame
|
/* Define this to nonzero if the nominal address of the stack frame
|
is at the high-address end of the local variables;
|
is at the high-address end of the local variables;
|
that is, each additional local variable allocated
|
that is, each additional local variable allocated
|
goes at a more negative offset in the frame. */
|
goes at a more negative offset in the frame. */
|
|
|
#define FRAME_GROWS_DOWNWARD 0
|
#define FRAME_GROWS_DOWNWARD 0
|
|
|
|
|
/* Registers That Address the Stack Frame. */
|
/* Registers That Address the Stack Frame. */
|
|
|
#define STACK_POINTER_REGNUM SP_REGNO /* SP. */
|
#define STACK_POINTER_REGNUM SP_REGNO /* SP. */
|
#define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */
|
#define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */
|
#define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */
|
#define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */
|
#define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */
|
#define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */
|
|
|
/* Eliminating Frame Pointer and Arg Pointer. */
|
/* Eliminating Frame Pointer and Arg Pointer. */
|
|
|
#define FRAME_POINTER_REQUIRED 0
|
#define FRAME_POINTER_REQUIRED 0
|
|
|
#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
|
#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
|
{ \
|
{ \
|
int regno; \
|
int regno; \
|
int offset = 0; \
|
int offset = 0; \
|
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
|
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
|
if (regs_ever_live[regno] && ! call_used_regs[regno]) \
|
if (regs_ever_live[regno] && ! call_used_regs[regno]) \
|
offset += TARGET_PRESERVE_FLOAT \
|
offset += TARGET_PRESERVE_FLOAT \
|
&& IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
|
&& IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
|
(DEPTH) = -(offset + get_frame_size ()); \
|
(DEPTH) = -(offset + get_frame_size ()); \
|
}
|
}
|
|
|
/* This is a hack... We need to specify a register. */
|
/* This is a hack... We need to specify a register. */
|
#define ELIMINABLE_REGS \
|
#define ELIMINABLE_REGS \
|
{{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
|
{{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
|
|
|
#define CAN_ELIMINATE(FROM, TO) \
|
#define CAN_ELIMINATE(FROM, TO) \
|
(! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
|
(! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
|
|| ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
|
|| ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
|
|
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
{ \
|
{ \
|
int regno; \
|
int regno; \
|
int offset = 0; \
|
int offset = 0; \
|
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
|
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
|
if (regs_ever_live[regno] && ! call_used_regs[regno]) \
|
if (regs_ever_live[regno] && ! call_used_regs[regno]) \
|
offset += TARGET_PRESERVE_FLOAT \
|
offset += TARGET_PRESERVE_FLOAT \
|
&& IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
|
&& IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
|
(OFFSET) = -(offset + get_frame_size ()); \
|
(OFFSET) = -(offset + get_frame_size ()); \
|
}
|
}
|
|
|
|
|
/* Passing Function Arguments on the Stack. */
|
/* Passing Function Arguments on the Stack. */
|
|
|
#define PUSH_ARGS 1
|
#define PUSH_ARGS 1
|
#define PUSH_ROUNDING(BYTES) (BYTES)
|
#define PUSH_ROUNDING(BYTES) (BYTES)
|
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
|
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
|
|
|
/* The following structure is used by calls.c, function.c, c4x.c. */
|
/* The following structure is used by calls.c, function.c, c4x.c. */
|
|
|
typedef struct c4x_args
|
typedef struct c4x_args
|
{
|
{
|
int floats;
|
int floats;
|
int ints;
|
int ints;
|
int maxfloats;
|
int maxfloats;
|
int maxints;
|
int maxints;
|
int init;
|
int init;
|
int var;
|
int var;
|
int prototype;
|
int prototype;
|
int args;
|
int args;
|
}
|
}
|
CUMULATIVE_ARGS;
|
CUMULATIVE_ARGS;
|
|
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
(c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
|
(c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
|
|
|
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
(c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
|
(c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
|
|
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
(c4x_function_arg(&CUM, MODE, TYPE, NAMED))
|
(c4x_function_arg(&CUM, MODE, TYPE, NAMED))
|
|
|
/* Define the profitability of saving registers around calls.
|
/* Define the profitability of saving registers around calls.
|
We disable caller save to avoid a bug in flow.c (this also affects
|
We disable caller save to avoid a bug in flow.c (this also affects
|
other targets such as m68k). Since we must use stf/sti,
|
other targets such as m68k). Since we must use stf/sti,
|
the profitability is marginal anyway. */
|
the profitability is marginal anyway. */
|
|
|
#define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
|
#define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
|
|
|
/* 1 if N is a possible register number for function argument passing. */
|
/* 1 if N is a possible register number for function argument passing. */
|
|
|
#define FUNCTION_ARG_REGNO_P(REGNO) \
|
#define FUNCTION_ARG_REGNO_P(REGNO) \
|
( ( ((REGNO) == AR2_REGNO) /* AR2. */ \
|
( ( ((REGNO) == AR2_REGNO) /* AR2. */ \
|
|| ((REGNO) == R2_REGNO) /* R2. */ \
|
|| ((REGNO) == R2_REGNO) /* R2. */ \
|
|| ((REGNO) == R3_REGNO) /* R3. */ \
|
|| ((REGNO) == R3_REGNO) /* R3. */ \
|
|| ((REGNO) == RC_REGNO) /* RC. */ \
|
|| ((REGNO) == RC_REGNO) /* RC. */ \
|
|| ((REGNO) == RS_REGNO) /* RS. */ \
|
|| ((REGNO) == RS_REGNO) /* RS. */ \
|
|| ((REGNO) == RE_REGNO)) /* RE. */ \
|
|| ((REGNO) == RE_REGNO)) /* RE. */ \
|
? 1 \
|
? 1 \
|
: 0)
|
: 0)
|
|
|
/* How Scalar Function Values Are Returned. */
|
/* How Scalar Function Values Are Returned. */
|
|
|
#define FUNCTION_VALUE(VALTYPE, FUNC) \
|
#define FUNCTION_VALUE(VALTYPE, FUNC) \
|
gen_rtx_REG (TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
|
gen_rtx_REG (TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
|
|
|
#define LIBCALL_VALUE(MODE) \
|
#define LIBCALL_VALUE(MODE) \
|
gen_rtx_REG (MODE, R0_REGNO) /* Return in R0. */
|
gen_rtx_REG (MODE, R0_REGNO) /* Return in R0. */
|
|
|
#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
|
#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
|
|
|
/* How Large Values Are Returned. */
|
/* How Large Values Are Returned. */
|
|
|
#define DEFAULT_PCC_STRUCT_RETURN 0
|
#define DEFAULT_PCC_STRUCT_RETURN 0
|
|
|
/* Generating Code for Profiling. */
|
/* Generating Code for Profiling. */
|
|
|
/* Note that the generated assembly uses the ^ operator to load the 16
|
/* Note that the generated assembly uses the ^ operator to load the 16
|
MSBs of the address. This is not supported by the TI assembler.
|
MSBs of the address. This is not supported by the TI assembler.
|
The FUNCTION profiler needs a function mcount which gets passed
|
The FUNCTION profiler needs a function mcount which gets passed
|
a pointer to the LABELNO. */
|
a pointer to the LABELNO. */
|
|
|
#define FUNCTION_PROFILER(FILE, LABELNO) \
|
#define FUNCTION_PROFILER(FILE, LABELNO) \
|
if (! TARGET_C3X) \
|
if (! TARGET_C3X) \
|
{ \
|
{ \
|
fprintf (FILE, "\tpush\tar2\n"); \
|
fprintf (FILE, "\tpush\tar2\n"); \
|
fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
|
fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
|
fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
|
fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
|
fprintf (FILE, "\tcall\tmcount\n"); \
|
fprintf (FILE, "\tcall\tmcount\n"); \
|
fprintf (FILE, "\tpop\tar2\n"); \
|
fprintf (FILE, "\tpop\tar2\n"); \
|
} \
|
} \
|
else \
|
else \
|
{ \
|
{ \
|
fprintf (FILE, "\tpush\tar2\n"); \
|
fprintf (FILE, "\tpush\tar2\n"); \
|
fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
|
fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
|
fprintf (FILE, "\tlsh\t16,ar2\n"); \
|
fprintf (FILE, "\tlsh\t16,ar2\n"); \
|
fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
|
fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
|
fprintf (FILE, "\tcall\tmcount\n"); \
|
fprintf (FILE, "\tcall\tmcount\n"); \
|
fprintf (FILE, "\tpop\tar2\n"); \
|
fprintf (FILE, "\tpop\tar2\n"); \
|
}
|
}
|
|
|
/* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
|
/* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
|
or MULT.
|
or MULT.
|
CCmode should be used when no special processing is needed. */
|
CCmode should be used when no special processing is needed. */
|
#define SELECT_CC_MODE(OP,X,Y) \
|
#define SELECT_CC_MODE(OP,X,Y) \
|
((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
|
((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
|
|| GET_CODE (X) == NEG || GET_CODE (X) == MULT \
|
|| GET_CODE (X) == NEG || GET_CODE (X) == MULT \
|
|| GET_MODE (X) == ABS \
|
|| GET_MODE (X) == ABS \
|
|| GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
|
|| GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
|
|| GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
|
|| GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
|
|| GET_MODE (Y) == ABS) \
|
|| GET_MODE (Y) == ABS) \
|
? CC_NOOVmode : CCmode)
|
? CC_NOOVmode : CCmode)
|
|
|
/* Addressing Modes. */
|
/* Addressing Modes. */
|
|
|
#define HAVE_POST_INCREMENT 1
|
#define HAVE_POST_INCREMENT 1
|
#define HAVE_PRE_INCREMENT 1
|
#define HAVE_PRE_INCREMENT 1
|
#define HAVE_POST_DECREMENT 1
|
#define HAVE_POST_DECREMENT 1
|
#define HAVE_PRE_DECREMENT 1
|
#define HAVE_PRE_DECREMENT 1
|
#define HAVE_PRE_MODIFY_REG 1
|
#define HAVE_PRE_MODIFY_REG 1
|
#define HAVE_POST_MODIFY_REG 1
|
#define HAVE_POST_MODIFY_REG 1
|
#define HAVE_PRE_MODIFY_DISP 1
|
#define HAVE_PRE_MODIFY_DISP 1
|
#define HAVE_POST_MODIFY_DISP 1
|
#define HAVE_POST_MODIFY_DISP 1
|
|
|
/* The number of insns that can be packed into a single opcode. */
|
/* The number of insns that can be packed into a single opcode. */
|
#define PACK_INSNS 2
|
#define PACK_INSNS 2
|
|
|
/* Recognize any constant value that is a valid address.
|
/* Recognize any constant value that is a valid address.
|
We could allow arbitrary constant addresses in the large memory
|
We could allow arbitrary constant addresses in the large memory
|
model but for the small memory model we can only accept addresses
|
model but for the small memory model we can only accept addresses
|
within the data page. I suppose we could also allow
|
within the data page. I suppose we could also allow
|
CONST PLUS SYMBOL_REF. */
|
CONST PLUS SYMBOL_REF. */
|
#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
|
#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
|
|
|
/* Maximum number of registers that can appear in a valid memory
|
/* Maximum number of registers that can appear in a valid memory
|
address. */
|
address. */
|
#define MAX_REGS_PER_ADDRESS 2
|
#define MAX_REGS_PER_ADDRESS 2
|
|
|
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
and check its validity for a certain class.
|
and check its validity for a certain class.
|
We have two alternate definitions for each of them.
|
We have two alternate definitions for each of them.
|
The usual definition accepts all pseudo regs; the other rejects
|
The usual definition accepts all pseudo regs; the other rejects
|
them unless they have been allocated suitable hard regs.
|
them unless they have been allocated suitable hard regs.
|
The symbol REG_OK_STRICT causes the latter definition to be used.
|
The symbol REG_OK_STRICT causes the latter definition to be used.
|
|
|
Most source files want to accept pseudo regs in the hope that
|
Most source files want to accept pseudo regs in the hope that
|
they will get allocated to the class that the insn wants them to be in.
|
they will get allocated to the class that the insn wants them to be in.
|
Source files for reload pass need to be strict.
|
Source files for reload pass need to be strict.
|
After reload, it makes no difference, since pseudo regs have
|
After reload, it makes no difference, since pseudo regs have
|
been eliminated by then. */
|
been eliminated by then. */
|
|
|
#ifndef REG_OK_STRICT
|
#ifndef REG_OK_STRICT
|
|
|
/* Nonzero if X is a hard or pseudo reg that can be used as a base. */
|
/* Nonzero if X is a hard or pseudo reg that can be used as a base. */
|
|
|
#define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
|
#define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
|
|
|
/* Nonzero if X is a hard or pseudo reg that can be used as an index. */
|
/* Nonzero if X is a hard or pseudo reg that can be used as an index. */
|
|
|
#define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
|
#define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
|
|
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
{ \
|
{ \
|
if (c4x_legitimate_address_p (MODE, X, 0)) \
|
if (c4x_legitimate_address_p (MODE, X, 0)) \
|
goto ADDR; \
|
goto ADDR; \
|
}
|
}
|
|
|
#else
|
#else
|
|
|
/* Nonzero if X is a hard reg that can be used as an index. */
|
/* Nonzero if X is a hard reg that can be used as an index. */
|
|
|
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
|
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
|
|
|
/* Nonzero if X is a hard reg that can be used as a base reg. */
|
/* Nonzero if X is a hard reg that can be used as a base reg. */
|
|
|
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
|
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
|
|
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
{ \
|
{ \
|
if (c4x_legitimate_address_p (MODE, X, 1)) \
|
if (c4x_legitimate_address_p (MODE, X, 1)) \
|
goto ADDR; \
|
goto ADDR; \
|
}
|
}
|
|
|
#endif
|
#endif
|
|
|
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
|
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
|
{ \
|
{ \
|
rtx new; \
|
rtx new; \
|
\
|
\
|
new = c4x_legitimize_address (X, MODE); \
|
new = c4x_legitimize_address (X, MODE); \
|
if (new != NULL_RTX) \
|
if (new != NULL_RTX) \
|
{ \
|
{ \
|
(X) = new; \
|
(X) = new; \
|
goto WIN; \
|
goto WIN; \
|
} \
|
} \
|
}
|
}
|
|
|
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
|
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
|
{ \
|
{ \
|
if (MODE != HImode \
|
if (MODE != HImode \
|
&& MODE != HFmode \
|
&& MODE != HFmode \
|
&& GET_MODE (X) != HImode \
|
&& GET_MODE (X) != HImode \
|
&& GET_MODE (X) != HFmode \
|
&& GET_MODE (X) != HFmode \
|
&& (GET_CODE (X) == CONST \
|
&& (GET_CODE (X) == CONST \
|
|| GET_CODE (X) == SYMBOL_REF \
|
|| GET_CODE (X) == SYMBOL_REF \
|
|| GET_CODE (X) == LABEL_REF)) \
|
|| GET_CODE (X) == LABEL_REF)) \
|
{ \
|
{ \
|
if (! TARGET_SMALL) \
|
if (! TARGET_SMALL) \
|
{ \
|
{ \
|
int i; \
|
int i; \
|
(X) = gen_rtx_LO_SUM (GET_MODE (X), \
|
(X) = gen_rtx_LO_SUM (GET_MODE (X), \
|
gen_rtx_HIGH (GET_MODE (X), X), X); \
|
gen_rtx_HIGH (GET_MODE (X), X), X); \
|
i = push_reload (XEXP (X, 0), NULL_RTX, \
|
i = push_reload (XEXP (X, 0), NULL_RTX, \
|
&XEXP (X, 0), NULL, \
|
&XEXP (X, 0), NULL, \
|
DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
|
DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
|
OPNUM, TYPE); \
|
OPNUM, TYPE); \
|
/* The only valid reg is DP. This is a fixed reg and will \
|
/* The only valid reg is DP. This is a fixed reg and will \
|
normally not be used so force it. */ \
|
normally not be used so force it. */ \
|
rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
|
rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
|
rld[i].nocombine = 1; \
|
rld[i].nocombine = 1; \
|
} \
|
} \
|
else \
|
else \
|
{ \
|
{ \
|
/* make_memloc in reload will substitute invalid memory \
|
/* make_memloc in reload will substitute invalid memory \
|
references. We need to fix them up. */ \
|
references. We need to fix them up. */ \
|
(X) = gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, DP_REGNO), (X)); \
|
(X) = gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, DP_REGNO), (X)); \
|
} \
|
} \
|
goto WIN; \
|
goto WIN; \
|
} \
|
} \
|
else if (MODE != HImode \
|
else if (MODE != HImode \
|
&& MODE != HFmode \
|
&& MODE != HFmode \
|
&& GET_MODE (X) != HImode \
|
&& GET_MODE (X) != HImode \
|
&& GET_MODE (X) != HFmode \
|
&& GET_MODE (X) != HFmode \
|
&& GET_CODE (X) == LO_SUM \
|
&& GET_CODE (X) == LO_SUM \
|
&& GET_CODE (XEXP (X,0)) == HIGH \
|
&& GET_CODE (XEXP (X,0)) == HIGH \
|
&& (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \
|
&& (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \
|
|| GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \
|
|| GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \
|
|| GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \
|
|| GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \
|
{ \
|
{ \
|
if (! TARGET_SMALL) \
|
if (! TARGET_SMALL) \
|
{ \
|
{ \
|
int i = push_reload (XEXP (X, 0), NULL_RTX, \
|
int i = push_reload (XEXP (X, 0), NULL_RTX, \
|
&XEXP (X, 0), NULL, \
|
&XEXP (X, 0), NULL, \
|
DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
|
DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
|
OPNUM, TYPE); \
|
OPNUM, TYPE); \
|
/* The only valid reg is DP. This is a fixed reg and will \
|
/* The only valid reg is DP. This is a fixed reg and will \
|
normally not be used so force it. */ \
|
normally not be used so force it. */ \
|
rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
|
rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
|
rld[i].nocombine = 1; \
|
rld[i].nocombine = 1; \
|
} \
|
} \
|
goto WIN; \
|
goto WIN; \
|
} \
|
} \
|
}
|
}
|
|
|
/* No mode-dependent addresses on the C4x are autoincrements. */
|
/* No mode-dependent addresses on the C4x are autoincrements. */
|
|
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
|
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
|
if (GET_CODE (ADDR) == PRE_DEC \
|
if (GET_CODE (ADDR) == PRE_DEC \
|
|| GET_CODE (ADDR) == POST_DEC \
|
|| GET_CODE (ADDR) == POST_DEC \
|
|| GET_CODE (ADDR) == PRE_INC \
|
|| GET_CODE (ADDR) == PRE_INC \
|
|| GET_CODE (ADDR) == POST_INC \
|
|| GET_CODE (ADDR) == POST_INC \
|
|| GET_CODE (ADDR) == POST_MODIFY \
|
|| GET_CODE (ADDR) == POST_MODIFY \
|
|| GET_CODE (ADDR) == PRE_MODIFY) \
|
|| GET_CODE (ADDR) == PRE_MODIFY) \
|
goto LABEL
|
goto LABEL
|
|
|
|
|
/* Nonzero if the constant value X is a legitimate general operand.
|
/* Nonzero if the constant value X is a legitimate general operand.
|
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
|
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
|
|
|
The C4x can only load 16-bit immediate values, so we only allow a
|
The C4x can only load 16-bit immediate values, so we only allow a
|
restricted subset of CONST_INT and CONST_DOUBLE. Disallow
|
restricted subset of CONST_INT and CONST_DOUBLE. Disallow
|
LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
|
LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
|
model) so that the symbols will be forced into the constant pool.
|
model) so that the symbols will be forced into the constant pool.
|
On second thoughts, let's do this with the move expanders since
|
On second thoughts, let's do this with the move expanders since
|
the alias analysis has trouble if we force constant addresses
|
the alias analysis has trouble if we force constant addresses
|
into memory.
|
into memory.
|
*/
|
*/
|
|
|
#define LEGITIMATE_CONSTANT_P(X) \
|
#define LEGITIMATE_CONSTANT_P(X) \
|
((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
|
((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
|
|| (GET_CODE (X) == CONST_INT) \
|
|| (GET_CODE (X) == CONST_INT) \
|
|| (GET_CODE (X) == SYMBOL_REF) \
|
|| (GET_CODE (X) == SYMBOL_REF) \
|
|| (GET_CODE (X) == LABEL_REF) \
|
|| (GET_CODE (X) == LABEL_REF) \
|
|| (GET_CODE (X) == CONST) \
|
|| (GET_CODE (X) == CONST) \
|
|| (GET_CODE (X) == HIGH && ! TARGET_C3X) \
|
|| (GET_CODE (X) == HIGH && ! TARGET_C3X) \
|
|| (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
|
|| (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
|
|
|
#define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
|
#define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
|
|
|
/* Describing Relative Cost of Operations. */
|
/* Describing Relative Cost of Operations. */
|
|
|
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
|
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
|
if (REG_P (OP1) && ! REG_P (OP0)) \
|
if (REG_P (OP1) && ! REG_P (OP0)) \
|
{ \
|
{ \
|
rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
|
rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
|
CODE = swap_condition (CODE); \
|
CODE = swap_condition (CODE); \
|
}
|
}
|
|
|
#define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
|
#define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
|
#define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
|
#define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
|
#define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
|
#define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
|
#define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
|
#define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
|
|| INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
|
|| INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
|
|
|
/* Compute extra cost of moving data between one register class
|
/* Compute extra cost of moving data between one register class
|
and another. */
|
and another. */
|
|
|
#define REGISTER_MOVE_COST(MODE, FROM, TO) 2
|
#define REGISTER_MOVE_COST(MODE, FROM, TO) 2
|
|
|
/* Memory move cost is same as fast register move. Maybe this should
|
/* Memory move cost is same as fast register move. Maybe this should
|
be bumped up?. */
|
be bumped up?. */
|
|
|
#define MEMORY_MOVE_COST(M,C,I) 4
|
#define MEMORY_MOVE_COST(M,C,I) 4
|
|
|
/* Branches are kind of expensive (even with delayed branching) so
|
/* Branches are kind of expensive (even with delayed branching) so
|
make their cost higher. */
|
make their cost higher. */
|
|
|
#define BRANCH_COST 8
|
#define BRANCH_COST 8
|
|
|
#define WORD_REGISTER_OPERATIONS
|
#define WORD_REGISTER_OPERATIONS
|
|
|
/* Dividing the Output into Sections. */
|
/* Dividing the Output into Sections. */
|
|
|
#define TEXT_SECTION_ASM_OP "\t.text"
|
#define TEXT_SECTION_ASM_OP "\t.text"
|
|
|
#define DATA_SECTION_ASM_OP "\t.data"
|
#define DATA_SECTION_ASM_OP "\t.data"
|
|
|
#define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\""
|
#define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\""
|
|
|
/* Do not use .init section so __main will be called on startup. This will
|
/* Do not use .init section so __main will be called on startup. This will
|
call __do_global_ctors and prepare for __do_global_dtors on exit. */
|
call __do_global_ctors and prepare for __do_global_dtors on exit. */
|
|
|
#if 0
|
#if 0
|
#define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
|
#define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
|
#endif
|
#endif
|
|
|
#define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
|
#define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
|
|
|
/* Switch into a generic section. */
|
/* Switch into a generic section. */
|
#define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
|
#define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
|
|
|
|
|
/* Overall Framework of an Assembler File. */
|
/* Overall Framework of an Assembler File. */
|
|
|
#define ASM_COMMENT_START ";"
|
#define ASM_COMMENT_START ";"
|
|
|
#define ASM_APP_ON ""
|
#define ASM_APP_ON ""
|
#define ASM_APP_OFF ""
|
#define ASM_APP_OFF ""
|
|
|
#define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
|
#define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
|
|
|
/* Output and Generation of Labels. */
|
/* Output and Generation of Labels. */
|
|
|
#define NO_DOT_IN_LABEL /* Only required for TI format. */
|
#define NO_DOT_IN_LABEL /* Only required for TI format. */
|
|
|
/* Globalizing directive for a label. */
|
/* Globalizing directive for a label. */
|
#define GLOBAL_ASM_OP "\t.global\t"
|
#define GLOBAL_ASM_OP "\t.global\t"
|
|
|
#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
|
#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
|
c4x_external_ref (NAME)
|
c4x_external_ref (NAME)
|
|
|
/* The prefix to add to user-visible assembler symbols. */
|
/* The prefix to add to user-visible assembler symbols. */
|
|
|
#define USER_LABEL_PREFIX "_"
|
#define USER_LABEL_PREFIX "_"
|
|
|
/* This is how to store into the string LABEL
|
/* This is how to store into the string LABEL
|
the symbol_ref name of an internal numbered label where
|
the symbol_ref name of an internal numbered label where
|
PREFIX is the class of label and NUM is the number within the class.
|
PREFIX is the class of label and NUM is the number within the class.
|
This is suitable for output with `assemble_name'. */
|
This is suitable for output with `assemble_name'. */
|
|
|
#define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
|
#define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
|
sprintf (BUFFER, "*%s%lu", PREFIX, (unsigned long)(NUM))
|
sprintf (BUFFER, "*%s%lu", PREFIX, (unsigned long)(NUM))
|
|
|
/* A C statement to output to the stdio stream STREAM assembler code which
|
/* A C statement to output to the stdio stream STREAM assembler code which
|
defines (equates) the symbol NAME to have the value VALUE. */
|
defines (equates) the symbol NAME to have the value VALUE. */
|
|
|
#define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
|
#define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
|
do { \
|
do { \
|
assemble_name (STREAM, NAME); \
|
assemble_name (STREAM, NAME); \
|
fprintf (STREAM, "\t.set\t%s\n", VALUE); \
|
fprintf (STREAM, "\t.set\t%s\n", VALUE); \
|
} while (0)
|
} while (0)
|
|
|
/* Output of Dispatch Tables. */
|
/* Output of Dispatch Tables. */
|
|
|
/* This is how to output an element of a case-vector that is absolute. */
|
/* This is how to output an element of a case-vector that is absolute. */
|
|
|
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
fprintf (FILE, "\t.long\tL%d\n", VALUE);
|
fprintf (FILE, "\t.long\tL%d\n", VALUE);
|
|
|
/* This is how to output an element of a case-vector that is relative. */
|
/* This is how to output an element of a case-vector that is relative. */
|
|
|
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
|
fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
|
|
|
#undef SIZE_TYPE
|
#undef SIZE_TYPE
|
#define SIZE_TYPE "unsigned int"
|
#define SIZE_TYPE "unsigned int"
|
|
|
#undef PTRDIFF_TYPE
|
#undef PTRDIFF_TYPE
|
#define PTRDIFF_TYPE "int"
|
#define PTRDIFF_TYPE "int"
|
|
|
#undef WCHAR_TYPE
|
#undef WCHAR_TYPE
|
#define WCHAR_TYPE "long int"
|
#define WCHAR_TYPE "long int"
|
|
|
#undef WCHAR_TYPE_SIZE
|
#undef WCHAR_TYPE_SIZE
|
#define WCHAR_TYPE_SIZE 32
|
#define WCHAR_TYPE_SIZE 32
|
|
|
#define INT_TYPE_SIZE 32
|
#define INT_TYPE_SIZE 32
|
#define LONG_LONG_TYPE_SIZE 64
|
#define LONG_LONG_TYPE_SIZE 64
|
#define FLOAT_TYPE_SIZE 32
|
#define FLOAT_TYPE_SIZE 32
|
#define DOUBLE_TYPE_SIZE 32
|
#define DOUBLE_TYPE_SIZE 32
|
#define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
|
#define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
|
|
|
/* Output #ident as a .ident. */
|
/* Output #ident as a .ident. */
|
|
|
#define ASM_OUTPUT_IDENT(FILE, NAME) \
|
#define ASM_OUTPUT_IDENT(FILE, NAME) \
|
fprintf (FILE, "\t.ident \"%s\"\n", NAME);
|
fprintf (FILE, "\t.ident \"%s\"\n", NAME);
|
|
|
/* Output of Uninitialized Variables. */
|
/* Output of Uninitialized Variables. */
|
|
|
/* This says how to output an assembler line to define a local
|
/* This says how to output an assembler line to define a local
|
uninitialized variable. */
|
uninitialized variable. */
|
|
|
#undef ASM_OUTPUT_LOCAL
|
#undef ASM_OUTPUT_LOCAL
|
#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
|
#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
|
( fputs ("\t.bss\t", FILE), \
|
( fputs ("\t.bss\t", FILE), \
|
assemble_name (FILE, (NAME)), \
|
assemble_name (FILE, (NAME)), \
|
fprintf (FILE, ",%u\n", (int)(ROUNDED)))
|
fprintf (FILE, ",%u\n", (int)(ROUNDED)))
|
|
|
/* This says how to output an assembler line to define a global
|
/* This says how to output an assembler line to define a global
|
uninitialized variable. */
|
uninitialized variable. */
|
|
|
#undef ASM_OUTPUT_COMMON
|
#undef ASM_OUTPUT_COMMON
|
#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
|
#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
|
( fputs ("\t.globl\t", FILE), \
|
( fputs ("\t.globl\t", FILE), \
|
assemble_name (FILE, (NAME)), \
|
assemble_name (FILE, (NAME)), \
|
fputs ("\n\t.bss\t", FILE), \
|
fputs ("\n\t.bss\t", FILE), \
|
assemble_name (FILE, (NAME)), \
|
assemble_name (FILE, (NAME)), \
|
fprintf (FILE, ",%u\n", (int)(ROUNDED)))
|
fprintf (FILE, ",%u\n", (int)(ROUNDED)))
|
|
|
#undef ASM_OUTPUT_BSS
|
#undef ASM_OUTPUT_BSS
|
#define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
|
#define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
|
( fputs ("\t.globl\t", FILE), \
|
( fputs ("\t.globl\t", FILE), \
|
assemble_name (FILE, (NAME)), \
|
assemble_name (FILE, (NAME)), \
|
fputs ("\n\t.bss\t", FILE), \
|
fputs ("\n\t.bss\t", FILE), \
|
assemble_name (FILE, (NAME)), \
|
assemble_name (FILE, (NAME)), \
|
fprintf (FILE, ",%u\n", (int)(SIZE)))
|
fprintf (FILE, ",%u\n", (int)(SIZE)))
|
|
|
/* Macros Controlling Initialization Routines. */
|
/* Macros Controlling Initialization Routines. */
|
|
|
#define OBJECT_FORMAT_COFF
|
#define OBJECT_FORMAT_COFF
|
#define REAL_NM_FILE_NAME "c4x-nm"
|
#define REAL_NM_FILE_NAME "c4x-nm"
|
|
|
/* Output of Assembler Instructions. */
|
/* Output of Assembler Instructions. */
|
|
|
/* Register names when used for integer modes. */
|
/* Register names when used for integer modes. */
|
|
|
#define REGISTER_NAMES \
|
#define REGISTER_NAMES \
|
{ \
|
{ \
|
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
|
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
|
"ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
|
"ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
|
"dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
|
"dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
|
"iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
|
"iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
|
}
|
}
|
|
|
/* Alternate register names when used for floating point modes. */
|
/* Alternate register names when used for floating point modes. */
|
|
|
#define FLOAT_REGISTER_NAMES \
|
#define FLOAT_REGISTER_NAMES \
|
{ \
|
{ \
|
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
|
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
|
"ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
|
"ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
|
"dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
|
"dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
|
"iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
|
"iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
|
}
|
}
|
|
|
#define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
|
#define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
|
|
|
/* Determine which codes are valid without a following integer. These must
|
/* Determine which codes are valid without a following integer. These must
|
not be alphabetic. */
|
not be alphabetic. */
|
|
|
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
|
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
|
|
|
#define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
|
#define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
|
|
|
/* C4x specific pragmas. */
|
/* C4x specific pragmas. */
|
#define REGISTER_TARGET_PRAGMAS() do { \
|
#define REGISTER_TARGET_PRAGMAS() do { \
|
c_register_pragma (0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
|
c_register_pragma (0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
|
c_register_pragma (0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
|
c_register_pragma (0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
|
c_register_pragma (0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
|
c_register_pragma (0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
|
c_register_pragma (0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
|
c_register_pragma (0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
|
c_register_pragma (0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
|
c_register_pragma (0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
|
c_register_pragma (0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
|
c_register_pragma (0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
|
c_register_pragma (0, "FUNC_NEVER_RETURNS", c4x_pr_FUNC_NEVER_RETURNS); \
|
c_register_pragma (0, "FUNC_NEVER_RETURNS", c4x_pr_FUNC_NEVER_RETURNS); \
|
c_register_pragma (0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
|
c_register_pragma (0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
|
c_register_pragma (0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
|
c_register_pragma (0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
|
c_register_pragma (0, "INTERRUPT", c4x_pr_INTERRUPT); \
|
c_register_pragma (0, "INTERRUPT", c4x_pr_INTERRUPT); \
|
} while (0)
|
} while (0)
|
|
|
/* Assembler Commands for Alignment. */
|
/* Assembler Commands for Alignment. */
|
|
|
#define ASM_OUTPUT_SKIP(FILE, SIZE) \
|
#define ASM_OUTPUT_SKIP(FILE, SIZE) \
|
{ int c = SIZE; \
|
{ int c = SIZE; \
|
for (; c > 0; --c) \
|
for (; c > 0; --c) \
|
fprintf (FILE,"\t.word\t0\n"); \
|
fprintf (FILE,"\t.word\t0\n"); \
|
}
|
}
|
|
|
#define ASM_NO_SKIP_IN_TEXT 1
|
#define ASM_NO_SKIP_IN_TEXT 1
|
|
|
/* I'm not sure about this one. FIXME. */
|
/* I'm not sure about this one. FIXME. */
|
|
|
#define ASM_OUTPUT_ALIGN(FILE, LOG) \
|
#define ASM_OUTPUT_ALIGN(FILE, LOG) \
|
if ((LOG) != 0) \
|
if ((LOG) != 0) \
|
fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
|
fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
|
|
|
|
|
/* Macros for SDB and DWARF Output (use .sdef instead of .def
|
/* Macros for SDB and DWARF Output (use .sdef instead of .def
|
to avoid conflict with TI's use of .def). */
|
to avoid conflict with TI's use of .def). */
|
|
|
#define SDB_DELIM "\n"
|
#define SDB_DELIM "\n"
|
#define SDB_DEBUGGING_INFO 1
|
#define SDB_DEBUGGING_INFO 1
|
|
|
/* Don't use octal since this can confuse gas for the c4x. */
|
/* Don't use octal since this can confuse gas for the c4x. */
|
#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
|
#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
|
|
|
#define PUT_SDB_DEF(A) \
|
#define PUT_SDB_DEF(A) \
|
do { fprintf (asm_out_file, "\t.sdef\t"); \
|
do { fprintf (asm_out_file, "\t.sdef\t"); \
|
ASM_OUTPUT_LABELREF (asm_out_file, A); \
|
ASM_OUTPUT_LABELREF (asm_out_file, A); \
|
fprintf (asm_out_file, SDB_DELIM); } while (0)
|
fprintf (asm_out_file, SDB_DELIM); } while (0)
|
|
|
#define PUT_SDB_PLAIN_DEF(A) \
|
#define PUT_SDB_PLAIN_DEF(A) \
|
fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
|
fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
|
|
|
#define PUT_SDB_BLOCK_START(LINE) \
|
#define PUT_SDB_BLOCK_START(LINE) \
|
fprintf (asm_out_file, \
|
fprintf (asm_out_file, \
|
"\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
|
"\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
|
SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
|
SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
|
|
|
#define PUT_SDB_BLOCK_END(LINE) \
|
#define PUT_SDB_BLOCK_END(LINE) \
|
fprintf (asm_out_file, \
|
fprintf (asm_out_file, \
|
"\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
|
"\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
|
SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
|
SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
|
|
|
#define PUT_SDB_FUNCTION_START(LINE) \
|
#define PUT_SDB_FUNCTION_START(LINE) \
|
fprintf (asm_out_file, \
|
fprintf (asm_out_file, \
|
"\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
|
"\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
|
SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
|
SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
|
|
|
/* Note we output relative line numbers for .ef which gas converts
|
/* Note we output relative line numbers for .ef which gas converts
|
to absolute line numbers. The TI compiler outputs absolute line numbers
|
to absolute line numbers. The TI compiler outputs absolute line numbers
|
in the .sym directive which gas does not support. */
|
in the .sym directive which gas does not support. */
|
#define PUT_SDB_FUNCTION_END(LINE) \
|
#define PUT_SDB_FUNCTION_END(LINE) \
|
fprintf (asm_out_file, \
|
fprintf (asm_out_file, \
|
"\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
|
"\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
|
SDB_DELIM, SDB_DELIM, SDB_DELIM, \
|
SDB_DELIM, SDB_DELIM, SDB_DELIM, \
|
(LINE), SDB_DELIM)
|
(LINE), SDB_DELIM)
|
|
|
#define PUT_SDB_EPILOGUE_END(NAME) \
|
#define PUT_SDB_EPILOGUE_END(NAME) \
|
do { fprintf (asm_out_file, "\t.sdef\t"); \
|
do { fprintf (asm_out_file, "\t.sdef\t"); \
|
ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
|
ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
|
fprintf (asm_out_file, \
|
fprintf (asm_out_file, \
|
"%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
|
"%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
|
SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
|
SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
|
|
|
/* Define this as 1 if `char' should by default be signed; else as 0. */
|
/* Define this as 1 if `char' should by default be signed; else as 0. */
|
|
|
#define DEFAULT_SIGNED_CHAR 1
|
#define DEFAULT_SIGNED_CHAR 1
|
|
|
/* A function address in a call instruction is a byte address (for
|
/* A function address in a call instruction is a byte address (for
|
indexing purposes) so give the MEM rtx a byte's mode. */
|
indexing purposes) so give the MEM rtx a byte's mode. */
|
|
|
#define FUNCTION_MODE QImode
|
#define FUNCTION_MODE QImode
|
|
|
#define SLOW_BYTE_ACCESS 0
|
#define SLOW_BYTE_ACCESS 0
|
|
|
/* Specify the machine mode that pointers have. After generation of
|
/* Specify the machine mode that pointers have. After generation of
|
RTL, the compiler makes no further distinction between pointers and
|
RTL, the compiler makes no further distinction between pointers and
|
any other objects of this machine mode. */
|
any other objects of this machine mode. */
|
|
|
#define Pmode QImode
|
#define Pmode QImode
|
|
|
/* On the C4x we can write the following code. We have to clear the cache
|
/* On the C4x we can write the following code. We have to clear the cache
|
every time we execute it because the data in the stack could change.
|
every time we execute it because the data in the stack could change.
|
|
|
laj $+4
|
laj $+4
|
addi3 4,r11,ar0
|
addi3 4,r11,ar0
|
lda *ar0,ar1
|
lda *ar0,ar1
|
lda *+ar0(1),ar0
|
lda *+ar0(1),ar0
|
bud ar1
|
bud ar1
|
nop
|
nop
|
nop
|
nop
|
or 1000h,st
|
or 1000h,st
|
.word FNADDR
|
.word FNADDR
|
.word CXT
|
.word CXT
|
|
|
On the c3x this is a bit more difficult. We have to write self
|
On the c3x this is a bit more difficult. We have to write self
|
modifying code here. So we have to clear the cache every time
|
modifying code here. So we have to clear the cache every time
|
we execute it because the data in the stack could change.
|
we execute it because the data in the stack could change.
|
|
|
ldiu TOP_OF_FUNCTION,ar1
|
ldiu TOP_OF_FUNCTION,ar1
|
lsh 16,ar1
|
lsh 16,ar1
|
or BOTTOM_OF_FUNCTION,ar1
|
or BOTTOM_OF_FUNCTION,ar1
|
ldiu TOP_OF_STATIC,ar0
|
ldiu TOP_OF_STATIC,ar0
|
bud ar1
|
bud ar1
|
lsh 16,ar0
|
lsh 16,ar0
|
or BOTTOM_OF_STATIC,ar0
|
or BOTTOM_OF_STATIC,ar0
|
or 1000h,st
|
or 1000h,st
|
|
|
*/
|
*/
|
|
|
#define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
|
#define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
|
|
|
#define TRAMPOLINE_TEMPLATE(FILE) \
|
#define TRAMPOLINE_TEMPLATE(FILE) \
|
{ \
|
{ \
|
if (TARGET_C3X) \
|
if (TARGET_C3X) \
|
{ \
|
{ \
|
fprintf (FILE, "\tldiu\t0,ar1\n"); \
|
fprintf (FILE, "\tldiu\t0,ar1\n"); \
|
fprintf (FILE, "\tlsh\t16,ar1\n"); \
|
fprintf (FILE, "\tlsh\t16,ar1\n"); \
|
fprintf (FILE, "\tor\t0,ar1\n"); \
|
fprintf (FILE, "\tor\t0,ar1\n"); \
|
fprintf (FILE, "\tldiu\t0,ar0\n"); \
|
fprintf (FILE, "\tldiu\t0,ar0\n"); \
|
fprintf (FILE, "\tbud\tar1\n"); \
|
fprintf (FILE, "\tbud\tar1\n"); \
|
fprintf (FILE, "\tlsh\t16,ar0\n"); \
|
fprintf (FILE, "\tlsh\t16,ar0\n"); \
|
fprintf (FILE, "\tor\t0,ar0\n"); \
|
fprintf (FILE, "\tor\t0,ar0\n"); \
|
fprintf (FILE, "\tor\t1000h,st\n"); \
|
fprintf (FILE, "\tor\t1000h,st\n"); \
|
} \
|
} \
|
else \
|
else \
|
{ \
|
{ \
|
fprintf (FILE, "\tlaj\t$+4\n"); \
|
fprintf (FILE, "\tlaj\t$+4\n"); \
|
fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
|
fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
|
fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
|
fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
|
fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
|
fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
|
fprintf (FILE, "\tbud\tar1\n"); \
|
fprintf (FILE, "\tbud\tar1\n"); \
|
fprintf (FILE, "\tnop\n"); \
|
fprintf (FILE, "\tnop\n"); \
|
fprintf (FILE, "\tnop\n"); \
|
fprintf (FILE, "\tnop\n"); \
|
fprintf (FILE, "\tor\t1000h,st\n"); \
|
fprintf (FILE, "\tor\t1000h,st\n"); \
|
fprintf (FILE, "\t.word\t0\n"); \
|
fprintf (FILE, "\t.word\t0\n"); \
|
fprintf (FILE, "\t.word\t0\n"); \
|
fprintf (FILE, "\t.word\t0\n"); \
|
} \
|
} \
|
}
|
}
|
|
|
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
|
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
|
{ \
|
{ \
|
if (TARGET_C3X) \
|
if (TARGET_C3X) \
|
{ \
|
{ \
|
rtx tmp1, tmp2; \
|
rtx tmp1, tmp2; \
|
tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
|
tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
|
size_int (16), 0, 1); \
|
size_int (16), 0, 1); \
|
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
|
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
|
GEN_INT (0x5069), size_int (16), 0, 1); \
|
GEN_INT (0x5069), size_int (16), 0, 1); \
|
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
|
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
plus_constant (TRAMP, 0)), tmp1); \
|
plus_constant (TRAMP, 0)), tmp1); \
|
tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \
|
tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \
|
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
|
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
|
GEN_INT (0x1069), size_int (16), 0, 1); \
|
GEN_INT (0x1069), size_int (16), 0, 1); \
|
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
|
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
plus_constant (TRAMP, 2)), tmp1); \
|
plus_constant (TRAMP, 2)), tmp1); \
|
tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
|
tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
|
size_int (16), 0, 1); \
|
size_int (16), 0, 1); \
|
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
|
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
|
GEN_INT (0x5068), size_int (16), 0, 1); \
|
GEN_INT (0x5068), size_int (16), 0, 1); \
|
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
|
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
plus_constant (TRAMP, 3)), tmp1); \
|
plus_constant (TRAMP, 3)), tmp1); \
|
tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \
|
tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \
|
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
|
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
|
GEN_INT (0x1068), size_int (16), 0, 1); \
|
GEN_INT (0x1068), size_int (16), 0, 1); \
|
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
|
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
plus_constant (TRAMP, 6)), tmp1); \
|
plus_constant (TRAMP, 6)), tmp1); \
|
} \
|
} \
|
else \
|
else \
|
{ \
|
{ \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
plus_constant (TRAMP, 8)), FNADDR); \
|
plus_constant (TRAMP, 8)), FNADDR); \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
emit_move_insn (gen_rtx_MEM (QImode, \
|
plus_constant (TRAMP, 9)), CXT); \
|
plus_constant (TRAMP, 9)), CXT); \
|
} \
|
} \
|
}
|
}
|
|
|
/* Specify the machine mode that this machine uses for the index in
|
/* Specify the machine mode that this machine uses for the index in
|
the tablejump instruction. */
|
the tablejump instruction. */
|
|
|
#define CASE_VECTOR_MODE Pmode
|
#define CASE_VECTOR_MODE Pmode
|
|
|
/* Max number of (32-bit) bytes we can move from memory to memory
|
/* Max number of (32-bit) bytes we can move from memory to memory
|
in one reasonably fast instruction. */
|
in one reasonably fast instruction. */
|
|
|
#define MOVE_MAX 1
|
#define MOVE_MAX 1
|
|
|
/* MOVE_RATIO is the number of move instructions that is better than a
|
/* MOVE_RATIO is the number of move instructions that is better than a
|
block move. */
|
block move. */
|
|
|
#define MOVE_RATIO 3
|
#define MOVE_RATIO 3
|
|
|
#define BSS_SECTION_ASM_OP "\t.bss"
|
#define BSS_SECTION_ASM_OP "\t.bss"
|
|
|
#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
|
#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
|
fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
|
fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
|
|
|
/* This is how to output an insn to pop a register from the stack.
|
/* This is how to output an insn to pop a register from the stack.
|
It need not be very fast code. */
|
It need not be very fast code. */
|
|
|
#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
|
#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
|
fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
|
fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
|
|
|
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
|
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
|
is done just by pretending it is already truncated. */
|
is done just by pretending it is already truncated. */
|
|
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
|
|
#define DBR_OUTPUT_SEQEND(FILE) \
|
#define DBR_OUTPUT_SEQEND(FILE) \
|
if (final_sequence != NULL_RTX) \
|
if (final_sequence != NULL_RTX) \
|
{ \
|
{ \
|
int count; \
|
int count; \
|
rtx insn = XVECEXP (final_sequence, 0, 0); \
|
rtx insn = XVECEXP (final_sequence, 0, 0); \
|
int laj = GET_CODE (insn) == CALL_INSN \
|
int laj = GET_CODE (insn) == CALL_INSN \
|
|| (GET_CODE (insn) == INSN \
|
|| (GET_CODE (insn) == INSN \
|
&& GET_CODE (PATTERN (insn)) == TRAP_IF);\
|
&& GET_CODE (PATTERN (insn)) == TRAP_IF);\
|
\
|
\
|
count = dbr_sequence_length(); \
|
count = dbr_sequence_length(); \
|
while (count < (laj ? 2 : 3)) \
|
while (count < (laj ? 2 : 3)) \
|
{ \
|
{ \
|
fputs("\tnop\n", FILE); \
|
fputs("\tnop\n", FILE); \
|
count++; \
|
count++; \
|
} \
|
} \
|
if (laj) \
|
if (laj) \
|
fputs("\tpush\tr11\n", FILE); \
|
fputs("\tpush\tr11\n", FILE); \
|
}
|
}
|
|
|
#define NO_FUNCTION_CSE
|
#define NO_FUNCTION_CSE
|
|
|
/* We don't want a leading tab. */
|
/* We don't want a leading tab. */
|
|
|
#define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
|
#define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
|
|
|
/* Define the intrinsic functions for the c3x/c4x. */
|
/* Define the intrinsic functions for the c3x/c4x. */
|
|
|
enum c4x_builtins
|
enum c4x_builtins
|
{
|
{
|
/* intrinsic name */
|
/* intrinsic name */
|
C4X_BUILTIN_FIX, /* fast_ftoi */
|
C4X_BUILTIN_FIX, /* fast_ftoi */
|
C4X_BUILTIN_FIX_ANSI, /* ansi_ftoi */
|
C4X_BUILTIN_FIX_ANSI, /* ansi_ftoi */
|
C4X_BUILTIN_MPYI, /* fast_imult (only C3x) */
|
C4X_BUILTIN_MPYI, /* fast_imult (only C3x) */
|
C4X_BUILTIN_TOIEEE, /* toieee (only C4x) */
|
C4X_BUILTIN_TOIEEE, /* toieee (only C4x) */
|
C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */
|
C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */
|
C4X_BUILTIN_RCPF /* fast_invf (only C4x) */
|
C4X_BUILTIN_RCPF /* fast_invf (only C4x) */
|
};
|
};
|
|
|
|
|
/* Hack to overcome use of libgcc2.c using auto-host.h to determine
|
/* Hack to overcome use of libgcc2.c using auto-host.h to determine
|
HAVE_GAS_HIDDEN. */
|
HAVE_GAS_HIDDEN. */
|
#undef HAVE_GAS_HIDDEN
|
#undef HAVE_GAS_HIDDEN
|
|
|
