;; Predicate definitions for TMS320C[34]x.
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;; Predicate definitions for TMS320C[34]x.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; Nonzero if OP is a floating point value with value 0.0.
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;; Nonzero if OP is a floating point value with value 0.0.
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(define_predicate "fp_zero_operand"
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(define_predicate "fp_zero_operand"
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(match_code "const_double")
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(match_code "const_double")
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{
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{
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REAL_VALUE_TYPE r;
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REAL_VALUE_TYPE r;
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if (GET_CODE (op) != CONST_DOUBLE)
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if (GET_CODE (op) != CONST_DOUBLE)
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return 0;
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return 0;
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REAL_VALUE_FROM_CONST_DOUBLE (r, op);
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REAL_VALUE_FROM_CONST_DOUBLE (r, op);
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return REAL_VALUES_EQUAL (r, dconst0);
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return REAL_VALUES_EQUAL (r, dconst0);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "const_operand"
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(define_predicate "const_operand"
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(match_code "const_int,const_double")
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(match_code "const_int,const_double")
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{
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{
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switch (mode)
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switch (mode)
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{
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{
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case QFmode:
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case QFmode:
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case HFmode:
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case HFmode:
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if (GET_CODE (op) != CONST_DOUBLE
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if (GET_CODE (op) != CONST_DOUBLE
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|| GET_MODE (op) != mode
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|| GET_MODE (op) != mode
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|| GET_MODE_CLASS (mode) != MODE_FLOAT)
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|| GET_MODE_CLASS (mode) != MODE_FLOAT)
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return 0;
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return 0;
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return c4x_immed_float_p (op);
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return c4x_immed_float_p (op);
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#if Pmode != QImode
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#if Pmode != QImode
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case Pmode:
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case Pmode:
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#endif
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#endif
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case QImode:
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case QImode:
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if (GET_CODE (op) != CONST_INT
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if (GET_CODE (op) != CONST_INT
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|| (GET_MODE (op) != VOIDmode && GET_MODE (op) != mode)
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|| (GET_MODE (op) != VOIDmode && GET_MODE (op) != mode)
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|| GET_MODE_CLASS (mode) != MODE_INT)
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|| GET_MODE_CLASS (mode) != MODE_INT)
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return 0;
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return 0;
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return IS_HIGH_CONST (INTVAL (op)) || IS_INT16_CONST (INTVAL (op));
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return IS_HIGH_CONST (INTVAL (op)) || IS_INT16_CONST (INTVAL (op));
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case HImode:
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case HImode:
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return 0;
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return 0;
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default:
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default:
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return 0;
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return 0;
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}
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}
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "stik_const_operand"
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(define_predicate "stik_const_operand"
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(match_code "const_int")
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(match_code "const_int")
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{
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{
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return c4x_K_constant (op);
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return c4x_K_constant (op);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "not_const_operand"
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(define_predicate "not_const_operand"
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(match_code "const_int")
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(match_code "const_int")
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{
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{
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return c4x_N_constant (op);
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return c4x_N_constant (op);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "reg_operand"
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(define_predicate "reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (GET_CODE (op) == SUBREG
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if (GET_CODE (op) == SUBREG
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&& GET_MODE (op) == QFmode)
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&& GET_MODE (op) == QFmode)
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return 0;
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return 0;
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return register_operand (op, mode);
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return register_operand (op, mode);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "reg_or_const_operand"
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(define_predicate "reg_or_const_operand"
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(match_code "reg,subreg,const_int,const_double")
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(match_code "reg,subreg,const_int,const_double")
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{
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{
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return reg_operand (op, mode) || const_operand (op, mode);
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return reg_operand (op, mode) || const_operand (op, mode);
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})
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})
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;; Extended precision register R0-R1.
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;; Extended precision register R0-R1.
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(define_predicate "r0r1_reg_operand"
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(define_predicate "r0r1_reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (! reg_operand (op, mode))
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if (! reg_operand (op, mode))
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return 0;
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return 0;
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if (GET_CODE (op) == SUBREG)
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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op = SUBREG_REG (op);
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return REG_P (op) && IS_R0R1_OR_PSEUDO_REG (op);
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return REG_P (op) && IS_R0R1_OR_PSEUDO_REG (op);
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})
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})
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;; Extended precision register R2-R3.
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;; Extended precision register R2-R3.
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(define_predicate "r2r3_reg_operand"
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(define_predicate "r2r3_reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (! reg_operand (op, mode))
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if (! reg_operand (op, mode))
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return 0;
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return 0;
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if (GET_CODE (op) == SUBREG)
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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op = SUBREG_REG (op);
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return REG_P (op) && IS_R2R3_OR_PSEUDO_REG (op);
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return REG_P (op) && IS_R2R3_OR_PSEUDO_REG (op);
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})
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})
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;; Low extended precision register R0-R7.
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;; Low extended precision register R0-R7.
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(define_predicate "ext_low_reg_operand"
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(define_predicate "ext_low_reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (! reg_operand (op, mode))
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if (! reg_operand (op, mode))
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return 0;
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return 0;
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if (GET_CODE (op) == SUBREG)
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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op = SUBREG_REG (op);
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return REG_P (op) && IS_EXT_LOW_OR_PSEUDO_REG (op);
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return REG_P (op) && IS_EXT_LOW_OR_PSEUDO_REG (op);
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})
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})
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;; Extended precision register.
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;; Extended precision register.
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(define_predicate "ext_reg_operand"
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(define_predicate "ext_reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (! reg_operand (op, mode))
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if (! reg_operand (op, mode))
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return 0;
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return 0;
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if (GET_CODE (op) == SUBREG)
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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op = SUBREG_REG (op);
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if (! REG_P (op))
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if (! REG_P (op))
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return 0;
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return 0;
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return IS_EXT_OR_PSEUDO_REG (op);
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return IS_EXT_OR_PSEUDO_REG (op);
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})
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})
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;; Standard precision register.
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;; Standard precision register.
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(define_predicate "std_reg_operand"
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(define_predicate "std_reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (! reg_operand (op, mode))
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if (! reg_operand (op, mode))
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return 0;
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return 0;
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if (GET_CODE (op) == SUBREG)
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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op = SUBREG_REG (op);
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return REG_P (op) && IS_STD_OR_PSEUDO_REG (op);
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return REG_P (op) && IS_STD_OR_PSEUDO_REG (op);
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})
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})
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;; Standard precision or normal register.
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;; Standard precision or normal register.
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(define_predicate "std_or_reg_operand"
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(define_predicate "std_or_reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (reload_in_progress)
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if (reload_in_progress)
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return std_reg_operand (op, mode);
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return std_reg_operand (op, mode);
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return reg_operand (op, mode);
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return reg_operand (op, mode);
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})
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})
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;; Address register.
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;; Address register.
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(define_predicate "addr_reg_operand"
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(define_predicate "addr_reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (! reg_operand (op, mode))
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if (! reg_operand (op, mode))
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return 0;
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return 0;
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return c4x_a_register (op);
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return c4x_a_register (op);
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})
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})
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;; Index register.
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;; Index register.
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(define_predicate "index_reg_operand"
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(define_predicate "index_reg_operand"
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(match_code "reg,subreg")
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(match_code "reg,subreg")
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{
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{
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if (! reg_operand (op, mode))
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if (! reg_operand (op, mode))
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return 0;
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return 0;
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if (GET_CODE (op) == SUBREG)
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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op = SUBREG_REG (op);
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return c4x_x_register (op);
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return c4x_x_register (op);
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})
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})
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;; DP register.
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;; DP register.
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(define_predicate "dp_reg_operand"
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(define_predicate "dp_reg_operand"
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(match_code "reg")
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(match_code "reg")
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{
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{
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return REG_P (op) && IS_DP_OR_PSEUDO_REG (op);
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return REG_P (op) && IS_DP_OR_PSEUDO_REG (op);
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})
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})
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;; SP register.
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;; SP register.
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(define_predicate "sp_reg_operand"
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(define_predicate "sp_reg_operand"
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(match_code "reg")
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(match_code "reg")
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{
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{
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return REG_P (op) && IS_SP_OR_PSEUDO_REG (op);
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return REG_P (op) && IS_SP_OR_PSEUDO_REG (op);
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})
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})
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;; ST register.
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;; ST register.
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(define_predicate "st_reg_operand"
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(define_predicate "st_reg_operand"
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(match_code "reg")
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(match_code "reg")
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{
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{
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return REG_P (op) && IS_ST_OR_PSEUDO_REG (op);
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return REG_P (op) && IS_ST_OR_PSEUDO_REG (op);
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})
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})
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;; RC register.
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;; RC register.
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(define_predicate "rc_reg_operand"
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(define_predicate "rc_reg_operand"
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(match_code "reg")
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(match_code "reg")
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{
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{
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return REG_P (op) && IS_RC_OR_PSEUDO_REG (op);
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return REG_P (op) && IS_RC_OR_PSEUDO_REG (op);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "call_address_operand"
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(define_predicate "call_address_operand"
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(match_code "reg,symbol_ref,label_ref,const")
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(match_code "reg,symbol_ref,label_ref,const")
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{
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{
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return (REG_P (op) || symbolic_address_operand (op, mode));
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return (REG_P (op) || symbolic_address_operand (op, mode));
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})
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})
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;; Check dst operand of a move instruction.
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;; Check dst operand of a move instruction.
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(define_predicate "dst_operand"
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(define_predicate "dst_operand"
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(match_code "subreg,reg,mem")
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(match_code "subreg,reg,mem")
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{
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{
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if (GET_CODE (op) == SUBREG
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if (GET_CODE (op) == SUBREG
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&& mixed_subreg_operand (op, mode))
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&& mixed_subreg_operand (op, mode))
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return 0;
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return 0;
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if (REG_P (op))
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if (REG_P (op))
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return reg_operand (op, mode);
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return reg_operand (op, mode);
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return nonimmediate_operand (op, mode);
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return nonimmediate_operand (op, mode);
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})
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})
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;; Check src operand of two operand arithmetic instructions.
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;; Check src operand of two operand arithmetic instructions.
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(define_predicate "src_operand"
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(define_predicate "src_operand"
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(match_code "subreg,reg,mem,const_int,const_double")
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(match_code "subreg,reg,mem,const_int,const_double")
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{
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{
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if (GET_CODE (op) == SUBREG
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if (GET_CODE (op) == SUBREG
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&& mixed_subreg_operand (op, mode))
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&& mixed_subreg_operand (op, mode))
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return 0;
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return 0;
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if (REG_P (op))
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if (REG_P (op))
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return reg_operand (op, mode);
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return reg_operand (op, mode);
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if (mode == VOIDmode)
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if (mode == VOIDmode)
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mode = GET_MODE (op);
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mode = GET_MODE (op);
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if (GET_CODE (op) == CONST_INT)
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if (GET_CODE (op) == CONST_INT)
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return (mode == QImode || mode == Pmode || mode == HImode)
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return (mode == QImode || mode == Pmode || mode == HImode)
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&& c4x_I_constant (op);
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&& c4x_I_constant (op);
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/* We don't like CONST_DOUBLE integers. */
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/* We don't like CONST_DOUBLE integers. */
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if (GET_CODE (op) == CONST_DOUBLE)
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if (GET_CODE (op) == CONST_DOUBLE)
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return c4x_H_constant (op);
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return c4x_H_constant (op);
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/* Disallow symbolic addresses. Only the predicate
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/* Disallow symbolic addresses. Only the predicate
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symbolic_address_operand will match these. */
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symbolic_address_operand will match these. */
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if (GET_CODE (op) == SYMBOL_REF
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if (GET_CODE (op) == SYMBOL_REF
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|| GET_CODE (op) == LABEL_REF
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|| GET_CODE (op) == LABEL_REF
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|| GET_CODE (op) == CONST)
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|| GET_CODE (op) == CONST)
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return 0;
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return 0;
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/* If TARGET_LOAD_DIRECT_MEMS is nonzero, disallow direct memory
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/* If TARGET_LOAD_DIRECT_MEMS is nonzero, disallow direct memory
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access to symbolic addresses. These operands will get forced
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access to symbolic addresses. These operands will get forced
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into a register and the movqi expander will generate a
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into a register and the movqi expander will generate a
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HIGH/LO_SUM pair if TARGET_EXPOSE_LDP is nonzero. */
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HIGH/LO_SUM pair if TARGET_EXPOSE_LDP is nonzero. */
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if (GET_CODE (op) == MEM
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if (GET_CODE (op) == MEM
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&& ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
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&& ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
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|| GET_CODE (XEXP (op, 0)) == LABEL_REF
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|| GET_CODE (XEXP (op, 0)) == LABEL_REF
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|| GET_CODE (XEXP (op, 0)) == CONST)))
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|| GET_CODE (XEXP (op, 0)) == CONST)))
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return !TARGET_EXPOSE_LDP &&
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return !TARGET_EXPOSE_LDP &&
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! TARGET_LOAD_DIRECT_MEMS && GET_MODE (op) == mode;
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! TARGET_LOAD_DIRECT_MEMS && GET_MODE (op) == mode;
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return general_operand (op, mode);
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return general_operand (op, mode);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "src_hi_operand"
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(define_predicate "src_hi_operand"
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(match_code "subreg,reg,mem,const_double")
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(match_code "subreg,reg,mem,const_double")
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{
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{
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if (c4x_O_constant (op))
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if (c4x_O_constant (op))
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return 1;
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return 1;
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return src_operand (op, mode);
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return src_operand (op, mode);
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})
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})
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;; Check src operand of two operand logical instructions.
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;; Check src operand of two operand logical instructions.
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(define_predicate "lsrc_operand"
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(define_predicate "lsrc_operand"
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(match_code "subreg,reg,mem,const_int,const_double")
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(match_code "subreg,reg,mem,const_int,const_double")
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{
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{
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if (mode == VOIDmode)
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if (mode == VOIDmode)
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mode = GET_MODE (op);
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mode = GET_MODE (op);
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if (mode != QImode && mode != Pmode)
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if (mode != QImode && mode != Pmode)
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fatal_insn ("mode not QImode", op);
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fatal_insn ("mode not QImode", op);
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|
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if (GET_CODE (op) == CONST_INT)
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if (GET_CODE (op) == CONST_INT)
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return c4x_L_constant (op) || c4x_J_constant (op);
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return c4x_L_constant (op) || c4x_J_constant (op);
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return src_operand (op, mode);
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return src_operand (op, mode);
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})
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})
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;; Check src operand of two operand tricky instructions.
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;; Check src operand of two operand tricky instructions.
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(define_predicate "tsrc_operand"
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(define_predicate "tsrc_operand"
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(match_code "subreg,reg,mem,const_int,const_double")
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(match_code "subreg,reg,mem,const_int,const_double")
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{
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{
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if (mode == VOIDmode)
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if (mode == VOIDmode)
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mode = GET_MODE (op);
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mode = GET_MODE (op);
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|
|
if (mode != QImode && mode != Pmode)
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if (mode != QImode && mode != Pmode)
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fatal_insn ("mode not QImode", op);
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fatal_insn ("mode not QImode", op);
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|
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if (GET_CODE (op) == CONST_INT)
|
if (GET_CODE (op) == CONST_INT)
|
return c4x_L_constant (op) || c4x_N_constant (op) || c4x_J_constant (op);
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return c4x_L_constant (op) || c4x_N_constant (op) || c4x_J_constant (op);
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|
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return src_operand (op, mode);
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return src_operand (op, mode);
|
})
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})
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;; Check src operand of two operand non immediate instructions.
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;; Check src operand of two operand non immediate instructions.
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|
|
(define_predicate "nonimmediate_src_operand"
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(define_predicate "nonimmediate_src_operand"
|
(match_code "subreg,reg,mem")
|
(match_code "subreg,reg,mem")
|
{
|
{
|
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
|
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
|
return 0;
|
return 0;
|
|
|
return src_operand (op, mode);
|
return src_operand (op, mode);
|
})
|
})
|
|
|
;; Check logical src operand of two operand non immediate instructions.
|
;; Check logical src operand of two operand non immediate instructions.
|
|
|
(define_predicate "nonimmediate_lsrc_operand"
|
(define_predicate "nonimmediate_lsrc_operand"
|
(match_code "subreg,reg,mem")
|
(match_code "subreg,reg,mem")
|
{
|
{
|
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
|
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
|
return 0;
|
return 0;
|
|
|
return lsrc_operand (op, mode);
|
return lsrc_operand (op, mode);
|
})
|
})
|
|
|
;; Match any operand.
|
;; Match any operand.
|
|
|
(define_predicate "any_operand"
|
(define_predicate "any_operand"
|
(match_code "subreg,reg,mem,const_int,const_double")
|
(match_code "subreg,reg,mem,const_int,const_double")
|
{
|
{
|
return 1;
|
return 1;
|
})
|
})
|
|
|
;; Check for indirect operands allowable in parallel instruction.
|
;; Check for indirect operands allowable in parallel instruction.
|
|
|
(define_predicate "par_ind_operand"
|
(define_predicate "par_ind_operand"
|
(match_code "mem")
|
(match_code "mem")
|
{
|
{
|
if (mode != VOIDmode && mode != GET_MODE (op))
|
if (mode != VOIDmode && mode != GET_MODE (op))
|
return 0;
|
return 0;
|
|
|
return c4x_S_indirect (op);
|
return c4x_S_indirect (op);
|
})
|
})
|
|
|
;; Check for operands allowable in parallel instruction.
|
;; Check for operands allowable in parallel instruction.
|
|
|
(define_predicate "parallel_operand"
|
(define_predicate "parallel_operand"
|
(match_code "subreg,reg,mem")
|
(match_code "subreg,reg,mem")
|
{
|
{
|
return ext_low_reg_operand (op, mode) || par_ind_operand (op, mode);
|
return ext_low_reg_operand (op, mode) || par_ind_operand (op, mode);
|
})
|
})
|
|
|
;; Symbolic address operand.
|
;; Symbolic address operand.
|
|
|
(define_predicate "symbolic_address_operand"
|
(define_predicate "symbolic_address_operand"
|
(match_code "symbol_ref,label_ref,const")
|
(match_code "symbol_ref,label_ref,const")
|
{
|
{
|
switch (GET_CODE (op))
|
switch (GET_CODE (op))
|
{
|
{
|
case CONST:
|
case CONST:
|
case SYMBOL_REF:
|
case SYMBOL_REF:
|
case LABEL_REF:
|
case LABEL_REF:
|
return 1;
|
return 1;
|
default:
|
default:
|
return 0;
|
return 0;
|
}
|
}
|
})
|
})
|
|
|
