;; GCC machine description for i386 synchronization instructions.
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;; GCC machine description for i386 synchronization instructions.
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;; Copyright (C) 2005, 2006, 2007
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;; Copyright (C) 2005, 2006, 2007
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;; Free Software Foundation, Inc.
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;; Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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(define_mode_macro IMODE [QI HI SI (DI "TARGET_64BIT")])
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(define_mode_macro IMODE [QI HI SI (DI "TARGET_64BIT")])
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(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
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(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
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(define_mode_attr modeconstraint [(QI "q") (HI "r") (SI "r") (DI "r")])
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(define_mode_attr modeconstraint [(QI "q") (HI "r") (SI "r") (DI "r")])
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(define_mode_attr immconstraint [(QI "i") (HI "i") (SI "i") (DI "e")])
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(define_mode_attr immconstraint [(QI "i") (HI "i") (SI "i") (DI "e")])
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(define_mode_macro CASMODE [QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B")
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(define_mode_macro CASMODE [QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B")
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(TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
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(TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
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(define_mode_macro DCASMODE
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(define_mode_macro DCASMODE
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[(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic")
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[(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic")
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(TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
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(TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
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(define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
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(define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
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(define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
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(define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
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;; ??? It would be possible to use cmpxchg8b on pentium for DImode
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;; ??? It would be possible to use cmpxchg8b on pentium for DImode
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;; changes. It's complicated because the insn uses ecx:ebx as the
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;; changes. It's complicated because the insn uses ecx:ebx as the
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;; new value; note that the registers are reversed from the order
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;; new value; note that the registers are reversed from the order
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;; that they'd be in with (reg:DI 2 ecx). Similarly for TImode
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;; that they'd be in with (reg:DI 2 ecx). Similarly for TImode
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;; data in 64-bit mode.
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;; data in 64-bit mode.
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(define_expand "sync_compare_and_swap"
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(define_expand "sync_compare_and_swap"
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[(parallel
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[(parallel
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[(set (match_operand:CASMODE 0 "register_operand" "")
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[(set (match_operand:CASMODE 0 "register_operand" "")
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(match_operand:CASMODE 1 "memory_operand" ""))
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(match_operand:CASMODE 1 "memory_operand" ""))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec_volatile:CASMODE
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(unspec_volatile:CASMODE
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[(match_dup 1)
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[(match_dup 1)
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(match_operand:CASMODE 2 "register_operand" "")
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(match_operand:CASMODE 2 "register_operand" "")
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(match_operand:CASMODE 3 "register_operand" "")]
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(match_operand:CASMODE 3 "register_operand" "")]
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UNSPECV_CMPXCHG_1))
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UNSPECV_CMPXCHG_1))
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(clobber (reg:CC FLAGS_REG))])]
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_CMPXCHG"
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"TARGET_CMPXCHG"
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{
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{
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if ((mode == DImode && !TARGET_64BIT) || mode == TImode)
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if ((mode == DImode && !TARGET_64BIT) || mode == TImode)
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{
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{
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enum machine_mode hmode = mode == DImode ? SImode : DImode;
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enum machine_mode hmode = mode == DImode ? SImode : DImode;
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rtx low = simplify_gen_subreg (hmode, operands[3], mode, 0);
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rtx low = simplify_gen_subreg (hmode, operands[3], mode, 0);
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rtx high = simplify_gen_subreg (hmode, operands[3], mode,
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rtx high = simplify_gen_subreg (hmode, operands[3], mode,
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GET_MODE_SIZE (hmode));
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GET_MODE_SIZE (hmode));
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low = force_reg (hmode, low);
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low = force_reg (hmode, low);
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high = force_reg (hmode, high);
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high = force_reg (hmode, high);
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if (mode == DImode)
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if (mode == DImode)
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emit_insn (gen_sync_double_compare_and_swapdi
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emit_insn (gen_sync_double_compare_and_swapdi
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(operands[0], operands[1], operands[2], low, high));
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(operands[0], operands[1], operands[2], low, high));
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else if (mode == TImode)
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else if (mode == TImode)
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emit_insn (gen_sync_double_compare_and_swapti
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emit_insn (gen_sync_double_compare_and_swapti
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(operands[0], operands[1], operands[2], low, high));
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(operands[0], operands[1], operands[2], low, high));
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else
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else
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gcc_unreachable ();
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gcc_unreachable ();
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DONE;
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DONE;
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}
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}
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})
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})
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(define_insn "*sync_compare_and_swap"
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(define_insn "*sync_compare_and_swap"
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[(set (match_operand:IMODE 0 "register_operand" "=a")
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[(set (match_operand:IMODE 0 "register_operand" "=a")
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(match_operand:IMODE 1 "memory_operand" "+m"))
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(match_operand:IMODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec_volatile:IMODE
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(unspec_volatile:IMODE
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[(match_dup 1)
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[(match_dup 1)
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(match_operand:IMODE 2 "register_operand" "a")
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(match_operand:IMODE 2 "register_operand" "a")
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(match_operand:IMODE 3 "register_operand" "")]
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(match_operand:IMODE 3 "register_operand" "")]
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UNSPECV_CMPXCHG_1))
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UNSPECV_CMPXCHG_1))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_CMPXCHG"
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"TARGET_CMPXCHG"
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"lock\;cmpxchg{}\t{%3, %1|%1, %3}")
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"lock\;cmpxchg{}\t{%3, %1|%1, %3}")
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(define_insn "sync_double_compare_and_swap"
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(define_insn "sync_double_compare_and_swap"
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[(set (match_operand:DCASMODE 0 "register_operand" "=A")
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[(set (match_operand:DCASMODE 0 "register_operand" "=A")
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(match_operand:DCASMODE 1 "memory_operand" "+m"))
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(match_operand:DCASMODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec_volatile:DCASMODE
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(unspec_volatile:DCASMODE
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[(match_dup 1)
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[(match_dup 1)
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(match_operand:DCASMODE 2 "register_operand" "A")
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(match_operand:DCASMODE 2 "register_operand" "A")
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(match_operand: 3 "register_operand" "b")
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(match_operand: 3 "register_operand" "b")
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(match_operand: 4 "register_operand" "c")]
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(match_operand: 4 "register_operand" "c")]
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UNSPECV_CMPXCHG_1))
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UNSPECV_CMPXCHG_1))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
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""
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""
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"lock\;cmpxchgb\t%1")
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"lock\;cmpxchgb\t%1")
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;; Theoretically we'd like to use constraint "r" (any reg) for operand
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;; Theoretically we'd like to use constraint "r" (any reg) for operand
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;; 3, but that includes ecx. If operand 3 and 4 are the same (like when
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;; 3, but that includes ecx. If operand 3 and 4 are the same (like when
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;; the input is -1LL) GCC might chose to allocate operand 3 to ecx, like
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;; the input is -1LL) GCC might chose to allocate operand 3 to ecx, like
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;; operand 4. This breaks, as the xchg will move the PIC register contents
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;; operand 4. This breaks, as the xchg will move the PIC register contents
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;; to %ecx then --> boom. Operands 3 and 4 really need to be different
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;; to %ecx then --> boom. Operands 3 and 4 really need to be different
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;; registers, which in this case means operand 3 must not be ecx.
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;; registers, which in this case means operand 3 must not be ecx.
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;; Instead of playing tricks with fake early clobbers or the like we
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;; Instead of playing tricks with fake early clobbers or the like we
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;; just enumerate all regs possible here, which (as this is !TARGET_64BIT)
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;; just enumerate all regs possible here, which (as this is !TARGET_64BIT)
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;; are just esi and edi.
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;; are just esi and edi.
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(define_insn "*sync_double_compare_and_swapdi_pic"
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(define_insn "*sync_double_compare_and_swapdi_pic"
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[(set (match_operand:DI 0 "register_operand" "=A")
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[(set (match_operand:DI 0 "register_operand" "=A")
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(match_operand:DI 1 "memory_operand" "+m"))
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(match_operand:DI 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec_volatile:DI
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(unspec_volatile:DI
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[(match_dup 1)
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[(match_dup 1)
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(match_operand:DI 2 "register_operand" "A")
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(match_operand:DI 2 "register_operand" "A")
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(match_operand:SI 3 "register_operand" "SD")
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(match_operand:SI 3 "register_operand" "SD")
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(match_operand:SI 4 "register_operand" "c")]
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(match_operand:SI 4 "register_operand" "c")]
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UNSPECV_CMPXCHG_1))
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UNSPECV_CMPXCHG_1))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
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"!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
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"xchg{l}\t%%ebx, %3\;lock\;cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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"xchg{l}\t%%ebx, %3\;lock\;cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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(define_expand "sync_compare_and_swap_cc"
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(define_expand "sync_compare_and_swap_cc"
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[(parallel
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[(parallel
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[(set (match_operand:CASMODE 0 "register_operand" "")
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[(set (match_operand:CASMODE 0 "register_operand" "")
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(match_operand:CASMODE 1 "memory_operand" ""))
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(match_operand:CASMODE 1 "memory_operand" ""))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec_volatile:CASMODE
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(unspec_volatile:CASMODE
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[(match_dup 1)
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[(match_dup 1)
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(match_operand:CASMODE 2 "register_operand" "")
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(match_operand:CASMODE 2 "register_operand" "")
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(match_operand:CASMODE 3 "register_operand" "")]
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(match_operand:CASMODE 3 "register_operand" "")]
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UNSPECV_CMPXCHG_1))
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UNSPECV_CMPXCHG_1))
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(set (match_dup 4)
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(set (match_dup 4)
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(compare:CCZ
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(compare:CCZ
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(unspec_volatile:CASMODE
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(unspec_volatile:CASMODE
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2)
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2)
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(match_dup 2)))])]
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(match_dup 2)))])]
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"TARGET_CMPXCHG"
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"TARGET_CMPXCHG"
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{
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{
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operands[4] = gen_rtx_REG (CCZmode, FLAGS_REG);
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operands[4] = gen_rtx_REG (CCZmode, FLAGS_REG);
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ix86_compare_op0 = operands[3];
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ix86_compare_op0 = operands[3];
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ix86_compare_op1 = NULL;
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ix86_compare_op1 = NULL;
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ix86_compare_emitted = operands[4];
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ix86_compare_emitted = operands[4];
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if ((mode == DImode && !TARGET_64BIT) || mode == TImode)
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if ((mode == DImode && !TARGET_64BIT) || mode == TImode)
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{
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{
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enum machine_mode hmode = mode == DImode ? SImode : DImode;
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enum machine_mode hmode = mode == DImode ? SImode : DImode;
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rtx low = simplify_gen_subreg (hmode, operands[3], mode, 0);
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rtx low = simplify_gen_subreg (hmode, operands[3], mode, 0);
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rtx high = simplify_gen_subreg (hmode, operands[3], mode,
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rtx high = simplify_gen_subreg (hmode, operands[3], mode,
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GET_MODE_SIZE (hmode));
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GET_MODE_SIZE (hmode));
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low = force_reg (hmode, low);
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low = force_reg (hmode, low);
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high = force_reg (hmode, high);
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high = force_reg (hmode, high);
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if (mode == DImode)
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if (mode == DImode)
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emit_insn (gen_sync_double_compare_and_swap_ccdi
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emit_insn (gen_sync_double_compare_and_swap_ccdi
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(operands[0], operands[1], operands[2], low, high));
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(operands[0], operands[1], operands[2], low, high));
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else if (mode == TImode)
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else if (mode == TImode)
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emit_insn (gen_sync_double_compare_and_swap_ccti
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emit_insn (gen_sync_double_compare_and_swap_ccti
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(operands[0], operands[1], operands[2], low, high));
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(operands[0], operands[1], operands[2], low, high));
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else
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else
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gcc_unreachable ();
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gcc_unreachable ();
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DONE;
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DONE;
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}
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}
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})
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})
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(define_insn "*sync_compare_and_swap_cc"
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(define_insn "*sync_compare_and_swap_cc"
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[(set (match_operand:IMODE 0 "register_operand" "=a")
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[(set (match_operand:IMODE 0 "register_operand" "=a")
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(match_operand:IMODE 1 "memory_operand" "+m"))
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(match_operand:IMODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec_volatile:IMODE
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(unspec_volatile:IMODE
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[(match_dup 1)
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[(match_dup 1)
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(match_operand:IMODE 2 "register_operand" "a")
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(match_operand:IMODE 2 "register_operand" "a")
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(match_operand:IMODE 3 "register_operand" "")]
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(match_operand:IMODE 3 "register_operand" "")]
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UNSPECV_CMPXCHG_1))
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UNSPECV_CMPXCHG_1))
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(set (reg:CCZ FLAGS_REG)
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(set (reg:CCZ FLAGS_REG)
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(compare:CCZ
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(compare:CCZ
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(unspec_volatile:IMODE
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(unspec_volatile:IMODE
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2)
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[(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2)
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(match_dup 2)))]
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(match_dup 2)))]
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"TARGET_CMPXCHG"
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"TARGET_CMPXCHG"
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"lock\;cmpxchg{}\t{%3, %1|%1, %3}")
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"lock\;cmpxchg{}\t{%3, %1|%1, %3}")
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(define_insn "sync_double_compare_and_swap_cc"
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(define_insn "sync_double_compare_and_swap_cc"
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[(set (match_operand:DCASMODE 0 "register_operand" "=A")
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[(set (match_operand:DCASMODE 0 "register_operand" "=A")
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(match_operand:DCASMODE 1 "memory_operand" "+m"))
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(match_operand:DCASMODE 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec_volatile:DCASMODE
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(unspec_volatile:DCASMODE
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[(match_dup 1)
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[(match_dup 1)
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(match_operand:DCASMODE 2 "register_operand" "A")
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(match_operand:DCASMODE 2 "register_operand" "A")
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(match_operand: 3 "register_operand" "b")
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(match_operand: 3 "register_operand" "b")
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(match_operand: 4 "register_operand" "c")]
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(match_operand: 4 "register_operand" "c")]
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UNSPECV_CMPXCHG_1))
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UNSPECV_CMPXCHG_1))
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(set (reg:CCZ FLAGS_REG)
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(set (reg:CCZ FLAGS_REG)
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(compare:CCZ
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(compare:CCZ
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(unspec_volatile:DCASMODE
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(unspec_volatile:DCASMODE
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[(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
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[(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
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UNSPECV_CMPXCHG_2)
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UNSPECV_CMPXCHG_2)
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(match_dup 2)))]
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(match_dup 2)))]
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""
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""
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"lock\;cmpxchgb\t%1")
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"lock\;cmpxchgb\t%1")
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;; See above for the explanation of using the constraint "SD" for
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;; See above for the explanation of using the constraint "SD" for
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;; operand 3.
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;; operand 3.
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(define_insn "*sync_double_compare_and_swap_ccdi_pic"
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(define_insn "*sync_double_compare_and_swap_ccdi_pic"
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[(set (match_operand:DI 0 "register_operand" "=A")
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[(set (match_operand:DI 0 "register_operand" "=A")
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(match_operand:DI 1 "memory_operand" "+m"))
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(match_operand:DI 1 "memory_operand" "+m"))
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(set (match_dup 1)
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(set (match_dup 1)
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(unspec_volatile:DI
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(unspec_volatile:DI
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[(match_dup 1)
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[(match_dup 1)
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(match_operand:DI 2 "register_operand" "A")
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(match_operand:DI 2 "register_operand" "A")
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(match_operand:SI 3 "register_operand" "SD")
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(match_operand:SI 3 "register_operand" "SD")
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(match_operand:SI 4 "register_operand" "c")]
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(match_operand:SI 4 "register_operand" "c")]
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UNSPECV_CMPXCHG_1))
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UNSPECV_CMPXCHG_1))
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(set (reg:CCZ FLAGS_REG)
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(set (reg:CCZ FLAGS_REG)
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(compare:CCZ
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(compare:CCZ
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(unspec_volatile:DI
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(unspec_volatile:DI
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[(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
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[(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
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UNSPECV_CMPXCHG_2)
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UNSPECV_CMPXCHG_2)
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(match_dup 2)))]
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(match_dup 2)))]
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"!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
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"!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
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"xchg{l}\t%%ebx, %3\;lock\;cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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"xchg{l}\t%%ebx, %3\;lock\;cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
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(define_insn "sync_old_add"
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(define_insn "sync_old_add"
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[(set (match_operand:IMODE 0 "register_operand" "=")
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[(set (match_operand:IMODE 0 "register_operand" "=")
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(unspec_volatile:IMODE
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(unspec_volatile:IMODE
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[(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
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[(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
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(set (match_dup 1)
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(set (match_dup 1)
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(plus:IMODE (match_dup 1)
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(plus:IMODE (match_dup 1)
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(match_operand:IMODE 2 "register_operand" "0")))
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(match_operand:IMODE 2 "register_operand" "0")))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_XADD"
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"TARGET_XADD"
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"lock\;xadd{}\t{%0, %1|%1, %0}")
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"lock\;xadd{}\t{%0, %1|%1, %0}")
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;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
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;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
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(define_insn "sync_lock_test_and_set"
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(define_insn "sync_lock_test_and_set"
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[(set (match_operand:IMODE 0 "register_operand" "=")
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[(set (match_operand:IMODE 0 "register_operand" "=")
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(unspec_volatile:IMODE
|
(unspec_volatile:IMODE
|
[(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
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[(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
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(set (match_dup 1)
|
(set (match_dup 1)
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(match_operand:IMODE 2 "register_operand" "0"))]
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(match_operand:IMODE 2 "register_operand" "0"))]
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""
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""
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"xchg{}\t{%1, %0|%0, %1}")
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"xchg{}\t{%1, %0|%0, %1}")
|
|
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(define_insn "sync_add"
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(define_insn "sync_add"
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[(set (match_operand:IMODE 0 "memory_operand" "+m")
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[(set (match_operand:IMODE 0 "memory_operand" "+m")
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(unspec_volatile:IMODE
|
(unspec_volatile:IMODE
|
[(plus:IMODE (match_dup 0)
|
[(plus:IMODE (match_dup 0)
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(match_operand:IMODE 1 "nonmemory_operand" ""))]
|
(match_operand:IMODE 1 "nonmemory_operand" ""))]
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UNSPECV_LOCK))
|
UNSPECV_LOCK))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
|
""
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""
|
"lock\;add{}\t{%1, %0|%0, %1}")
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"lock\;add{}\t{%1, %0|%0, %1}")
|
|
|
(define_insn "sync_sub"
|
(define_insn "sync_sub"
|
[(set (match_operand:IMODE 0 "memory_operand" "+m")
|
[(set (match_operand:IMODE 0 "memory_operand" "+m")
|
(unspec_volatile:IMODE
|
(unspec_volatile:IMODE
|
[(minus:IMODE (match_dup 0)
|
[(minus:IMODE (match_dup 0)
|
(match_operand:IMODE 1 "nonmemory_operand" ""))]
|
(match_operand:IMODE 1 "nonmemory_operand" ""))]
|
UNSPECV_LOCK))
|
UNSPECV_LOCK))
|
(clobber (reg:CC FLAGS_REG))]
|
(clobber (reg:CC FLAGS_REG))]
|
""
|
""
|
"lock\;sub{}\t{%1, %0|%0, %1}")
|
"lock\;sub{}\t{%1, %0|%0, %1}")
|
|
|
(define_insn "sync_ior"
|
(define_insn "sync_ior"
|
[(set (match_operand:IMODE 0 "memory_operand" "+m")
|
[(set (match_operand:IMODE 0 "memory_operand" "+m")
|
(unspec_volatile:IMODE
|
(unspec_volatile:IMODE
|
[(ior:IMODE (match_dup 0)
|
[(ior:IMODE (match_dup 0)
|
(match_operand:IMODE 1 "nonmemory_operand" ""))]
|
(match_operand:IMODE 1 "nonmemory_operand" ""))]
|
UNSPECV_LOCK))
|
UNSPECV_LOCK))
|
(clobber (reg:CC FLAGS_REG))]
|
(clobber (reg:CC FLAGS_REG))]
|
""
|
""
|
"lock\;or{}\t{%1, %0|%0, %1}")
|
"lock\;or{}\t{%1, %0|%0, %1}")
|
|
|
(define_insn "sync_and"
|
(define_insn "sync_and"
|
[(set (match_operand:IMODE 0 "memory_operand" "+m")
|
[(set (match_operand:IMODE 0 "memory_operand" "+m")
|
(unspec_volatile:IMODE
|
(unspec_volatile:IMODE
|
[(and:IMODE (match_dup 0)
|
[(and:IMODE (match_dup 0)
|
(match_operand:IMODE 1 "nonmemory_operand" ""))]
|
(match_operand:IMODE 1 "nonmemory_operand" ""))]
|
UNSPECV_LOCK))
|
UNSPECV_LOCK))
|
(clobber (reg:CC FLAGS_REG))]
|
(clobber (reg:CC FLAGS_REG))]
|
""
|
""
|
"lock\;and{}\t{%1, %0|%0, %1}")
|
"lock\;and{}\t{%1, %0|%0, %1}")
|
|
|
(define_insn "sync_xor"
|
(define_insn "sync_xor"
|
[(set (match_operand:IMODE 0 "memory_operand" "+m")
|
[(set (match_operand:IMODE 0 "memory_operand" "+m")
|
(unspec_volatile:IMODE
|
(unspec_volatile:IMODE
|
[(xor:IMODE (match_dup 0)
|
[(xor:IMODE (match_dup 0)
|
(match_operand:IMODE 1 "nonmemory_operand" ""))]
|
(match_operand:IMODE 1 "nonmemory_operand" ""))]
|
UNSPECV_LOCK))
|
UNSPECV_LOCK))
|
(clobber (reg:CC FLAGS_REG))]
|
(clobber (reg:CC FLAGS_REG))]
|
""
|
""
|
"lock\;xor{}\t{%1, %0|%0, %1}")
|
"lock\;xor{}\t{%1, %0|%0, %1}")
|
|
|
