;; Machine Descriptions for R8C/M16C/M32C
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;; Machine Descriptions for R8C/M16C/M32C
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;; Copyright (C) 2005, 2007
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;; Copyright (C) 2005, 2007
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;; Free Software Foundation, Inc.
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;; Contributed by Red Hat.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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|
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;; Bit-wise operations (and, ior, xor, shift)
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;; Bit-wise operations (and, ior, xor, shift)
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|
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; On the R8C and M16C, "address" for bit instructions is usually (but
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; On the R8C and M16C, "address" for bit instructions is usually (but
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; not always!) the *bit* address, not the *byte* address. This
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; not always!) the *bit* address, not the *byte* address. This
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; confuses gcc, so we avoid cases where gcc would produce the wrong
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; confuses gcc, so we avoid cases where gcc would produce the wrong
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; code. We're left with absolute addresses and registers, and the odd
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; code. We're left with absolute addresses and registers, and the odd
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; case of shifting a bit by a variable.
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; case of shifting a bit by a variable.
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; On the M32C, "address" for bit instructions is a regular address,
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; On the M32C, "address" for bit instructions is a regular address,
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; and the bit number is stored in a separate field. Thus, we can let
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; and the bit number is stored in a separate field. Thus, we can let
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; gcc do more interesting things. However, the M32C cannot set all
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; gcc do more interesting things. However, the M32C cannot set all
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; the bits in a 16 bit register, which the R8C/M16C can do.
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; the bits in a 16 bit register, which the R8C/M16C can do.
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|
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; However, it all means that we end up with two sets of patterns, one
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; However, it all means that we end up with two sets of patterns, one
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; for each chip.
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; for each chip.
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;;----------------------------------------------------------------------
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;;----------------------------------------------------------------------
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;; First off, all the ways we can set one bit, other than plain IOR.
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;; First off, all the ways we can set one bit, other than plain IOR.
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(define_insn "bset_qi"
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(define_insn "bset_qi"
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[(set (match_operand:QI 0 "memsym_operand" "+Si")
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[(set (match_operand:QI 0 "memsym_operand" "+Si")
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(ior:QI (subreg:QI (ashift:HI (const_int 1)
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(ior:QI (subreg:QI (ashift:HI (const_int 1)
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(subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
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(subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
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(match_operand:QI 2 "" "0")))]
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(match_operand:QI 2 "" "0")))]
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"TARGET_A16"
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"TARGET_A16"
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"bset\t%0[%1]"
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"bset\t%0[%1]"
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[(set_attr "flags" "n")]
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[(set_attr "flags" "n")]
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)
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)
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(define_insn "bset_hi"
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(define_insn "bset_hi"
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[(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
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[(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
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(const_int 1)
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(const_int 1)
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(zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
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(zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
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(const_int 1))]
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(const_int 1))]
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"TARGET_A16"
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"TARGET_A16"
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"bset\t%0[%1]"
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"bset\t%0[%1]"
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[(set_attr "flags" "n")]
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[(set_attr "flags" "n")]
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)
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)
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;;----------------------------------------------------------------------
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;;----------------------------------------------------------------------
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;; Now all the ways we can clear one bit, other than plain AND.
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;; Now all the ways we can clear one bit, other than plain AND.
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; This is odd because the shift patterns use QI counts, but we can't
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; This is odd because the shift patterns use QI counts, but we can't
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; easily put QI in $aN without causing problems elsewhere.
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; easily put QI in $aN without causing problems elsewhere.
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(define_insn "bclr_qi"
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(define_insn "bclr_qi"
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[(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
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[(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
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(const_int 1)
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(const_int 1)
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(zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
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(zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
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(const_int 0))]
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(const_int 0))]
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"TARGET_A16"
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"TARGET_A16"
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"bclr\t%0[%1]"
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"bclr\t%0[%1]"
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[(set_attr "flags" "n")]
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[(set_attr "flags" "n")]
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)
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)
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;;----------------------------------------------------------------------
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;;----------------------------------------------------------------------
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;; Now the generic patterns.
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;; Now the generic patterns.
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(define_insn "andqi3_16"
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(define_insn "andqi3_16"
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[(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
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[(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
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(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
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(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
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(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
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(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
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"TARGET_A16"
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"TARGET_A16"
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"@
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"@
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bclr\t%B2,%0
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bclr\t%B2,%0
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bclr\t%B2,%h0
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bclr\t%B2,%h0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0"
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and.b\t%x2,%0"
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[(set_attr "flags" "n,n,sz,sz,sz,sz")]
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[(set_attr "flags" "n,n,sz,sz,sz,sz")]
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)
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)
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(define_insn "andhi3_16"
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(define_insn "andhi3_16"
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[(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
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[(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
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(and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
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(and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
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(match_operand:HI 2 "mrai_operand" "Imb,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
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(match_operand:HI 2 "mrai_operand" "Imb,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
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"TARGET_A16"
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"TARGET_A16"
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"@
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"@
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bclr\t%B2,%0
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bclr\t%B2,%0
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bclr\t%B2-8,1+%0
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bclr\t%B2-8,1+%0
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bclr\t%B2,%0
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bclr\t%B2,%0
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and.w\t%X2,%0
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and.w\t%X2,%0
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and.w\t%X2,%0
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and.w\t%X2,%0
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and.w\t%X2,%0
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and.w\t%X2,%0
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and.w\t%X2,%0"
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and.w\t%X2,%0"
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[(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
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[(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
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)
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)
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(define_insn "andsi3"
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(define_insn "andsi3"
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
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(and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
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(and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
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(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
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""
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""
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"*
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"*
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0:
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case 0:
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output_asm_insn (\"and.w %X2,%h0\",operands);
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output_asm_insn (\"and.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"and.w %X2,%H0\";
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return \"and.w %X2,%H0\";
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case 1:
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case 1:
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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case 2:
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case 2:
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output_asm_insn (\"and.w %X2,%h0\",operands);
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output_asm_insn (\"and.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"and.w %X2,%H0\";
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return \"and.w %X2,%H0\";
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case 3:
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case 3:
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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case 4:
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case 4:
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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case 5:
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case 5:
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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return \"and.w %h2,%h0\;and.w %H2,%H0\";
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}"
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}"
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[(set_attr "flags" "x,x,x,x,x,x")]
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[(set_attr "flags" "x,x,x,x,x,x")]
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)
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)
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(define_insn "iorqi3_16"
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(define_insn "iorqi3_16"
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[(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
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[(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
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(ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
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(ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
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(match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
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(match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
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"TARGET_A16"
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"TARGET_A16"
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"@
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"@
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bset\t%B2,%0
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bset\t%B2,%0
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bset\t%B2,%h0
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bset\t%B2,%h0
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or.b\t%x2,%0
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or.b\t%x2,%0
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or.b\t%x2,%0
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or.b\t%x2,%0
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or.b\t%x2,%0
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or.b\t%x2,%0
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or.b\t%x2,%0"
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or.b\t%x2,%0"
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[(set_attr "flags" "n,n,sz,sz,sz,sz")]
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[(set_attr "flags" "n,n,sz,sz,sz,sz")]
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)
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)
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(define_insn "iorhi3_16"
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(define_insn "iorhi3_16"
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[(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
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[(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
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(ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
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(ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
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(match_operand:HI 2 "mrai_operand" "Imb,Imw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
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(match_operand:HI 2 "mrai_operand" "Imb,Imw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
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"TARGET_A16"
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"TARGET_A16"
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"@
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"@
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bset %B2,%0
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bset %B2,%0
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bset\t%B2-8,1+%0
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bset\t%B2-8,1+%0
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bset\t%B2,%0
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bset\t%B2,%0
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or.w\t%X2,%0
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or.w\t%X2,%0
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or.w\t%X2,%0
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or.w\t%X2,%0
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or.w\t%X2,%0
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or.w\t%X2,%0
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or.w\t%X2,%0"
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or.w\t%X2,%0"
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[(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
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[(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
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)
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)
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|
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|
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(define_insn "andqi3_24"
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(define_insn "andqi3_24"
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[(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
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[(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
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(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
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(and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
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(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
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(match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
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"TARGET_A24"
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"TARGET_A24"
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"@
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"@
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bclr\t%B2,%0
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bclr\t%B2,%0
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bclr\t%B2,%0
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bclr\t%B2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0
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and.b\t%x2,%0"
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and.b\t%x2,%0"
|
[(set_attr "flags" "n,n,sz,sz,sz,sz")]
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[(set_attr "flags" "n,n,sz,sz,sz,sz")]
|
)
|
)
|
|
|
(define_insn "andhi3_24"
|
(define_insn "andhi3_24"
|
[(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,??Rmm,RhiSd,??Rmm")
|
[(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,??Rmm,RhiSd,??Rmm")
|
(and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
|
(and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
|
(match_operand:HI 2 "mrai_operand" "Imb,Imw,Imb,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
|
(match_operand:HI 2 "mrai_operand" "Imb,Imw,Imb,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
|
"TARGET_A24"
|
"TARGET_A24"
|
"@
|
"@
|
bclr\t%B2,%0
|
bclr\t%B2,%0
|
bclr\t%B2-8,1+%0
|
bclr\t%B2-8,1+%0
|
bclr\t%B2,%h0
|
bclr\t%B2,%h0
|
bclr\t%B2-8,%H0
|
bclr\t%B2-8,%H0
|
and.w\t%X2,%0
|
and.w\t%X2,%0
|
and.w\t%X2,%0
|
and.w\t%X2,%0
|
and.w\t%X2,%0
|
and.w\t%X2,%0
|
and.w\t%X2,%0"
|
and.w\t%X2,%0"
|
[(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
|
[(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
|
)
|
)
|
|
|
|
|
|
|
(define_insn "iorqi3_24"
|
(define_insn "iorqi3_24"
|
[(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
|
[(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
|
(ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
|
(ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
|
(match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
|
(match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
|
"TARGET_A24"
|
"TARGET_A24"
|
"@
|
"@
|
bset\t%B2,%0
|
bset\t%B2,%0
|
or.b\t%x2,%0
|
or.b\t%x2,%0
|
or.b\t%x2,%0
|
or.b\t%x2,%0
|
or.b\t%x2,%0
|
or.b\t%x2,%0
|
or.b\t%x2,%0"
|
or.b\t%x2,%0"
|
[(set_attr "flags" "n,sz,sz,sz,sz")]
|
[(set_attr "flags" "n,sz,sz,sz,sz")]
|
)
|
)
|
|
|
(define_insn "iorhi3_24"
|
(define_insn "iorhi3_24"
|
[(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,RhiSd,??Rmm,??Rmm")
|
[(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,RhiSd,??Rmm,??Rmm")
|
(ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
|
(ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
|
(match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
|
(match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
|
"TARGET_A24"
|
"TARGET_A24"
|
"@
|
"@
|
bset\t%B2,%0
|
bset\t%B2,%0
|
bset\t%B2-8,1+%0
|
bset\t%B2-8,1+%0
|
bset\t%B2,%h0
|
bset\t%B2,%h0
|
bset\t%B2-8,%H0
|
bset\t%B2-8,%H0
|
or.w\t%X2,%0
|
or.w\t%X2,%0
|
or.w\t%X2,%0
|
or.w\t%X2,%0
|
or.w\t%X2,%0
|
or.w\t%X2,%0
|
or.w\t%X2,%0"
|
or.w\t%X2,%0"
|
[(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
|
[(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
|
)
|
)
|
|
|
|
|
; ----------------------------------------------------------------------
|
; ----------------------------------------------------------------------
|
|
|
(define_expand "andqi3"
|
(define_expand "andqi3"
|
[(set (match_operand:QI 0 "mra_operand" "")
|
[(set (match_operand:QI 0 "mra_operand" "")
|
(and:QI (match_operand:QI 1 "mra_operand" "")
|
(and:QI (match_operand:QI 1 "mra_operand" "")
|
(match_operand:QI 2 "mrai_operand" "")))]
|
(match_operand:QI 2 "mrai_operand" "")))]
|
""
|
""
|
"if (TARGET_A16)
|
"if (TARGET_A16)
|
emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));
|
else
|
else
|
emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));
|
DONE;"
|
DONE;"
|
)
|
)
|
|
|
(define_expand "andhi3"
|
(define_expand "andhi3"
|
[(set (match_operand:HI 0 "mra_operand" "")
|
[(set (match_operand:HI 0 "mra_operand" "")
|
(and:HI (match_operand:HI 1 "mra_operand" "")
|
(and:HI (match_operand:HI 1 "mra_operand" "")
|
(match_operand:HI 2 "mrai_operand" "")))]
|
(match_operand:HI 2 "mrai_operand" "")))]
|
""
|
""
|
"if (TARGET_A16)
|
"if (TARGET_A16)
|
emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));
|
else
|
else
|
emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));
|
DONE;"
|
DONE;"
|
)
|
)
|
|
|
(define_expand "iorqi3"
|
(define_expand "iorqi3"
|
[(set (match_operand:QI 0 "mra_operand" "")
|
[(set (match_operand:QI 0 "mra_operand" "")
|
(ior:QI (match_operand:QI 1 "mra_operand" "")
|
(ior:QI (match_operand:QI 1 "mra_operand" "")
|
(match_operand:QI 2 "mrai_operand" "")))]
|
(match_operand:QI 2 "mrai_operand" "")))]
|
""
|
""
|
"if (TARGET_A16)
|
"if (TARGET_A16)
|
emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));
|
else
|
else
|
emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));
|
DONE;"
|
DONE;"
|
)
|
)
|
|
|
(define_expand "iorhi3"
|
(define_expand "iorhi3"
|
[(set (match_operand:HI 0 "mra_operand" "")
|
[(set (match_operand:HI 0 "mra_operand" "")
|
(ior:HI (match_operand:HI 1 "mra_operand" "")
|
(ior:HI (match_operand:HI 1 "mra_operand" "")
|
(match_operand:HI 2 "mrai_operand" "")))]
|
(match_operand:HI 2 "mrai_operand" "")))]
|
""
|
""
|
"if (TARGET_A16)
|
"if (TARGET_A16)
|
emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));
|
else
|
else
|
emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));
|
DONE;"
|
DONE;"
|
)
|
)
|
|
|
(define_insn "iorsi3"
|
(define_insn "iorsi3"
|
[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
|
[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
|
(ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
|
(ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
|
(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
|
(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
|
""
|
""
|
"*
|
"*
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0:
|
case 0:
|
output_asm_insn (\"or.w %X2,%h0\",operands);
|
output_asm_insn (\"or.w %X2,%h0\",operands);
|
operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
|
operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
|
return \"or.w %X2,%H0\";
|
return \"or.w %X2,%H0\";
|
case 1:
|
case 1:
|
return \"or.w %h2,%h0\;or.w %H2,%H0\";
|
return \"or.w %h2,%h0\;or.w %H2,%H0\";
|
case 2:
|
case 2:
|
output_asm_insn (\"or.w %X2,%h0\",operands);
|
output_asm_insn (\"or.w %X2,%h0\",operands);
|
operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
|
operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
|
return \"or.w %X2,%H0\";
|
return \"or.w %X2,%H0\";
|
case 3:
|
case 3:
|
return \"or.w %h2,%h0\;or.w %H2,%H0\";
|
return \"or.w %h2,%h0\;or.w %H2,%H0\";
|
case 4:
|
case 4:
|
return \"or.w %h2,%h0\;or.w %H2,%H0\";
|
return \"or.w %h2,%h0\;or.w %H2,%H0\";
|
case 5:
|
case 5:
|
return \"or.w %h2,%h0\;or.w %H2,%H0\";
|
return \"or.w %h2,%h0\;or.w %H2,%H0\";
|
}"
|
}"
|
[(set_attr "flags" "x,x,x,x,x,x")]
|
[(set_attr "flags" "x,x,x,x,x,x")]
|
)
|
)
|
|
|
(define_insn "xorqi3"
|
(define_insn "xorqi3"
|
[(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
|
[(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
|
(xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
|
(xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
|
(match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
|
(match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
|
""
|
""
|
"xor.b\t%x2,%0"
|
"xor.b\t%x2,%0"
|
[(set_attr "flags" "sz,sz,sz,sz")]
|
[(set_attr "flags" "sz,sz,sz,sz")]
|
)
|
)
|
|
|
(define_insn "xorhi3"
|
(define_insn "xorhi3"
|
[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
|
[(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
|
(xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
|
(xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
|
(match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
|
(match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
|
""
|
""
|
"xor.w\t%X2,%0"
|
"xor.w\t%X2,%0"
|
[(set_attr "flags" "sz,sz,sz,sz")]
|
[(set_attr "flags" "sz,sz,sz,sz")]
|
)
|
)
|
|
|
(define_insn "xorsi3"
|
(define_insn "xorsi3"
|
[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
|
[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
|
(xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
|
(xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
|
(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
|
(match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
|
""
|
""
|
"*
|
"*
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0:
|
case 0:
|
output_asm_insn (\"xor.w %X2,%h0\",operands);
|
output_asm_insn (\"xor.w %X2,%h0\",operands);
|
operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
|
operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
|
return \"xor.w %X2,%H0\";
|
return \"xor.w %X2,%H0\";
|
case 1:
|
case 1:
|
return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
|
return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
|
case 2:
|
case 2:
|
output_asm_insn (\"xor.w %X2,%h0\",operands);
|
output_asm_insn (\"xor.w %X2,%h0\",operands);
|
operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
|
operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
|
return \"xor.w %X2,%H0\";
|
return \"xor.w %X2,%H0\";
|
case 3:
|
case 3:
|
return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
|
return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
|
case 4:
|
case 4:
|
return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
|
return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
|
case 5:
|
case 5:
|
return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
|
return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
|
}"
|
}"
|
[(set_attr "flags" "x,x,x,x,x,x")]
|
[(set_attr "flags" "x,x,x,x,x,x")]
|
)
|
)
|
|
|
(define_insn "one_cmplqi2"
|
(define_insn "one_cmplqi2"
|
[(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
|
[(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
|
(not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
|
(not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
|
""
|
""
|
"not.b\t%0"
|
"not.b\t%0"
|
[(set_attr "flags" "sz,sz")]
|
[(set_attr "flags" "sz,sz")]
|
)
|
)
|
|
|
(define_insn "one_cmplhi2"
|
(define_insn "one_cmplhi2"
|
[(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
|
[(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
|
(not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
|
(not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
|
""
|
""
|
"not.w\t%0"
|
"not.w\t%0"
|
[(set_attr "flags" "sz,sz")]
|
[(set_attr "flags" "sz,sz")]
|
)
|
)
|
|
|
; Optimizations using bit opcodes
|
; Optimizations using bit opcodes
|
|
|
; We need this because combine only looks at three insns at a time,
|
; We need this because combine only looks at three insns at a time,
|
; and the bclr_qi pattern uses four - mov, shift, not, and. GCC
|
; and the bclr_qi pattern uses four - mov, shift, not, and. GCC
|
; should never expand this pattern, because it only shifts a constant
|
; should never expand this pattern, because it only shifts a constant
|
; by a constant, so gcc should do that itself.
|
; by a constant, so gcc should do that itself.
|
(define_insn "shift1_qi"
|
(define_insn "shift1_qi"
|
[(set (match_operand:QI 0 "mra_operand" "=Rqi")
|
[(set (match_operand:QI 0 "mra_operand" "=Rqi")
|
(ashift:QI (const_int 1)
|
(ashift:QI (const_int 1)
|
(match_operand 1 "const_int_operand" "In4")))]
|
(match_operand 1 "const_int_operand" "In4")))]
|
""
|
""
|
"mov.b\t#1,%0\n\tshl.b\t%1,%0"
|
"mov.b\t#1,%0\n\tshl.b\t%1,%0"
|
)
|
)
|
(define_insn "shift1_hi"
|
(define_insn "shift1_hi"
|
[(set (match_operand:HI 0 "mra_operand" "=Rhi")
|
[(set (match_operand:HI 0 "mra_operand" "=Rhi")
|
(ashift:HI (const_int 1)
|
(ashift:HI (const_int 1)
|
(match_operand 1 "const_int_operand" "In4")))]
|
(match_operand 1 "const_int_operand" "In4")))]
|
""
|
""
|
"mov.w\t#1,%0\n\tshl.w\t%1,%0"
|
"mov.w\t#1,%0\n\tshl.w\t%1,%0"
|
)
|
)
|
|
|
; Generic insert-bit expander, needed so that we can use the bit
|
; Generic insert-bit expander, needed so that we can use the bit
|
; opcodes for volatile bitfields.
|
; opcodes for volatile bitfields.
|
|
|
(define_expand "insv"
|
(define_expand "insv"
|
[(set (zero_extract:HI (match_operand:HI 0 "mra_operand" "")
|
[(set (zero_extract:HI (match_operand:HI 0 "mra_operand" "")
|
(match_operand 1 "const_int_operand" "")
|
(match_operand 1 "const_int_operand" "")
|
(match_operand 2 "const_int_operand" ""))
|
(match_operand 2 "const_int_operand" ""))
|
(match_operand:HI 3 "const_int_operand" ""))]
|
(match_operand:HI 3 "const_int_operand" ""))]
|
""
|
""
|
"if (m32c_expand_insv (operands))
|
"if (m32c_expand_insv (operands))
|
FAIL;
|
FAIL;
|
DONE;"
|
DONE;"
|
)
|
)
|
|
|
