OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [m32c/] [m32c.opt] - Diff between revs 38 and 154

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 38 Rev 154
; Target Options for R8C/M16C/M32C
; Target Options for R8C/M16C/M32C
; Copyright (C) 2005 2007
; Copyright (C) 2005 2007
; Free Software Foundation, Inc.
; Free Software Foundation, Inc.
; Contributed by Red Hat.
; Contributed by Red Hat.
;
;
; This file is part of GCC.
; This file is part of GCC.
;
;
; GCC is free software; you can redistribute it and/or modify it
; GCC is free software; you can redistribute it and/or modify it
; under the terms of the GNU General Public License as published
; under the terms of the GNU General Public License as published
; by the Free Software Foundation; either version 3, or (at your
; by the Free Software Foundation; either version 3, or (at your
; option) any later version.
; option) any later version.
;
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
; License for more details.
; License for more details.
;
;
; You should have received a copy of the GNU General Public License
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; along with GCC; see the file COPYING3.  If not see
; .
; .
msim
msim
Target
Target
-msim   Use simulator runtime
-msim   Use simulator runtime
mcpu=r8c
mcpu=r8c
Target RejectNegative Var(target_cpu,'r') Init('r')
Target RejectNegative Var(target_cpu,'r') Init('r')
-mcpu=r8c       Compile code for R8C variants
-mcpu=r8c       Compile code for R8C variants
mcpu=m16c
mcpu=m16c
Target RejectNegative Var(target_cpu,'6')
Target RejectNegative Var(target_cpu,'6')
-mcpu=m16c      Compile code for M16C variants
-mcpu=m16c      Compile code for M16C variants
mcpu=m32cm
mcpu=m32cm
Target RejectNegative Var(target_cpu,'m')
Target RejectNegative Var(target_cpu,'m')
-mcpu=m32cm     Compile code for M32CM variants
-mcpu=m32cm     Compile code for M32CM variants
mcpu=m32c
mcpu=m32c
Target RejectNegative Var(target_cpu,'3')
Target RejectNegative Var(target_cpu,'3')
-mcpu=m32c      Compile code for M32C variants
-mcpu=m32c      Compile code for M32C variants
memregs=
memregs=
Target RejectNegative Joined Var(target_memregs_string)
Target RejectNegative Joined Var(target_memregs_string)
-memregs=       Number of memreg bytes (default: 16, range: 0..16)
-memregs=       Number of memreg bytes (default: 16, range: 0..16)
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.