;; DFA-based pipeline descriptions for MIPS Technologies 24K core.
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;; DFA-based pipeline descriptions for MIPS Technologies 24K core.
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;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com)
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;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com)
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;; and David Ung (davidu@mips.com)
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;; and David Ung (davidu@mips.com)
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;;
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;;
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;; The 24K is a single-issue processor with a half-clocked fpu.
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;; The 24K is a single-issue processor with a half-clocked fpu.
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;; The 24Kx is 24k with 1:1 clocked fpu.
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;; The 24Kx is 24k with 1:1 clocked fpu.
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;;
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;;
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;; References:
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;; References:
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;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
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;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
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;;
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;;
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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|
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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(define_automaton "r24k_cpu, r24k_mdu, r24k_fpu")
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(define_automaton "r24k_cpu, r24k_mdu, r24k_fpu")
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;; Integer execution unit.
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;; Integer execution unit.
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(define_cpu_unit "r24k_iss" "r24k_cpu")
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(define_cpu_unit "r24k_iss" "r24k_cpu")
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(define_cpu_unit "r24k_ixu_arith" "r24k_cpu")
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(define_cpu_unit "r24k_ixu_arith" "r24k_cpu")
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(define_cpu_unit "r24k_mul3a" "r24k_mdu")
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(define_cpu_unit "r24k_mul3a" "r24k_mdu")
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(define_cpu_unit "r24k_mul3b" "r24k_mdu")
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(define_cpu_unit "r24k_mul3b" "r24k_mdu")
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(define_cpu_unit "r24k_mul3c" "r24k_mdu")
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(define_cpu_unit "r24k_mul3c" "r24k_mdu")
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;; --------------------------------------------------------------
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;; --------------------------------------------------------------
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;; Producers
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;; Producers
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;; --------------------------------------------------------------
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;; --------------------------------------------------------------
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;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
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;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
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(define_insn_reservation "r24k_int_load" 2
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(define_insn_reservation "r24k_int_load" 2
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "load"))
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(eq_attr "type" "load"))
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"r24k_iss+r24k_ixu_arith")
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"r24k_iss+r24k_ixu_arith")
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;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
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;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
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;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll,
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;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll,
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;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
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;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
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;; xor, xori
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;; xor, xori
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;; (movn/movz is not matched, we'll need to split condmov to
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;; (movn/movz is not matched, we'll need to split condmov to
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;; differentiate between integer/float moves)
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;; differentiate between integer/float moves)
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(define_insn_reservation "r24k_int_arith" 1
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(define_insn_reservation "r24k_int_arith" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "arith,const,nop,shift,slt"))
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(eq_attr "type" "arith,const,nop,shift,slt"))
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"r24k_iss+r24k_ixu_arith")
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"r24k_iss+r24k_ixu_arith")
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;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx
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;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx
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;; 3a. jr/jalr consumer
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;; 3a. jr/jalr consumer
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(define_insn_reservation "r24k_int_jump" 1
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(define_insn_reservation "r24k_int_jump" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "call,jump"))
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(eq_attr "type" "call,jump"))
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"r24k_iss+r24k_ixu_arith")
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"r24k_iss+r24k_ixu_arith")
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;; 3b. branch consumer
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;; 3b. branch consumer
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(define_insn_reservation "r24k_int_branch" 1
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(define_insn_reservation "r24k_int_branch" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "branch"))
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(eq_attr "type" "branch"))
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"r24k_iss+r24k_ixu_arith")
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"r24k_iss+r24k_ixu_arith")
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;; 4. MDU: fully pipelined multiplier
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;; 4. MDU: fully pipelined multiplier
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;; mult - delivers result to hi/lo in 1 cycle (pipelined)
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;; mult - delivers result to hi/lo in 1 cycle (pipelined)
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(define_insn_reservation "r24k_int_mult" 1
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(define_insn_reservation "r24k_int_mult" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "imul"))
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(eq_attr "type" "imul"))
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined)
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;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined)
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(define_insn_reservation "r24k_int_madd" 1
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(define_insn_reservation "r24k_int_madd" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "imadd"))
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(eq_attr "type" "imadd"))
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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;; mul - delivers result to gpr in 5 cycles
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;; mul - delivers result to gpr in 5 cycles
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(define_insn_reservation "r24k_int_mul3" 5
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(define_insn_reservation "r24k_int_mul3" 5
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "imul3"))
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(eq_attr "type" "imul3"))
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
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;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
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;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
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(define_insn_reservation "r24k_int_mfhilo" 5
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(define_insn_reservation "r24k_int_mfhilo" 5
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "mfhilo"))
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(eq_attr "type" "mfhilo"))
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
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;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
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(define_insn_reservation "r24k_int_mthilo" 1
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(define_insn_reservation "r24k_int_mthilo" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "mthilo"))
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(eq_attr "type" "mthilo"))
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
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;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and
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;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and
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;; 8bit, but is tricky to identify.
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;; 8bit, but is tricky to identify.
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(define_insn_reservation "r24k_int_div" 36
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(define_insn_reservation "r24k_int_div" 36
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "idiv"))
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(eq_attr "type" "idiv"))
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"r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36")
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"r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36")
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;; 5. Cop: cfc1, di, ei, mfc0, mtc0
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;; 5. Cop: cfc1, di, ei, mfc0, mtc0
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;; (Disabled until we add proper cop0 support)
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;; (Disabled until we add proper cop0 support)
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;;(define_insn_reservation "r24k_int_cop" 3
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;;(define_insn_reservation "r24k_int_cop" 3
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;; (and (eq_attr "cpu" "24k,24kx")
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;; (and (eq_attr "cpu" "24k,24kx")
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;; (eq_attr "type" "cop0"))
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;; (eq_attr "type" "cop0"))
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;; "r24k_iss+r24k_ixu_arith")
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;; "r24k_iss+r24k_ixu_arith")
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;; 6. Store
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;; 6. Store
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(define_insn_reservation "r24k_int_store" 1
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(define_insn_reservation "r24k_int_store" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "type" "store")
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(and (eq_attr "type" "store")
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(eq_attr "mode" "!unknown")))
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(eq_attr "mode" "!unknown")))
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"r24k_iss+r24k_ixu_arith")
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"r24k_iss+r24k_ixu_arith")
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;; 6.1 Special case - matches the cprestore pattern which don't set the mode
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;; 6.1 Special case - matches the cprestore pattern which don't set the mode
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;; attrib. This avoids being set as r24k_int_store and have it checked
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;; attrib. This avoids being set as r24k_int_store and have it checked
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;; against store_data_bypass_p, which would then fail because cprestore
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;; against store_data_bypass_p, which would then fail because cprestore
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;; does not have a normal SET pattern.
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;; does not have a normal SET pattern.
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(define_insn_reservation "r24k_unknown_store" 1
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(define_insn_reservation "r24k_unknown_store" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "type" "store")
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(and (eq_attr "type" "store")
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(eq_attr "mode" "unknown")))
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(eq_attr "mode" "unknown")))
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"r24k_iss+r24k_ixu_arith")
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"r24k_iss+r24k_ixu_arith")
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;; 7. Multiple instructions
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;; 7. Multiple instructions
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(define_insn_reservation "r24k_int_multi" 1
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(define_insn_reservation "r24k_int_multi" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "multi"))
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(eq_attr "type" "multi"))
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"r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)")
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"r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)")
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;; 8. Unknowns - Currently these include blockage, consttable and alignment
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;; 8. Unknowns - Currently these include blockage, consttable and alignment
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;; rtls. They do not really affect scheduling latency, (blockage affects
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;; rtls. They do not really affect scheduling latency, (blockage affects
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;; scheduling via log links, but not used here).
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;; scheduling via log links, but not used here).
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(define_insn_reservation "r24k_int_unknown" 0
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(define_insn_reservation "r24k_int_unknown" 0
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "unknown"))
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(eq_attr "type" "unknown"))
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"r24k_iss")
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"r24k_iss")
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;; 9. Prefetch
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;; 9. Prefetch
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(define_insn_reservation "r24k_int_prefetch" 1
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(define_insn_reservation "r24k_int_prefetch" 1
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(and (eq_attr "cpu" "24k,24kx")
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(and (eq_attr "cpu" "24k,24kx")
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(eq_attr "type" "prefetch,prefetchx"))
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(eq_attr "type" "prefetch,prefetchx"))
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"r24k_iss+r24k_ixu_arith")
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"r24k_iss+r24k_ixu_arith")
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;; --------------------------------------------------------------
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;; --------------------------------------------------------------
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;; Bypass to Consumer
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;; Bypass to Consumer
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;; --------------------------------------------------------------
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;; --------------------------------------------------------------
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;; load->next use : 2 cycles (Default)
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;; load->next use : 2 cycles (Default)
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;; load->load base: 3 cycles
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;; load->load base: 3 cycles
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;; load->store base: 3 cycles
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;; load->store base: 3 cycles
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;; load->prefetch: 3 cycles
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;; load->prefetch: 3 cycles
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(define_bypass 3 "r24k_int_load" "r24k_int_load")
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(define_bypass 3 "r24k_int_load" "r24k_int_load")
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(define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
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(define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
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;; arith->next use : 1 cycles (Default)
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;; arith->next use : 1 cycles (Default)
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;; arith->load base: 2 cycles
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;; arith->load base: 2 cycles
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;; arith->store base: 2 cycles
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;; arith->store base: 2 cycles
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;; arith->prefetch: 2 cycles
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;; arith->prefetch: 2 cycles
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(define_bypass 2 "r24k_int_arith" "r24k_int_load")
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(define_bypass 2 "r24k_int_arith" "r24k_int_load")
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(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
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(define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
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;; mul3->next use : 5 cycles (default)
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;; mul3->next use : 5 cycles (default)
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;; mul3->l/s base : 6 cycles
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;; mul3->l/s base : 6 cycles
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;; mul3->prefetch : 6 cycles
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;; mul3->prefetch : 6 cycles
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(define_bypass 6 "r24k_int_mul3" "r24k_int_load")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_load")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
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|
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;; mfhilo->next use : 5 cycles (default)
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;; mfhilo->next use : 5 cycles (default)
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;; mfhilo->l/s base : 6 cycles
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;; mfhilo->l/s base : 6 cycles
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;; mfhilo->prefetch : 6 cycles
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;; mfhilo->prefetch : 6 cycles
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;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
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;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
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(define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
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(define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
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|
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;; cop->next use : 3 cycles (Default)
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;; cop->next use : 3 cycles (Default)
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;; cop->l/s base : 4 cycles
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;; cop->l/s base : 4 cycles
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;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
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;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
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;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p")
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;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p")
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|
|
;; multi->next use : 1 cycles (Default)
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;; multi->next use : 1 cycles (Default)
|
;; multi->l/s base : 2 cycles
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;; multi->l/s base : 2 cycles
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;; multi->prefetch : 2 cycles
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;; multi->prefetch : 2 cycles
|
(define_bypass 2 "r24k_int_multi" "r24k_int_load")
|
(define_bypass 2 "r24k_int_multi" "r24k_int_load")
|
(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
|
(define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
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|
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|
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;; --------------------------------------------------------------
|
;; --------------------------------------------------------------
|
;; Floating Point Instructions
|
;; Floating Point Instructions
|
;; --------------------------------------------------------------
|
;; --------------------------------------------------------------
|
|
|
(define_cpu_unit "r24k_fpu_arith" "r24k_fpu")
|
(define_cpu_unit "r24k_fpu_arith" "r24k_fpu")
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|
|
;; The 24k is a single issue cpu, and the fpu runs at half clock speed,
|
;; The 24k is a single issue cpu, and the fpu runs at half clock speed,
|
;; so each fpu instruction ties up the shared instruction scheduler for
|
;; so each fpu instruction ties up the shared instruction scheduler for
|
;; 1 cycle, and the fpu scheduler for 2 cycles.
|
;; 1 cycle, and the fpu scheduler for 2 cycles.
|
;;
|
;;
|
;; These timings are therefore twice the values in the 24K manual,
|
;; These timings are therefore twice the values in the 24K manual,
|
;; which are quoted in fpu clocks.
|
;; which are quoted in fpu clocks.
|
;;
|
;;
|
;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
|
;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
|
;; the unscaled timings
|
;; the unscaled timings
|
|
|
(define_reservation "r24k_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)")
|
(define_reservation "r24k_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)")
|
|
|
;; fadd, fabs, fneg
|
;; fadd, fabs, fneg
|
(define_insn_reservation "r24k_fadd" 8
|
(define_insn_reservation "r24k_fadd" 8
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(eq_attr "type" "fadd,fabs,fneg"))
|
(eq_attr "type" "fadd,fabs,fneg"))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
;; fmove, fcmove
|
;; fmove, fcmove
|
(define_insn_reservation "r24k_fmove" 8
|
(define_insn_reservation "r24k_fmove" 8
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(eq_attr "type" "fmove,condmove"))
|
(eq_attr "type" "fmove,condmove"))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
;; fload
|
;; fload
|
(define_insn_reservation "r24k_fload" 6
|
(define_insn_reservation "r24k_fload" 6
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(eq_attr "type" "fpload,fpidxload"))
|
(eq_attr "type" "fpload,fpidxload"))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
;; fstore
|
;; fstore
|
(define_insn_reservation "r24k_fstore" 2
|
(define_insn_reservation "r24k_fstore" 2
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(eq_attr "type" "fpstore"))
|
(eq_attr "type" "fpstore"))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
;; fmul, fmadd
|
;; fmul, fmadd
|
(define_insn_reservation "r24k_fmul_sf" 8
|
(define_insn_reservation "r24k_fmul_sf" 8
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "type" "fmul,fmadd")
|
(and (eq_attr "type" "fmul,fmadd")
|
(eq_attr "mode" "SF")))
|
(eq_attr "mode" "SF")))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
(define_insn_reservation "r24k_fmul_df" 10
|
(define_insn_reservation "r24k_fmul_df" 10
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "type" "fmul,fmadd")
|
(and (eq_attr "type" "fmul,fmadd")
|
(eq_attr "mode" "DF")))
|
(eq_attr "mode" "DF")))
|
"r24k_fpu_iss,(r24k_fpu_arith*2)")
|
"r24k_fpu_iss,(r24k_fpu_arith*2)")
|
|
|
|
|
;; fdiv, fsqrt, frsqrt
|
;; fdiv, fsqrt, frsqrt
|
(define_insn_reservation "r24k_fdiv_sf" 34
|
(define_insn_reservation "r24k_fdiv_sf" 34
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
|
(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
|
(eq_attr "mode" "SF")))
|
(eq_attr "mode" "SF")))
|
"r24k_fpu_iss,(r24k_fpu_arith*26)")
|
"r24k_fpu_iss,(r24k_fpu_arith*26)")
|
|
|
(define_insn_reservation "r24k_fdiv_df" 64
|
(define_insn_reservation "r24k_fdiv_df" 64
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "type" "fdiv,fsqrt")
|
(and (eq_attr "type" "fdiv,fsqrt")
|
(eq_attr "mode" "DF")))
|
(eq_attr "mode" "DF")))
|
"r24k_fpu_iss,(r24k_fpu_arith*56)")
|
"r24k_fpu_iss,(r24k_fpu_arith*56)")
|
|
|
;; frsqrt
|
;; frsqrt
|
(define_insn_reservation "r24k_frsqrt_df" 70
|
(define_insn_reservation "r24k_frsqrt_df" 70
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "type" "frsqrt")
|
(and (eq_attr "type" "frsqrt")
|
(eq_attr "mode" "DF")))
|
(eq_attr "mode" "DF")))
|
"r24k_fpu_iss,(r24k_fpu_arith*60)")
|
"r24k_fpu_iss,(r24k_fpu_arith*60)")
|
|
|
;; fcmp
|
;; fcmp
|
(define_insn_reservation "r24k_fcmp" 4
|
(define_insn_reservation "r24k_fcmp" 4
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(eq_attr "type" "fcmp"))
|
(eq_attr "type" "fcmp"))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
|
;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
|
(define_bypass 2 "r24k_fcmp" "r24k_fmove")
|
(define_bypass 2 "r24k_fcmp" "r24k_fmove")
|
|
|
;; fcvt (cvt.d.s, cvt.[sd].[wl])
|
;; fcvt (cvt.d.s, cvt.[sd].[wl])
|
(define_insn_reservation "r24k_fcvt_i2f_s2d" 8
|
(define_insn_reservation "r24k_fcvt_i2f_s2d" 8
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "type" "fcvt")
|
(and (eq_attr "type" "fcvt")
|
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
|
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
;; fcvt (cvt.s.d)
|
;; fcvt (cvt.s.d)
|
(define_insn_reservation "r24k_fcvt_s2d" 12
|
(define_insn_reservation "r24k_fcvt_s2d" 12
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "type" "fcvt")
|
(and (eq_attr "type" "fcvt")
|
(eq_attr "cnv_mode" "D2S")))
|
(eq_attr "cnv_mode" "D2S")))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
;; fcvt (cvt.[wl].[sd], etc)
|
;; fcvt (cvt.[wl].[sd], etc)
|
(define_insn_reservation "r24k_fcvt_f2i" 10
|
(define_insn_reservation "r24k_fcvt_f2i" 10
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "type" "fcvt")
|
(and (eq_attr "type" "fcvt")
|
(eq_attr "cnv_mode" "S2I,D2I")))
|
(eq_attr "cnv_mode" "S2I,D2I")))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
;; fxfer (mfc1, mfhc1, mtc1, mthc1)
|
;; fxfer (mfc1, mfhc1, mtc1, mthc1)
|
(define_insn_reservation "r24k_fxfer" 4
|
(define_insn_reservation "r24k_fxfer" 4
|
(and (eq_attr "cpu" "24k")
|
(and (eq_attr "cpu" "24k")
|
(eq_attr "type" "xfer"))
|
(eq_attr "type" "xfer"))
|
"r24k_fpu_iss")
|
"r24k_fpu_iss")
|
|
|
;; --------------------------------------------------------------
|
;; --------------------------------------------------------------
|
;; Bypass to Consumer
|
;; Bypass to Consumer
|
;; --------------------------------------------------------------
|
;; --------------------------------------------------------------
|
;; r24k_fcvt_f2i->l/s base : 11 cycles
|
;; r24k_fcvt_f2i->l/s base : 11 cycles
|
;; r24k_fcvt_f2i->prefetch : 11 cycles
|
;; r24k_fcvt_f2i->prefetch : 11 cycles
|
(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_load")
|
(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_load")
|
(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_prefetch")
|
(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_prefetch")
|
|
|
;; r24k_fxfer->l/s base : 5 cycles
|
;; r24k_fxfer->l/s base : 5 cycles
|
;; r24k_fxfer->prefetch : 5 cycles
|
;; r24k_fxfer->prefetch : 5 cycles
|
(define_bypass 5 "r24k_fxfer" "r24k_int_load")
|
(define_bypass 5 "r24k_fxfer" "r24k_int_load")
|
(define_bypass 5 "r24k_fxfer" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 5 "r24k_fxfer" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 5 "r24k_fxfer" "r24k_int_prefetch")
|
(define_bypass 5 "r24k_fxfer" "r24k_int_prefetch")
|
|
|
;; --------------------------------------------------------------
|
;; --------------------------------------------------------------
|
;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
|
;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
|
;; the unscaled timings
|
;; the unscaled timings
|
;; --------------------------------------------------------------
|
;; --------------------------------------------------------------
|
|
|
(define_reservation "r24kx_fpu_iss" "r24k_iss+r24k_fpu_arith")
|
(define_reservation "r24kx_fpu_iss" "r24k_iss+r24k_fpu_arith")
|
|
|
;; fadd, fabs, fneg
|
;; fadd, fabs, fneg
|
(define_insn_reservation "r24kx_fadd" 4
|
(define_insn_reservation "r24kx_fadd" 4
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(eq_attr "type" "fadd,fabs,fneg"))
|
(eq_attr "type" "fadd,fabs,fneg"))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
;; fmove, fcmove
|
;; fmove, fcmove
|
(define_insn_reservation "r24kx_fmove" 4
|
(define_insn_reservation "r24kx_fmove" 4
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(eq_attr "type" "fmove,condmove"))
|
(eq_attr "type" "fmove,condmove"))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
;; fload
|
;; fload
|
(define_insn_reservation "r24kx_fload" 3
|
(define_insn_reservation "r24kx_fload" 3
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(eq_attr "type" "fpload,fpidxload"))
|
(eq_attr "type" "fpload,fpidxload"))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
;; fstore
|
;; fstore
|
(define_insn_reservation "r24kx_fstore" 1
|
(define_insn_reservation "r24kx_fstore" 1
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(eq_attr "type" "fpstore"))
|
(eq_attr "type" "fpstore"))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
;; fmul, fmadd
|
;; fmul, fmadd
|
(define_insn_reservation "r24kx_fmul_sf" 4
|
(define_insn_reservation "r24kx_fmul_sf" 4
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "type" "fmul,fmadd")
|
(and (eq_attr "type" "fmul,fmadd")
|
(eq_attr "mode" "SF")))
|
(eq_attr "mode" "SF")))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
(define_insn_reservation "r24kx_fmul_df" 5
|
(define_insn_reservation "r24kx_fmul_df" 5
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "type" "fmul,fmadd")
|
(and (eq_attr "type" "fmul,fmadd")
|
(eq_attr "mode" "DF")))
|
(eq_attr "mode" "DF")))
|
"r24kx_fpu_iss,r24k_fpu_arith")
|
"r24kx_fpu_iss,r24k_fpu_arith")
|
|
|
|
|
;; fdiv, fsqrt, frsqrt
|
;; fdiv, fsqrt, frsqrt
|
(define_insn_reservation "r24kx_fdiv_sf" 17
|
(define_insn_reservation "r24kx_fdiv_sf" 17
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
|
(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
|
(eq_attr "mode" "SF")))
|
(eq_attr "mode" "SF")))
|
"r24kx_fpu_iss,(r24k_fpu_arith*13)")
|
"r24kx_fpu_iss,(r24k_fpu_arith*13)")
|
|
|
(define_insn_reservation "r24kx_fdiv_df" 32
|
(define_insn_reservation "r24kx_fdiv_df" 32
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "type" "fdiv,fsqrt")
|
(and (eq_attr "type" "fdiv,fsqrt")
|
(eq_attr "mode" "DF")))
|
(eq_attr "mode" "DF")))
|
"r24kx_fpu_iss,(r24k_fpu_arith*28)")
|
"r24kx_fpu_iss,(r24k_fpu_arith*28)")
|
|
|
;; frsqrt
|
;; frsqrt
|
(define_insn_reservation "r24kx_frsqrt_df" 35
|
(define_insn_reservation "r24kx_frsqrt_df" 35
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "type" "frsqrt")
|
(and (eq_attr "type" "frsqrt")
|
(eq_attr "mode" "DF")))
|
(eq_attr "mode" "DF")))
|
"r24kx_fpu_iss,(r24k_fpu_arith*30)")
|
"r24kx_fpu_iss,(r24k_fpu_arith*30)")
|
|
|
;; fcmp
|
;; fcmp
|
(define_insn_reservation "r24kx_fcmp" 2
|
(define_insn_reservation "r24kx_fcmp" 2
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(eq_attr "type" "fcmp"))
|
(eq_attr "type" "fcmp"))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
|
;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
|
(define_bypass 1 "r24kx_fcmp" "r24kx_fmove")
|
(define_bypass 1 "r24kx_fcmp" "r24kx_fmove")
|
|
|
;; fcvt (cvt.d.s, cvt.[sd].[wl])
|
;; fcvt (cvt.d.s, cvt.[sd].[wl])
|
(define_insn_reservation "r24kx_fcvt_i2f_s2d" 4
|
(define_insn_reservation "r24kx_fcvt_i2f_s2d" 4
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "type" "fcvt")
|
(and (eq_attr "type" "fcvt")
|
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
|
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
;; fcvt (cvt.s.d)
|
;; fcvt (cvt.s.d)
|
(define_insn_reservation "r24kx_fcvt_s2d" 6
|
(define_insn_reservation "r24kx_fcvt_s2d" 6
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "type" "fcvt")
|
(and (eq_attr "type" "fcvt")
|
(eq_attr "cnv_mode" "D2S")))
|
(eq_attr "cnv_mode" "D2S")))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
;; fcvt (cvt.[wl].[sd], etc)
|
;; fcvt (cvt.[wl].[sd], etc)
|
(define_insn_reservation "r24kx_fcvt_f2i" 5
|
(define_insn_reservation "r24kx_fcvt_f2i" 5
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "type" "fcvt")
|
(and (eq_attr "type" "fcvt")
|
(eq_attr "cnv_mode" "S2I,D2I")))
|
(eq_attr "cnv_mode" "S2I,D2I")))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
;; fxfer (mfc1, mfhc1, mtc1, mthc1)
|
;; fxfer (mfc1, mfhc1, mtc1, mthc1)
|
(define_insn_reservation "r24kx_fxfer" 2
|
(define_insn_reservation "r24kx_fxfer" 2
|
(and (eq_attr "cpu" "24kx")
|
(and (eq_attr "cpu" "24kx")
|
(eq_attr "type" "xfer"))
|
(eq_attr "type" "xfer"))
|
"r24kx_fpu_iss")
|
"r24kx_fpu_iss")
|
|
|
;; --------------------------------------------------------------
|
;; --------------------------------------------------------------
|
;; Bypass to Consumer
|
;; Bypass to Consumer
|
;; --------------------------------------------------------------
|
;; --------------------------------------------------------------
|
;; r24kx_fcvt_f2i->l/s base : 6 cycles
|
;; r24kx_fcvt_f2i->l/s base : 6 cycles
|
;; r24kx_fcvt_f2i->prefetch : 6 cycles
|
;; r24kx_fcvt_f2i->prefetch : 6 cycles
|
(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_load")
|
(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_load")
|
(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_prefetch")
|
(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_prefetch")
|
|
|
;; r24kx_fxfer->l/s base : 3 cycles
|
;; r24kx_fxfer->l/s base : 3 cycles
|
;; r24kx_fxfer->prefetch : 3 cycles
|
;; r24kx_fxfer->prefetch : 3 cycles
|
(define_bypass 3 "r24kx_fxfer" "r24k_int_load")
|
(define_bypass 3 "r24kx_fxfer" "r24k_int_load")
|
(define_bypass 3 "r24kx_fxfer" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 3 "r24kx_fxfer" "r24k_int_store" "!store_data_bypass_p")
|
(define_bypass 3 "r24kx_fxfer" "r24k_int_prefetch")
|
(define_bypass 3 "r24kx_fxfer" "r24k_int_prefetch")
|
|
|
|
|
