;; DFA-based pipeline descriptions for MIPS32 5K processor family
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;; DFA-based pipeline descriptions for MIPS32 5K processor family
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;; Contributed by David Ung (davidu@mips.com)
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;; Contributed by David Ung (davidu@mips.com)
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;; and Nigel Stephens (nigel@mips.com)
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;; and Nigel Stephens (nigel@mips.com)
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;;
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;;
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;; References:
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;; References:
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;; "MIPS64 5K Processor Core Family Software User's Manual,
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;; "MIPS64 5K Processor Core Family Software User's Manual,
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;; Doc no: MD00012, Rev 2.09, Jan 28, 2005."
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;; Doc no: MD00012, Rev 2.09, Jan 28, 2005."
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;;
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;;
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;; 5Kc - Single issue with no floating point unit.
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;; 5Kc - Single issue with no floating point unit.
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;; 5kf - Separate floating point pipe which can dual-issue with the
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;; 5kf - Separate floating point pipe which can dual-issue with the
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;; integer pipe.
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;; integer pipe.
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;;
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;;
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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|
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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|
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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(define_automaton "r5k_cpu, r5k_mdu, r5k_fpu")
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(define_automaton "r5k_cpu, r5k_mdu, r5k_fpu")
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;; Integer execution unit.
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;; Integer execution unit.
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(define_cpu_unit "r5k_ixu_arith" "r5k_cpu")
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(define_cpu_unit "r5k_ixu_arith" "r5k_cpu")
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(define_cpu_unit "r5k_ixu_mpydiv" "r5k_mdu")
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(define_cpu_unit "r5k_ixu_mpydiv" "r5k_mdu")
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(define_cpu_unit "r5kf_fpu_arith" "r5k_fpu")
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(define_cpu_unit "r5kf_fpu_arith" "r5k_fpu")
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|
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(define_insn_reservation "r5k_int_load" 2
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(define_insn_reservation "r5k_int_load" 2
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(eq_attr "type" "load"))
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(eq_attr "type" "load"))
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"r5k_ixu_arith")
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"r5k_ixu_arith")
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|
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(define_insn_reservation "r5k_int_prefetch" 1
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(define_insn_reservation "r5k_int_prefetch" 1
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(eq_attr "type" "prefetch,prefetchx"))
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(eq_attr "type" "prefetch,prefetchx"))
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"r5k_ixu_arith")
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"r5k_ixu_arith")
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|
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(define_insn_reservation "r5k_int_store" 1
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(define_insn_reservation "r5k_int_store" 1
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(eq_attr "type" "store"))
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(eq_attr "type" "store"))
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"r5k_ixu_arith")
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"r5k_ixu_arith")
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;; Divides
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;; Divides
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(define_insn_reservation "r5k_int_divsi" 34
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(define_insn_reservation "r5k_int_divsi" 34
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "type" "idiv")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "!DI")))
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(eq_attr "mode" "!DI")))
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"r5k_ixu_arith+(r5k_ixu_mpydiv*34)")
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"r5k_ixu_arith+(r5k_ixu_mpydiv*34)")
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(define_insn_reservation "r5k_int_divdi" 66
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(define_insn_reservation "r5k_int_divdi" 66
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "type" "idiv")
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(and (eq_attr "type" "idiv")
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(eq_attr "mode" "DI")))
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(eq_attr "mode" "DI")))
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"r5k_ixu_arith+(r5k_ixu_mpydiv*66)")
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"r5k_ixu_arith+(r5k_ixu_mpydiv*66)")
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;; 32x32 multiply
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;; 32x32 multiply
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;; 32x16 is faster, but there's no way to detect this
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;; 32x16 is faster, but there's no way to detect this
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(define_insn_reservation "r5k_int_mult" 2
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(define_insn_reservation "r5k_int_mult" 2
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "type" "imul,imadd")
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(and (eq_attr "type" "imul,imadd")
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(eq_attr "mode" "SI")))
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(eq_attr "mode" "SI")))
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"r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
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"r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
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;; 64x64 multiply
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;; 64x64 multiply
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(define_insn_reservation "r5k_int_mult_64" 9
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(define_insn_reservation "r5k_int_mult_64" 9
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "type" "imul,imadd")
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(and (eq_attr "type" "imul,imadd")
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(eq_attr "mode" "DI")))
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(eq_attr "mode" "DI")))
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"r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
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"r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
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;; 3 operand MUL 32x32
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;; 3 operand MUL 32x32
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(define_insn_reservation "r5k_int_mul" 4
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(define_insn_reservation "r5k_int_mul" 4
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "type" "imul3")
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(and (eq_attr "type" "imul3")
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(eq_attr "mode" "SI")))
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(eq_attr "mode" "SI")))
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"r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
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"r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
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;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
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;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
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(define_insn_reservation "r5k_int_mthilo" 1
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(define_insn_reservation "r5k_int_mthilo" 1
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(eq_attr "type" "mthilo"))
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(eq_attr "type" "mthilo"))
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"r5k_ixu_arith+r5k_ixu_mpydiv")
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"r5k_ixu_arith+r5k_ixu_mpydiv")
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;; Move from HI/LO -> integer operation has a 2 cycle latency.
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;; Move from HI/LO -> integer operation has a 2 cycle latency.
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(define_insn_reservation "r5k_int_mfhilo" 2
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(define_insn_reservation "r5k_int_mfhilo" 2
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(eq_attr "type" "mfhilo"))
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(eq_attr "type" "mfhilo"))
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"r5k_ixu_arith+r5k_ixu_mpydiv")
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"r5k_ixu_arith+r5k_ixu_mpydiv")
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;; All other integer insns.
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;; All other integer insns.
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(define_insn_reservation "r5k_int_alu" 1
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(define_insn_reservation "r5k_int_alu" 1
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(eq_attr "type" "arith,condmove,shift,const,nop,slt"))
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(eq_attr "type" "arith,condmove,shift,const,nop,slt"))
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"r5k_ixu_arith")
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"r5k_ixu_arith")
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|
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(define_insn_reservation "r5k_int_branch" 1
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(define_insn_reservation "r5k_int_branch" 1
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(eq_attr "type" "branch"))
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(eq_attr "type" "branch"))
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"r5k_ixu_arith")
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"r5k_ixu_arith")
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;; JR/JALR always cause one pipeline bubble because of interlock.
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;; JR/JALR always cause one pipeline bubble because of interlock.
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(define_insn_reservation "r5k_int_jump" 2
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(define_insn_reservation "r5k_int_jump" 2
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(eq_attr "type" "jump,call"))
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(eq_attr "type" "jump,call"))
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"r5k_ixu_arith")
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"r5k_ixu_arith")
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;; Any -> JR/JALR (without dependency) : 1 clock issue delay
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;; Any -> JR/JALR (without dependency) : 1 clock issue delay
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;; Any -> JR/JALR (with dependency) : 2 clock issue delay
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;; Any -> JR/JALR (with dependency) : 2 clock issue delay
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;; load -> JR/JALR (with dependency) : 3 clock issue delay
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;; load -> JR/JALR (with dependency) : 3 clock issue delay
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;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay
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;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay
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;; mul -> JR/JALR (with dependency) : 3 clock issue delay
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;; mul -> JR/JALR (with dependency) : 3 clock issue delay
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(define_bypass 2 "r5k_int_alu" "r5k_int_jump")
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(define_bypass 2 "r5k_int_alu" "r5k_int_jump")
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(define_bypass 3 "r5k_int_load" "r5k_int_jump")
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(define_bypass 3 "r5k_int_load" "r5k_int_jump")
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(define_bypass 3 "r5k_int_mfhilo" "r5k_int_jump")
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(define_bypass 3 "r5k_int_mfhilo" "r5k_int_jump")
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(define_bypass 3 "r5k_int_mul" "r5k_int_jump")
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(define_bypass 3 "r5k_int_mul" "r5k_int_jump")
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;; Unknown or multi - single issue
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;; Unknown or multi - single issue
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(define_insn_reservation "r5k_int_unknown" 1
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(define_insn_reservation "r5k_int_unknown" 1
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(and (eq_attr "cpu" "5kc,5kf")
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(and (eq_attr "cpu" "5kc,5kf")
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(eq_attr "type" "unknown,multi"))
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(eq_attr "type" "unknown,multi"))
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"r5k_ixu_arith+r5k_ixu_mpydiv")
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"r5k_ixu_arith+r5k_ixu_mpydiv")
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;; Floating Point Instructions
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;; Floating Point Instructions
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;; The 5Kf is a partial dual-issue cpu which can dual issue an integer
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;; The 5Kf is a partial dual-issue cpu which can dual issue an integer
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;; and floating-point instruction in the same cycle.
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;; and floating-point instruction in the same cycle.
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;; fadd, fabs, fneg
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;; fadd, fabs, fneg
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(define_insn_reservation "r5kf_fadd" 4
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(define_insn_reservation "r5kf_fadd" 4
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
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(eq_attr "type" "fadd,fabs,fneg"))
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(eq_attr "type" "fadd,fabs,fneg"))
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"r5kf_fpu_arith")
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"r5kf_fpu_arith")
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;; fmove, fcmove
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;; fmove, fcmove
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(define_insn_reservation "r5kf_fmove" 4
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(define_insn_reservation "r5kf_fmove" 4
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
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(eq_attr "type" "fmove"))
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(eq_attr "type" "fmove"))
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"r5kf_fpu_arith")
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"r5kf_fpu_arith")
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;; fload
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;; fload
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(define_insn_reservation "r5kf_fload" 3
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(define_insn_reservation "r5kf_fload" 3
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
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(eq_attr "type" "fpload,fpidxload"))
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(eq_attr "type" "fpload,fpidxload"))
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"r5kf_fpu_arith")
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"r5kf_fpu_arith")
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;; fstore
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;; fstore
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(define_insn_reservation "r5kf_fstore" 1
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(define_insn_reservation "r5kf_fstore" 1
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
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(eq_attr "type" "fpstore"))
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(eq_attr "type" "fpstore"))
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"r5kf_fpu_arith")
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"r5kf_fpu_arith")
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;; fmul, fmadd
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;; fmul, fmadd
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(define_insn_reservation "r5kf_fmul_sf" 4
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(define_insn_reservation "r5kf_fmul_sf" 4
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "type" "fmul,fmadd")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "SF")))
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(eq_attr "mode" "SF")))
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"r5kf_fpu_arith")
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"r5kf_fpu_arith")
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(define_insn_reservation "r5kf_fmul_df" 5
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(define_insn_reservation "r5kf_fmul_df" 5
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "type" "fmul,fmadd")
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(and (eq_attr "type" "fmul,fmadd")
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(eq_attr "mode" "DF")))
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(eq_attr "mode" "DF")))
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"r5kf_fpu_arith*2")
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"r5kf_fpu_arith*2")
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|
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;; fdiv, fsqrt, frsqrt
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;; fdiv, fsqrt, frsqrt
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(define_insn_reservation "r5kf_fdiv_sf" 17
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(define_insn_reservation "r5kf_fdiv_sf" 17
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
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(and (eq_attr "type" "fdiv,fsqrt,frsqrt")
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(eq_attr "mode" "SF")))
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(eq_attr "mode" "SF")))
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"r5kf_fpu_arith*14")
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"r5kf_fpu_arith*14")
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|
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(define_insn_reservation "r5kf_fdiv_df" 32
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(define_insn_reservation "r5kf_fdiv_df" 32
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "type" "fdiv,fsqrt")
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(and (eq_attr "type" "fdiv,fsqrt")
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(eq_attr "mode" "DF")))
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(eq_attr "mode" "DF")))
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"r5kf_fpu_arith*29")
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"r5kf_fpu_arith*29")
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|
|
;; frsqrt
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;; frsqrt
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(define_insn_reservation "r5kf_frsqrt_df" 35
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(define_insn_reservation "r5kf_frsqrt_df" 35
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "type" "frsqrt")
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(and (eq_attr "type" "frsqrt")
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(eq_attr "mode" "DF")))
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(eq_attr "mode" "DF")))
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"r5kf_fpu_arith*31")
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"r5kf_fpu_arith*31")
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|
|
;; fcmp
|
;; fcmp
|
(define_insn_reservation "r5kf_fcmp" 2
|
(define_insn_reservation "r5kf_fcmp" 2
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(and (eq_attr "cpu" "5kf")
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(and (eq_attr "cpu" "5kf")
|
(eq_attr "type" "fcmp"))
|
(eq_attr "type" "fcmp"))
|
"r5kf_fpu_arith")
|
"r5kf_fpu_arith")
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|
|
;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on condition)
|
;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on condition)
|
(define_bypass 1 "r5kf_fcmp" "r5kf_fmove")
|
(define_bypass 1 "r5kf_fcmp" "r5kf_fmove")
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|
|
;; fcvt (cvt.d.s, cvt.[sd].[wl]
|
;; fcvt (cvt.d.s, cvt.[sd].[wl]
|
(define_insn_reservation "r5kf_fcvt_d2s" 4
|
(define_insn_reservation "r5kf_fcvt_d2s" 4
|
(and (eq_attr "cpu" "5kf")
|
(and (eq_attr "cpu" "5kf")
|
(and (eq_attr "type" "fcvt")
|
(and (eq_attr "type" "fcvt")
|
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
|
(eq_attr "cnv_mode" "I2S,I2D,S2D")))
|
"r5kf_fpu_arith")
|
"r5kf_fpu_arith")
|
|
|
;; fcvt (cvt.s.d)
|
;; fcvt (cvt.s.d)
|
(define_insn_reservation "r5kf_fcvt_s2d" 6
|
(define_insn_reservation "r5kf_fcvt_s2d" 6
|
(and (eq_attr "cpu" "5kc")
|
(and (eq_attr "cpu" "5kc")
|
(and (eq_attr "type" "fcvt")
|
(and (eq_attr "type" "fcvt")
|
(eq_attr "cnv_mode" "D2S")))
|
(eq_attr "cnv_mode" "D2S")))
|
"r5kf_fpu_arith")
|
"r5kf_fpu_arith")
|
|
|
;; fcvt (cvt.[wl].[sd], etc)
|
;; fcvt (cvt.[wl].[sd], etc)
|
(define_insn_reservation "r5kf_fcvt_f2i" 5
|
(define_insn_reservation "r5kf_fcvt_f2i" 5
|
(and (eq_attr "cpu" "5kf")
|
(and (eq_attr "cpu" "5kf")
|
(and (eq_attr "type" "fcvt")
|
(and (eq_attr "type" "fcvt")
|
(eq_attr "cnv_mode" "S2I,D2I")))
|
(eq_attr "cnv_mode" "S2I,D2I")))
|
"r5kf_fpu_arith")
|
"r5kf_fpu_arith")
|
|
|
;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue
|
;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue
|
(define_insn_reservation "r5kf_fxfer" 2
|
(define_insn_reservation "r5kf_fxfer" 2
|
(and (eq_attr "cpu" "5kf")
|
(and (eq_attr "cpu" "5kf")
|
(eq_attr "type" "xfer"))
|
(eq_attr "type" "xfer"))
|
"r5k_ixu_arith+r5kf_fpu_arith")
|
"r5k_ixu_arith+r5kf_fpu_arith")
|
|
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