(define_constants
|
(define_constants
|
[(CCDSP_PO_REGNUM 182)
|
[(CCDSP_PO_REGNUM 182)
|
(CCDSP_SC_REGNUM 183)
|
(CCDSP_SC_REGNUM 183)
|
(CCDSP_CA_REGNUM 184)
|
(CCDSP_CA_REGNUM 184)
|
(CCDSP_OU_REGNUM 185)
|
(CCDSP_OU_REGNUM 185)
|
(CCDSP_CC_REGNUM 186)
|
(CCDSP_CC_REGNUM 186)
|
(CCDSP_EF_REGNUM 187)])
|
(CCDSP_EF_REGNUM 187)])
|
|
|
;; This mode macro allows si, v2hi, v4qi for all possible modes in DSP ASE.
|
;; This mode macro allows si, v2hi, v4qi for all possible modes in DSP ASE.
|
(define_mode_macro DSP [(SI "TARGET_DSP")
|
(define_mode_macro DSP [(SI "TARGET_DSP")
|
(V2HI "TARGET_DSP")
|
(V2HI "TARGET_DSP")
|
(V4QI "TARGET_DSP")])
|
(V4QI "TARGET_DSP")])
|
|
|
;; This mode macro allows v2hi, v4qi for vector/SIMD data.
|
;; This mode macro allows v2hi, v4qi for vector/SIMD data.
|
(define_mode_macro DSPV [(V2HI "TARGET_DSP")
|
(define_mode_macro DSPV [(V2HI "TARGET_DSP")
|
(V4QI "TARGET_DSP")])
|
(V4QI "TARGET_DSP")])
|
|
|
;; This mode macro allows si, v2hi for Q31 and V2Q15 fixed-point data.
|
;; This mode macro allows si, v2hi for Q31 and V2Q15 fixed-point data.
|
(define_mode_macro DSPQ [(SI "TARGET_DSP")
|
(define_mode_macro DSPQ [(SI "TARGET_DSP")
|
(V2HI "TARGET_DSP")])
|
(V2HI "TARGET_DSP")])
|
|
|
;; DSP instructions use q for fixed-point data, and u for integer in the infix.
|
;; DSP instructions use q for fixed-point data, and u for integer in the infix.
|
(define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
|
(define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
|
|
|
;; DSP instructions use nothing for fixed-point data, and u for integer in
|
;; DSP instructions use nothing for fixed-point data, and u for integer in
|
;; the infix.
|
;; the infix.
|
(define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")])
|
(define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")])
|
|
|
;; DSP instructions use w, ph, qb in the postfix.
|
;; DSP instructions use w, ph, qb in the postfix.
|
(define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")])
|
(define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")])
|
|
|
;; DSP shift masks for SI, V2HI, V4QI.
|
;; DSP shift masks for SI, V2HI, V4QI.
|
(define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")])
|
(define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")])
|
|
|
;; MIPS DSP ASE Revision 0.98 3/24/2005
|
;; MIPS DSP ASE Revision 0.98 3/24/2005
|
;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic
|
;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic
|
;; ADDQ*
|
;; ADDQ*
|
(define_insn "add3"
|
(define_insn "add3"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DSPV 0 "register_operand" "=d")
|
[(set (match_operand:DSPV 0 "register_operand" "=d")
|
(plus:DSPV (match_operand:DSPV 1 "register_operand" "d")
|
(plus:DSPV (match_operand:DSPV 1 "register_operand" "d")
|
(match_operand:DSPV 2 "register_operand" "d")))
|
(match_operand:DSPV 2 "register_operand" "d")))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])]
|
""
|
""
|
"add.\t%0,%1,%2"
|
"add.\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_add_s_"
|
(define_insn "mips_add_s_"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DSP 0 "register_operand" "=d")
|
[(set (match_operand:DSP 0 "register_operand" "=d")
|
(unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
|
(unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
|
(match_operand:DSP 2 "register_operand" "d")]
|
(match_operand:DSP 2 "register_operand" "d")]
|
UNSPEC_ADDQ_S))
|
UNSPEC_ADDQ_S))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
|
""
|
""
|
"add_s.\t%0,%1,%2"
|
"add_s.\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; SUBQ*
|
;; SUBQ*
|
(define_insn "sub3"
|
(define_insn "sub3"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DSPV 0 "register_operand" "=d")
|
[(set (match_operand:DSPV 0 "register_operand" "=d")
|
(minus:DSPV (match_operand:DSPV 1 "register_operand" "d")
|
(minus:DSPV (match_operand:DSPV 1 "register_operand" "d")
|
(match_operand:DSPV 2 "register_operand" "d")))
|
(match_operand:DSPV 2 "register_operand" "d")))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"sub.\t%0,%1,%2"
|
"sub.\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_sub_s_"
|
(define_insn "mips_sub_s_"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DSP 0 "register_operand" "=d")
|
[(set (match_operand:DSP 0 "register_operand" "=d")
|
(unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
|
(unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
|
(match_operand:DSP 2 "register_operand" "d")]
|
(match_operand:DSP 2 "register_operand" "d")]
|
UNSPEC_SUBQ_S))
|
UNSPEC_SUBQ_S))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"sub_s.\t%0,%1,%2"
|
"sub_s.\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; ADDSC
|
;; ADDSC
|
(define_insn "mips_addsc"
|
(define_insn "mips_addsc"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")]
|
(match_operand:SI 2 "register_operand" "d")]
|
UNSPEC_ADDSC))
|
UNSPEC_ADDSC))
|
(set (reg:CCDSP CCDSP_CA_REGNUM)
|
(set (reg:CCDSP CCDSP_CA_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"addsc\t%0,%1,%2"
|
"addsc\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; ADDWC
|
;; ADDWC
|
(define_insn "mips_addwc"
|
(define_insn "mips_addwc"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")
|
(reg:CCDSP CCDSP_CA_REGNUM)]
|
(reg:CCDSP CCDSP_CA_REGNUM)]
|
UNSPEC_ADDWC))
|
UNSPEC_ADDWC))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"addwc\t%0,%1,%2"
|
"addwc\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; MODSUB
|
;; MODSUB
|
(define_insn "mips_modsub"
|
(define_insn "mips_modsub"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")]
|
(match_operand:SI 2 "register_operand" "d")]
|
UNSPEC_MODSUB))]
|
UNSPEC_MODSUB))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"modsub\t%0,%1,%2"
|
"modsub\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; RADDU*
|
;; RADDU*
|
(define_insn "mips_raddu_w_qb"
|
(define_insn "mips_raddu_w_qb"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")]
|
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")]
|
UNSPEC_RADDU_W_QB))]
|
UNSPEC_RADDU_W_QB))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"raddu.w.qb\t%0,%1"
|
"raddu.w.qb\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; ABSQ*
|
;; ABSQ*
|
(define_insn "mips_absq_s_"
|
(define_insn "mips_absq_s_"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DSPQ 0 "register_operand" "=d")
|
[(set (match_operand:DSPQ 0 "register_operand" "=d")
|
(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")]
|
(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")]
|
UNSPEC_ABSQ_S))
|
UNSPEC_ABSQ_S))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
|
(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"absq_s.\t%0,%1"
|
"absq_s.\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; PRECRQ*
|
;; PRECRQ*
|
(define_insn "mips_precrq_qb_ph"
|
(define_insn "mips_precrq_qb_ph"
|
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
(unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
|
(unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")]
|
(match_operand:V2HI 2 "register_operand" "d")]
|
UNSPEC_PRECRQ_QB_PH))]
|
UNSPEC_PRECRQ_QB_PH))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"precrq.qb.ph\t%0,%1,%2"
|
"precrq.qb.ph\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_precrq_ph_w"
|
(define_insn "mips_precrq_ph_w"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
|
(unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")]
|
(match_operand:SI 2 "register_operand" "d")]
|
UNSPEC_PRECRQ_PH_W))]
|
UNSPEC_PRECRQ_PH_W))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"precrq.ph.w\t%0,%1,%2"
|
"precrq.ph.w\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_precrq_rs_ph_w"
|
(define_insn "mips_precrq_rs_ph_w"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
|
(unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")]
|
(match_operand:SI 2 "register_operand" "d")]
|
UNSPEC_PRECRQ_RS_PH_W))
|
UNSPEC_PRECRQ_RS_PH_W))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)]
|
UNSPEC_PRECRQ_RS_PH_W))])]
|
UNSPEC_PRECRQ_RS_PH_W))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"precrq_rs.ph.w\t%0,%1,%2"
|
"precrq_rs.ph.w\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; PRECRQU*
|
;; PRECRQU*
|
(define_insn "mips_precrqu_s_qb_ph"
|
(define_insn "mips_precrqu_s_qb_ph"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
(unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
|
(unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")]
|
(match_operand:V2HI 2 "register_operand" "d")]
|
UNSPEC_PRECRQU_S_QB_PH))
|
UNSPEC_PRECRQU_S_QB_PH))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)]
|
UNSPEC_PRECRQU_S_QB_PH))])]
|
UNSPEC_PRECRQU_S_QB_PH))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"precrqu_s.qb.ph\t%0,%1,%2"
|
"precrqu_s.qb.ph\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; PRECEQ*
|
;; PRECEQ*
|
(define_insn "mips_preceq_w_phl"
|
(define_insn "mips_preceq_w_phl"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
|
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
|
UNSPEC_PRECEQ_W_PHL))]
|
UNSPEC_PRECEQ_W_PHL))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"preceq.w.phl\t%0,%1"
|
"preceq.w.phl\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_preceq_w_phr"
|
(define_insn "mips_preceq_w_phr"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
|
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
|
UNSPEC_PRECEQ_W_PHR))]
|
UNSPEC_PRECEQ_W_PHR))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"preceq.w.phr\t%0,%1"
|
"preceq.w.phr\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; PRECEQU*
|
;; PRECEQU*
|
(define_insn "mips_precequ_ph_qbl"
|
(define_insn "mips_precequ_ph_qbl"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
UNSPEC_PRECEQU_PH_QBL))]
|
UNSPEC_PRECEQU_PH_QBL))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"precequ.ph.qbl\t%0,%1"
|
"precequ.ph.qbl\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_precequ_ph_qbr"
|
(define_insn "mips_precequ_ph_qbr"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
UNSPEC_PRECEQU_PH_QBR))]
|
UNSPEC_PRECEQU_PH_QBR))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"precequ.ph.qbr\t%0,%1"
|
"precequ.ph.qbr\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_precequ_ph_qbla"
|
(define_insn "mips_precequ_ph_qbla"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
UNSPEC_PRECEQU_PH_QBLA))]
|
UNSPEC_PRECEQU_PH_QBLA))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"precequ.ph.qbla\t%0,%1"
|
"precequ.ph.qbla\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_precequ_ph_qbra"
|
(define_insn "mips_precequ_ph_qbra"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
UNSPEC_PRECEQU_PH_QBRA))]
|
UNSPEC_PRECEQU_PH_QBRA))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"precequ.ph.qbra\t%0,%1"
|
"precequ.ph.qbra\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; PRECEU*
|
;; PRECEU*
|
(define_insn "mips_preceu_ph_qbl"
|
(define_insn "mips_preceu_ph_qbl"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
UNSPEC_PRECEU_PH_QBL))]
|
UNSPEC_PRECEU_PH_QBL))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"preceu.ph.qbl\t%0,%1"
|
"preceu.ph.qbl\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_preceu_ph_qbr"
|
(define_insn "mips_preceu_ph_qbr"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
UNSPEC_PRECEU_PH_QBR))]
|
UNSPEC_PRECEU_PH_QBR))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"preceu.ph.qbr\t%0,%1"
|
"preceu.ph.qbr\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_preceu_ph_qbla"
|
(define_insn "mips_preceu_ph_qbla"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
UNSPEC_PRECEU_PH_QBLA))]
|
UNSPEC_PRECEU_PH_QBLA))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"preceu.ph.qbla\t%0,%1"
|
"preceu.ph.qbla\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_preceu_ph_qbra"
|
(define_insn "mips_preceu_ph_qbra"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
|
UNSPEC_PRECEU_PH_QBRA))]
|
UNSPEC_PRECEU_PH_QBRA))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"preceu.ph.qbra\t%0,%1"
|
"preceu.ph.qbra\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; Table 2-2. MIPS DSP ASE Instructions: Shift
|
;; Table 2-2. MIPS DSP ASE Instructions: Shift
|
;; SHLL*
|
;; SHLL*
|
(define_insn "mips_shll_"
|
(define_insn "mips_shll_"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DSPV 0 "register_operand" "=d,d")
|
[(set (match_operand:DSPV 0 "register_operand" "=d,d")
|
(unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d")
|
(unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_SHLL))
|
UNSPEC_SHLL))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2])
|
if (INTVAL (operands[2])
|
& ~(unsigned HOST_WIDE_INT) )
|
& ~(unsigned HOST_WIDE_INT) )
|
operands[2] = GEN_INT (INTVAL (operands[2]) & );
|
operands[2] = GEN_INT (INTVAL (operands[2]) & );
|
return "shll.\t%0,%1,%2";
|
return "shll.\t%0,%1,%2";
|
}
|
}
|
return "shllv.\t%0,%1,%2";
|
return "shllv.\t%0,%1,%2";
|
}
|
}
|
[(set_attr "type" "shift")
|
[(set_attr "type" "shift")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_shll_s_"
|
(define_insn "mips_shll_s_"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DSPQ 0 "register_operand" "=d,d")
|
[(set (match_operand:DSPQ 0 "register_operand" "=d,d")
|
(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
|
(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_SHLL_S))
|
UNSPEC_SHLL_S))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2])
|
if (INTVAL (operands[2])
|
& ~(unsigned HOST_WIDE_INT) )
|
& ~(unsigned HOST_WIDE_INT) )
|
operands[2] = GEN_INT (INTVAL (operands[2]) & );
|
operands[2] = GEN_INT (INTVAL (operands[2]) & );
|
return "shll_s.\t%0,%1,%2";
|
return "shll_s.\t%0,%1,%2";
|
}
|
}
|
return "shllv_s.\t%0,%1,%2";
|
return "shllv_s.\t%0,%1,%2";
|
}
|
}
|
[(set_attr "type" "shift")
|
[(set_attr "type" "shift")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; SHRL*
|
;; SHRL*
|
(define_insn "mips_shrl_qb"
|
(define_insn "mips_shrl_qb"
|
[(set (match_operand:V4QI 0 "register_operand" "=d,d")
|
[(set (match_operand:V4QI 0 "register_operand" "=d,d")
|
(unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d")
|
(unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_SHRL_QB))]
|
UNSPEC_SHRL_QB))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7)
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7)
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7);
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7);
|
return "shrl.qb\t%0,%1,%2";
|
return "shrl.qb\t%0,%1,%2";
|
}
|
}
|
return "shrlv.qb\t%0,%1,%2";
|
return "shrlv.qb\t%0,%1,%2";
|
}
|
}
|
[(set_attr "type" "shift")
|
[(set_attr "type" "shift")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; SHRA*
|
;; SHRA*
|
(define_insn "mips_shra_ph"
|
(define_insn "mips_shra_ph"
|
[(set (match_operand:V2HI 0 "register_operand" "=d,d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d,d")
|
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d")
|
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_SHRA_PH))]
|
UNSPEC_SHRA_PH))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf)
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf)
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf);
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf);
|
return "shra.ph\t%0,%1,%2";
|
return "shra.ph\t%0,%1,%2";
|
}
|
}
|
return "shrav.ph\t%0,%1,%2";
|
return "shrav.ph\t%0,%1,%2";
|
}
|
}
|
[(set_attr "type" "shift")
|
[(set_attr "type" "shift")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_shra_r_"
|
(define_insn "mips_shra_r_"
|
[(set (match_operand:DSPQ 0 "register_operand" "=d,d")
|
[(set (match_operand:DSPQ 0 "register_operand" "=d,d")
|
(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
|
(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_SHRA_R))]
|
UNSPEC_SHRA_R))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2])
|
if (INTVAL (operands[2])
|
& ~(unsigned HOST_WIDE_INT) )
|
& ~(unsigned HOST_WIDE_INT) )
|
operands[2] = GEN_INT (INTVAL (operands[2]) & );
|
operands[2] = GEN_INT (INTVAL (operands[2]) & );
|
return "shra_r.\t%0,%1,%2";
|
return "shra_r.\t%0,%1,%2";
|
}
|
}
|
return "shrav_r.\t%0,%1,%2";
|
return "shrav_r.\t%0,%1,%2";
|
}
|
}
|
[(set_attr "type" "shift")
|
[(set_attr "type" "shift")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; Table 2-3. MIPS DSP ASE Instructions: Multiply
|
;; Table 2-3. MIPS DSP ASE Instructions: Multiply
|
;; MULEU*
|
;; MULEU*
|
(define_insn "mips_muleu_s_ph_qbl"
|
(define_insn "mips_muleu_s_ph_qbl"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")]
|
(match_operand:V2HI 2 "register_operand" "d")]
|
UNSPEC_MULEU_S_PH_QBL))
|
UNSPEC_MULEU_S_PH_QBL))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
|
(clobber (match_scratch:DI 3 "=x"))])]
|
(clobber (match_scratch:DI 3 "=x"))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"muleu_s.ph.qbl\t%0,%1,%2"
|
"muleu_s.ph.qbl\t%0,%1,%2"
|
[(set_attr "type" "imul3")
|
[(set_attr "type" "imul3")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_muleu_s_ph_qbr"
|
(define_insn "mips_muleu_s_ph_qbr"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
|
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")]
|
(match_operand:V2HI 2 "register_operand" "d")]
|
UNSPEC_MULEU_S_PH_QBR))
|
UNSPEC_MULEU_S_PH_QBR))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
|
(clobber (match_scratch:DI 3 "=x"))])]
|
(clobber (match_scratch:DI 3 "=x"))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"muleu_s.ph.qbr\t%0,%1,%2"
|
"muleu_s.ph.qbr\t%0,%1,%2"
|
[(set_attr "type" "imul3")
|
[(set_attr "type" "imul3")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; MULQ*
|
;; MULQ*
|
(define_insn "mips_mulq_rs_ph"
|
(define_insn "mips_mulq_rs_ph"
|
[(parallel
|
[(parallel
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
|
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")]
|
(match_operand:V2HI 2 "register_operand" "d")]
|
UNSPEC_MULQ_RS_PH))
|
UNSPEC_MULQ_RS_PH))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
|
(clobber (match_scratch:DI 3 "=x"))])]
|
(clobber (match_scratch:DI 3 "=x"))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"mulq_rs.ph\t%0,%1,%2"
|
"mulq_rs.ph\t%0,%1,%2"
|
[(set_attr "type" "imul3")
|
[(set_attr "type" "imul3")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; MULEQ*
|
;; MULEQ*
|
(define_insn "mips_muleq_s_w_phl"
|
(define_insn "mips_muleq_s_w_phl"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
|
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")]
|
(match_operand:V2HI 2 "register_operand" "d")]
|
UNSPEC_MULEQ_S_W_PHL))
|
UNSPEC_MULEQ_S_W_PHL))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
|
(clobber (match_scratch:DI 3 "=x"))])]
|
(clobber (match_scratch:DI 3 "=x"))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"muleq_s.w.phl\t%0,%1,%2"
|
"muleq_s.w.phl\t%0,%1,%2"
|
[(set_attr "type" "imul3")
|
[(set_attr "type" "imul3")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_muleq_s_w_phr"
|
(define_insn "mips_muleq_s_w_phr"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
|
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")]
|
(match_operand:V2HI 2 "register_operand" "d")]
|
UNSPEC_MULEQ_S_W_PHR))
|
UNSPEC_MULEQ_S_W_PHR))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
|
(clobber (match_scratch:DI 3 "=x"))])]
|
(clobber (match_scratch:DI 3 "=x"))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"muleq_s.w.phr\t%0,%1,%2"
|
"muleq_s.w.phr\t%0,%1,%2"
|
[(set_attr "type" "imul3")
|
[(set_attr "type" "imul3")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; DPAU*
|
;; DPAU*
|
(define_insn "mips_dpau_h_qbl"
|
(define_insn "mips_dpau_h_qbl"
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V4QI 2 "register_operand" "d")
|
(match_operand:V4QI 2 "register_operand" "d")
|
(match_operand:V4QI 3 "register_operand" "d")]
|
(match_operand:V4QI 3 "register_operand" "d")]
|
UNSPEC_DPAU_H_QBL))]
|
UNSPEC_DPAU_H_QBL))]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"dpau.h.qbl\t%q0,%2,%3"
|
"dpau.h.qbl\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_dpau_h_qbr"
|
(define_insn "mips_dpau_h_qbr"
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V4QI 2 "register_operand" "d")
|
(match_operand:V4QI 2 "register_operand" "d")
|
(match_operand:V4QI 3 "register_operand" "d")]
|
(match_operand:V4QI 3 "register_operand" "d")]
|
UNSPEC_DPAU_H_QBR))]
|
UNSPEC_DPAU_H_QBR))]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"dpau.h.qbr\t%q0,%2,%3"
|
"dpau.h.qbr\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; DPSU*
|
;; DPSU*
|
(define_insn "mips_dpsu_h_qbl"
|
(define_insn "mips_dpsu_h_qbl"
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V4QI 2 "register_operand" "d")
|
(match_operand:V4QI 2 "register_operand" "d")
|
(match_operand:V4QI 3 "register_operand" "d")]
|
(match_operand:V4QI 3 "register_operand" "d")]
|
UNSPEC_DPSU_H_QBL))]
|
UNSPEC_DPSU_H_QBL))]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"dpsu.h.qbl\t%q0,%2,%3"
|
"dpsu.h.qbl\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_dpsu_h_qbr"
|
(define_insn "mips_dpsu_h_qbr"
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V4QI 2 "register_operand" "d")
|
(match_operand:V4QI 2 "register_operand" "d")
|
(match_operand:V4QI 3 "register_operand" "d")]
|
(match_operand:V4QI 3 "register_operand" "d")]
|
UNSPEC_DPSU_H_QBR))]
|
UNSPEC_DPSU_H_QBR))]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"dpsu.h.qbr\t%q0,%2,%3"
|
"dpsu.h.qbr\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; DPAQ*
|
;; DPAQ*
|
(define_insn "mips_dpaq_s_w_ph"
|
(define_insn "mips_dpaq_s_w_ph"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 3 "register_operand" "d")]
|
(match_operand:V2HI 3 "register_operand" "d")]
|
UNSPEC_DPAQ_S_W_PH))
|
UNSPEC_DPAQ_S_W_PH))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
UNSPEC_DPAQ_S_W_PH))])]
|
UNSPEC_DPAQ_S_W_PH))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"dpaq_s.w.ph\t%q0,%2,%3"
|
"dpaq_s.w.ph\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; DPSQ*
|
;; DPSQ*
|
(define_insn "mips_dpsq_s_w_ph"
|
(define_insn "mips_dpsq_s_w_ph"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 3 "register_operand" "d")]
|
(match_operand:V2HI 3 "register_operand" "d")]
|
UNSPEC_DPSQ_S_W_PH))
|
UNSPEC_DPSQ_S_W_PH))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
UNSPEC_DPSQ_S_W_PH))])]
|
UNSPEC_DPSQ_S_W_PH))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"dpsq_s.w.ph\t%q0,%2,%3"
|
"dpsq_s.w.ph\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; MULSAQ*
|
;; MULSAQ*
|
(define_insn "mips_mulsaq_s_w_ph"
|
(define_insn "mips_mulsaq_s_w_ph"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 3 "register_operand" "d")]
|
(match_operand:V2HI 3 "register_operand" "d")]
|
UNSPEC_MULSAQ_S_W_PH))
|
UNSPEC_MULSAQ_S_W_PH))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
UNSPEC_MULSAQ_S_W_PH))])]
|
UNSPEC_MULSAQ_S_W_PH))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"mulsaq_s.w.ph\t%q0,%2,%3"
|
"mulsaq_s.w.ph\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; DPAQ*
|
;; DPAQ*
|
(define_insn "mips_dpaq_sa_l_w"
|
(define_insn "mips_dpaq_sa_l_w"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:SI 2 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")
|
(match_operand:SI 3 "register_operand" "d")]
|
(match_operand:SI 3 "register_operand" "d")]
|
UNSPEC_DPAQ_SA_L_W))
|
UNSPEC_DPAQ_SA_L_W))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
UNSPEC_DPAQ_SA_L_W))])]
|
UNSPEC_DPAQ_SA_L_W))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"dpaq_sa.l.w\t%q0,%2,%3"
|
"dpaq_sa.l.w\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; DPSQ*
|
;; DPSQ*
|
(define_insn "mips_dpsq_sa_l_w"
|
(define_insn "mips_dpsq_sa_l_w"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:SI 2 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")
|
(match_operand:SI 3 "register_operand" "d")]
|
(match_operand:SI 3 "register_operand" "d")]
|
UNSPEC_DPSQ_SA_L_W))
|
UNSPEC_DPSQ_SA_L_W))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
UNSPEC_DPSQ_SA_L_W))])]
|
UNSPEC_DPSQ_SA_L_W))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"dpsq_sa.l.w\t%q0,%2,%3"
|
"dpsq_sa.l.w\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; MAQ*
|
;; MAQ*
|
(define_insn "mips_maq_s_w_phl"
|
(define_insn "mips_maq_s_w_phl"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 3 "register_operand" "d")]
|
(match_operand:V2HI 3 "register_operand" "d")]
|
UNSPEC_MAQ_S_W_PHL))
|
UNSPEC_MAQ_S_W_PHL))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
UNSPEC_MAQ_S_W_PHL))])]
|
UNSPEC_MAQ_S_W_PHL))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"maq_s.w.phl\t%q0,%2,%3"
|
"maq_s.w.phl\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_maq_s_w_phr"
|
(define_insn "mips_maq_s_w_phr"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 3 "register_operand" "d")]
|
(match_operand:V2HI 3 "register_operand" "d")]
|
UNSPEC_MAQ_S_W_PHR))
|
UNSPEC_MAQ_S_W_PHR))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
UNSPEC_MAQ_S_W_PHR))])]
|
UNSPEC_MAQ_S_W_PHR))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"maq_s.w.phr\t%q0,%2,%3"
|
"maq_s.w.phr\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; MAQ_SA*
|
;; MAQ_SA*
|
(define_insn "mips_maq_sa_w_phl"
|
(define_insn "mips_maq_sa_w_phl"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 3 "register_operand" "d")]
|
(match_operand:V2HI 3 "register_operand" "d")]
|
UNSPEC_MAQ_SA_W_PHL))
|
UNSPEC_MAQ_SA_W_PHL))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
UNSPEC_MAQ_SA_W_PHL))])]
|
UNSPEC_MAQ_SA_W_PHL))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"maq_sa.w.phl\t%q0,%2,%3"
|
"maq_sa.w.phl\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_maq_sa_w_phr"
|
(define_insn "mips_maq_sa_w_phr"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")
|
(match_operand:V2HI 3 "register_operand" "d")]
|
(match_operand:V2HI 3 "register_operand" "d")]
|
UNSPEC_MAQ_SA_W_PHR))
|
UNSPEC_MAQ_SA_W_PHR))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
UNSPEC_MAQ_SA_W_PHR))])]
|
UNSPEC_MAQ_SA_W_PHR))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"maq_sa.w.phr\t%q0,%2,%3"
|
"maq_sa.w.phr\t%q0,%2,%3"
|
[(set_attr "type" "imadd")
|
[(set_attr "type" "imadd")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation
|
;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation
|
;; BITREV
|
;; BITREV
|
(define_insn "mips_bitrev"
|
(define_insn "mips_bitrev"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")]
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")]
|
UNSPEC_BITREV))]
|
UNSPEC_BITREV))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"bitrev\t%0,%1"
|
"bitrev\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; INSV
|
;; INSV
|
(define_insn "mips_insv"
|
(define_insn "mips_insv"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "0")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")
|
(reg:CCDSP CCDSP_SC_REGNUM)
|
(reg:CCDSP CCDSP_SC_REGNUM)
|
(reg:CCDSP CCDSP_PO_REGNUM)]
|
(reg:CCDSP CCDSP_PO_REGNUM)]
|
UNSPEC_INSV))]
|
UNSPEC_INSV))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"insv\t%0,%2"
|
"insv\t%0,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; REPL*
|
;; REPL*
|
(define_insn "mips_repl_qb"
|
(define_insn "mips_repl_qb"
|
[(set (match_operand:V4QI 0 "register_operand" "=d,d")
|
[(set (match_operand:V4QI 0 "register_operand" "=d,d")
|
(unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")]
|
(unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")]
|
UNSPEC_REPL_QB))]
|
UNSPEC_REPL_QB))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff)
|
if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff)
|
operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
|
operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
|
return "repl.qb\t%0,%1";
|
return "repl.qb\t%0,%1";
|
}
|
}
|
return "replv.qb\t%0,%1";
|
return "replv.qb\t%0,%1";
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_repl_ph"
|
(define_insn "mips_repl_ph"
|
[(set (match_operand:V2HI 0 "register_operand" "=d,d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d,d")
|
(unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")]
|
(unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")]
|
UNSPEC_REPL_PH))]
|
UNSPEC_REPL_PH))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"@
|
"@
|
repl.ph\t%0,%1
|
repl.ph\t%0,%1
|
replv.ph\t%0,%1"
|
replv.ph\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick
|
;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick
|
;; CMPU.* CMP.*
|
;; CMPU.* CMP.*
|
(define_insn "mips_cmp_eq_"
|
(define_insn "mips_cmp_eq_"
|
[(set (reg:CCDSP CCDSP_CC_REGNUM)
|
[(set (reg:CCDSP CCDSP_CC_REGNUM)
|
(unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
|
(unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
|
(match_operand:DSPV 1 "register_operand" "d")
|
(match_operand:DSPV 1 "register_operand" "d")
|
(reg:CCDSP CCDSP_CC_REGNUM)]
|
(reg:CCDSP CCDSP_CC_REGNUM)]
|
UNSPEC_CMP_EQ))]
|
UNSPEC_CMP_EQ))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"cmp.eq.\t%0,%1"
|
"cmp.eq.\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_cmp_lt_"
|
(define_insn "mips_cmp_lt_"
|
[(set (reg:CCDSP CCDSP_CC_REGNUM)
|
[(set (reg:CCDSP CCDSP_CC_REGNUM)
|
(unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
|
(unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
|
(match_operand:DSPV 1 "register_operand" "d")
|
(match_operand:DSPV 1 "register_operand" "d")
|
(reg:CCDSP CCDSP_CC_REGNUM)]
|
(reg:CCDSP CCDSP_CC_REGNUM)]
|
UNSPEC_CMP_LT))]
|
UNSPEC_CMP_LT))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"cmp.lt.\t%0,%1"
|
"cmp.lt.\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_cmp_le_"
|
(define_insn "mips_cmp_le_"
|
[(set (reg:CCDSP CCDSP_CC_REGNUM)
|
[(set (reg:CCDSP CCDSP_CC_REGNUM)
|
(unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
|
(unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
|
(match_operand:DSPV 1 "register_operand" "d")
|
(match_operand:DSPV 1 "register_operand" "d")
|
(reg:CCDSP CCDSP_CC_REGNUM)]
|
(reg:CCDSP CCDSP_CC_REGNUM)]
|
UNSPEC_CMP_LE))]
|
UNSPEC_CMP_LE))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"cmp.le.\t%0,%1"
|
"cmp.le.\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_cmpgu_eq_qb"
|
(define_insn "mips_cmpgu_eq_qb"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
|
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
|
(match_operand:V4QI 2 "register_operand" "d")]
|
(match_operand:V4QI 2 "register_operand" "d")]
|
UNSPEC_CMPGU_EQ_QB))]
|
UNSPEC_CMPGU_EQ_QB))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"cmpgu.eq.qb\t%0,%1,%2"
|
"cmpgu.eq.qb\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_cmpgu_lt_qb"
|
(define_insn "mips_cmpgu_lt_qb"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
|
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
|
(match_operand:V4QI 2 "register_operand" "d")]
|
(match_operand:V4QI 2 "register_operand" "d")]
|
UNSPEC_CMPGU_LT_QB))]
|
UNSPEC_CMPGU_LT_QB))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"cmpgu.lt.qb\t%0,%1,%2"
|
"cmpgu.lt.qb\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_cmpgu_le_qb"
|
(define_insn "mips_cmpgu_le_qb"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
|
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
|
(match_operand:V4QI 2 "register_operand" "d")]
|
(match_operand:V4QI 2 "register_operand" "d")]
|
UNSPEC_CMPGU_LE_QB))]
|
UNSPEC_CMPGU_LE_QB))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"cmpgu.le.qb\t%0,%1,%2"
|
"cmpgu.le.qb\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; PICK*
|
;; PICK*
|
(define_insn "mips_pick_"
|
(define_insn "mips_pick_"
|
[(set (match_operand:DSPV 0 "register_operand" "=d")
|
[(set (match_operand:DSPV 0 "register_operand" "=d")
|
(unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d")
|
(unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d")
|
(match_operand:DSPV 2 "register_operand" "d")
|
(match_operand:DSPV 2 "register_operand" "d")
|
(reg:CCDSP CCDSP_CC_REGNUM)]
|
(reg:CCDSP CCDSP_CC_REGNUM)]
|
UNSPEC_PICK))]
|
UNSPEC_PICK))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"pick.\t%0,%1,%2"
|
"pick.\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; PACKRL*
|
;; PACKRL*
|
(define_insn "mips_packrl_ph"
|
(define_insn "mips_packrl_ph"
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
|
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
|
(match_operand:V2HI 2 "register_operand" "d")]
|
(match_operand:V2HI 2 "register_operand" "d")]
|
UNSPEC_PACKRL_PH))]
|
UNSPEC_PACKRL_PH))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"packrl.ph\t%0,%1,%2"
|
"packrl.ph\t%0,%1,%2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access
|
;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access
|
;; EXTR*
|
;; EXTR*
|
(define_insn "mips_extr_w"
|
(define_insn "mips_extr_w"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_EXTR_W))
|
UNSPEC_EXTR_W))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
return "extr.w\t%0,%q1,%2";
|
return "extr.w\t%0,%q1,%2";
|
}
|
}
|
return "extrv.w\t%0,%q1,%2";
|
return "extrv.w\t%0,%q1,%2";
|
}
|
}
|
[(set_attr "type" "mfhilo")
|
[(set_attr "type" "mfhilo")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_extr_r_w"
|
(define_insn "mips_extr_r_w"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_EXTR_R_W))
|
UNSPEC_EXTR_R_W))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
return "extr_r.w\t%0,%q1,%2";
|
return "extr_r.w\t%0,%q1,%2";
|
}
|
}
|
return "extrv_r.w\t%0,%q1,%2";
|
return "extrv_r.w\t%0,%q1,%2";
|
}
|
}
|
[(set_attr "type" "mfhilo")
|
[(set_attr "type" "mfhilo")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_extr_rs_w"
|
(define_insn "mips_extr_rs_w"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_EXTR_RS_W))
|
UNSPEC_EXTR_RS_W))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
return "extr_rs.w\t%0,%q1,%2";
|
return "extr_rs.w\t%0,%q1,%2";
|
}
|
}
|
return "extrv_rs.w\t%0,%q1,%2";
|
return "extrv_rs.w\t%0,%q1,%2";
|
}
|
}
|
[(set_attr "type" "mfhilo")
|
[(set_attr "type" "mfhilo")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; EXTR*_S.H
|
;; EXTR*_S.H
|
(define_insn "mips_extr_s_h"
|
(define_insn "mips_extr_s_h"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_EXTR_S_H))
|
UNSPEC_EXTR_S_H))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
return "extr_s.h\t%0,%q1,%2";
|
return "extr_s.h\t%0,%q1,%2";
|
}
|
}
|
return "extrv_s.h\t%0,%q1,%2";
|
return "extrv_s.h\t%0,%q1,%2";
|
}
|
}
|
[(set_attr "type" "mfhilo")
|
[(set_attr "type" "mfhilo")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; EXTP*
|
;; EXTP*
|
(define_insn "mips_extp"
|
(define_insn "mips_extp"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(match_operand:SI 2 "arith_operand" "I,d")
|
(match_operand:SI 2 "arith_operand" "I,d")
|
(reg:CCDSP CCDSP_PO_REGNUM)]
|
(reg:CCDSP CCDSP_PO_REGNUM)]
|
UNSPEC_EXTP))
|
UNSPEC_EXTP))
|
(set (reg:CCDSP CCDSP_EF_REGNUM)
|
(set (reg:CCDSP CCDSP_EF_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
return "extp\t%0,%q1,%2";
|
return "extp\t%0,%q1,%2";
|
}
|
}
|
return "extpv\t%0,%q1,%2";
|
return "extpv\t%0,%q1,%2";
|
}
|
}
|
[(set_attr "type" "mfhilo")
|
[(set_attr "type" "mfhilo")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mips_extpdp"
|
(define_insn "mips_extpdp"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
|
(match_operand:SI 2 "arith_operand" "I,d")
|
(match_operand:SI 2 "arith_operand" "I,d")
|
(reg:CCDSP CCDSP_PO_REGNUM)]
|
(reg:CCDSP CCDSP_PO_REGNUM)]
|
UNSPEC_EXTPDP))
|
UNSPEC_EXTPDP))
|
(set (reg:CCDSP CCDSP_PO_REGNUM)
|
(set (reg:CCDSP CCDSP_PO_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)
|
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
|
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
|
(set (reg:CCDSP CCDSP_EF_REGNUM)
|
(set (reg:CCDSP CCDSP_EF_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])]
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
|
return "extpdp\t%0,%q1,%2";
|
return "extpdp\t%0,%q1,%2";
|
}
|
}
|
return "extpdpv\t%0,%q1,%2";
|
return "extpdpv\t%0,%q1,%2";
|
}
|
}
|
[(set_attr "type" "mfhilo")
|
[(set_attr "type" "mfhilo")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; SHILO*
|
;; SHILO*
|
(define_insn "mips_shilo"
|
(define_insn "mips_shilo"
|
[(set (match_operand:DI 0 "register_operand" "=a,a")
|
[(set (match_operand:DI 0 "register_operand" "=a,a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0,0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0,0")
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
(match_operand:SI 2 "arith_operand" "I,d")]
|
UNSPEC_SHILO))]
|
UNSPEC_SHILO))]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
{
|
{
|
if (which_alternative == 0)
|
if (which_alternative == 0)
|
{
|
{
|
if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31)
|
if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31)
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
|
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
|
return "shilo\t%q0,%2";
|
return "shilo\t%q0,%2";
|
}
|
}
|
return "shilov\t%q0,%2";
|
return "shilov\t%q0,%2";
|
}
|
}
|
[(set_attr "type" "mfhilo")
|
[(set_attr "type" "mfhilo")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; MTHLIP*
|
;; MTHLIP*
|
(define_insn "mips_mthlip"
|
(define_insn "mips_mthlip"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
[(set (match_operand:DI 0 "register_operand" "=a")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
(match_operand:SI 2 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")
|
(reg:CCDSP CCDSP_PO_REGNUM)]
|
(reg:CCDSP CCDSP_PO_REGNUM)]
|
UNSPEC_MTHLIP))
|
UNSPEC_MTHLIP))
|
(set (reg:CCDSP CCDSP_PO_REGNUM)
|
(set (reg:CCDSP CCDSP_PO_REGNUM)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)
|
(unspec:CCDSP [(match_dup 1) (match_dup 2)
|
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
|
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
|
"TARGET_DSP && !TARGET_64BIT"
|
"TARGET_DSP && !TARGET_64BIT"
|
"mthlip\t%2,%q0"
|
"mthlip\t%2,%q0"
|
[(set_attr "type" "mfhilo")
|
[(set_attr "type" "mfhilo")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; WRDSP
|
;; WRDSP
|
(define_insn "mips_wrdsp"
|
(define_insn "mips_wrdsp"
|
[(parallel
|
[(parallel
|
[(set (reg:CCDSP CCDSP_PO_REGNUM)
|
[(set (reg:CCDSP CCDSP_PO_REGNUM)
|
(unspec:CCDSP [(match_operand:SI 0 "register_operand" "d")
|
(unspec:CCDSP [(match_operand:SI 0 "register_operand" "d")
|
(match_operand:SI 1 "const_uimm6_operand" "YA")]
|
(match_operand:SI 1 "const_uimm6_operand" "YA")]
|
UNSPEC_WRDSP))
|
UNSPEC_WRDSP))
|
(set (reg:CCDSP CCDSP_SC_REGNUM)
|
(set (reg:CCDSP CCDSP_SC_REGNUM)
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
|
(set (reg:CCDSP CCDSP_CA_REGNUM)
|
(set (reg:CCDSP CCDSP_CA_REGNUM)
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
|
(set (reg:CCDSP CCDSP_CC_REGNUM)
|
(set (reg:CCDSP CCDSP_CC_REGNUM)
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
|
(set (reg:CCDSP CCDSP_EF_REGNUM)
|
(set (reg:CCDSP CCDSP_EF_REGNUM)
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
|
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"wrdsp\t%0,%1"
|
"wrdsp\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; RDDSP
|
;; RDDSP
|
(define_insn "mips_rddsp"
|
(define_insn "mips_rddsp"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA")
|
(unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA")
|
(reg:CCDSP CCDSP_PO_REGNUM)
|
(reg:CCDSP CCDSP_PO_REGNUM)
|
(reg:CCDSP CCDSP_SC_REGNUM)
|
(reg:CCDSP CCDSP_SC_REGNUM)
|
(reg:CCDSP CCDSP_CA_REGNUM)
|
(reg:CCDSP CCDSP_CA_REGNUM)
|
(reg:CCDSP CCDSP_OU_REGNUM)
|
(reg:CCDSP CCDSP_OU_REGNUM)
|
(reg:CCDSP CCDSP_CC_REGNUM)
|
(reg:CCDSP CCDSP_CC_REGNUM)
|
(reg:CCDSP CCDSP_EF_REGNUM)]
|
(reg:CCDSP CCDSP_EF_REGNUM)]
|
UNSPEC_RDDSP))]
|
UNSPEC_RDDSP))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"rddsp\t%0,%1"
|
"rddsp\t%0,%1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load
|
;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load
|
;; L*X
|
;; L*X
|
(define_insn "mips_lbux"
|
(define_insn "mips_lbux"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1
|
(zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1
|
"register_operand" "d")
|
"register_operand" "d")
|
(match_operand:SI 2
|
(match_operand:SI 2
|
"register_operand" "d")))))]
|
"register_operand" "d")))))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"lbux\t%0,%2(%1)"
|
"lbux\t%0,%2(%1)"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "mode" "SI")
|
(set_attr "mode" "SI")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "mips_lhx"
|
(define_insn "mips_lhx"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(sign_extend:SI (mem:HI (plus:SI (match_operand:SI 1
|
(sign_extend:SI (mem:HI (plus:SI (match_operand:SI 1
|
"register_operand" "d")
|
"register_operand" "d")
|
(match_operand:SI 2
|
(match_operand:SI 2
|
"register_operand" "d")))))]
|
"register_operand" "d")))))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"lhx\t%0,%2(%1)"
|
"lhx\t%0,%2(%1)"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "mode" "SI")
|
(set_attr "mode" "SI")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "mips_lwx"
|
(define_insn "mips_lwx"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
|
(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d"))))]
|
(match_operand:SI 2 "register_operand" "d"))))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"lwx\t%0,%2(%1)"
|
"lwx\t%0,%2(%1)"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "mode" "SI")
|
(set_attr "mode" "SI")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
;; Table 2-8. MIPS DSP ASE Instructions: Branch
|
;; Table 2-8. MIPS DSP ASE Instructions: Branch
|
;; BPOSGE32
|
;; BPOSGE32
|
(define_insn "mips_bposge"
|
(define_insn "mips_bposge"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM)
|
(if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM)
|
(match_operand:SI 0 "immediate_operand" "I"))
|
(match_operand:SI 0 "immediate_operand" "I"))
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
"TARGET_DSP"
|
"TARGET_DSP"
|
"%*bposge%0\t%1%/"
|
"%*bposge%0\t%1%/"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "mode" "none")])
|
(set_attr "mode" "none")])
|
|
|
|
|
