Subversion Repositories openrisc_2011-10-31

/* Subroutines used for MIPS code generation.

/* Subroutines used for MIPS code generation.

   Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,

   Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,

   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.

   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.

   Contributed by A. Lichnewsky, lich@inria.inria.fr.

   Contributed by A. Lichnewsky, lich@inria.inria.fr.

   Changes by Michael Meissner, meissner@osf.org.

   Changes by Michael Meissner, meissner@osf.org.

   64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and

   64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and

   Brendan Eich, brendan@microunity.com.

   Brendan Eich, brendan@microunity.com.

This file is part of GCC.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify

GCC is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 3, or (at your option)

the Free Software Foundation; either version 3, or (at your option)

any later version.

any later version.

GCC is distributed in the hope that it will be useful,

GCC is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

You should have received a copy of the GNU General Public License

along with GCC; see the file COPYING3.  If not see

along with GCC; see the file COPYING3.  If not see

<http://www.gnu.org/licenses/>.  */

<http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "config.h"

#include "system.h"

#include "system.h"

#include "coretypes.h"

#include "coretypes.h"

#include "tm.h"

#include "tm.h"

#include <signal.h>

#include <signal.h>

#include "rtl.h"

#include "rtl.h"

#include "regs.h"

#include "regs.h"

#include "hard-reg-set.h"

#include "hard-reg-set.h"

#include "real.h"

#include "real.h"

#include "insn-config.h"

#include "insn-config.h"

#include "conditions.h"

#include "conditions.h"

#include "insn-attr.h"

#include "insn-attr.h"

#include "recog.h"

#include "recog.h"

#include "toplev.h"

#include "toplev.h"

#include "output.h"

#include "output.h"

#include "tree.h"

#include "tree.h"

#include "function.h"

#include "function.h"

#include "expr.h"

#include "expr.h"

#include "optabs.h"

#include "optabs.h"

#include "flags.h"

#include "flags.h"

#include "reload.h"

#include "reload.h"

#include "tm_p.h"

#include "tm_p.h"

#include "ggc.h"

#include "ggc.h"

#include "gstab.h"

#include "gstab.h"

#include "hashtab.h"

#include "hashtab.h"

#include "debug.h"

#include "debug.h"

#include "target.h"

#include "target.h"

#include "target-def.h"

#include "target-def.h"

#include "integrate.h"

#include "integrate.h"

#include "langhooks.h"

#include "langhooks.h"

#include "cfglayout.h"

#include "cfglayout.h"

#include "sched-int.h"

#include "sched-int.h"

#include "tree-gimple.h"

#include "tree-gimple.h"

#include "bitmap.h"

#include "bitmap.h"

/* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF.  */

/* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF.  */

#define UNSPEC_ADDRESS_P(X)                                     \

#define UNSPEC_ADDRESS_P(X)                                     \

  (GET_CODE (X) == UNSPEC                                       \

  (GET_CODE (X) == UNSPEC                                       \

   && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST                       \

   && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST                       \

   && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)

   && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)

/* Extract the symbol or label from UNSPEC wrapper X.  */

/* Extract the symbol or label from UNSPEC wrapper X.  */

#define UNSPEC_ADDRESS(X) \

#define UNSPEC_ADDRESS(X) \

  XVECEXP (X, 0, 0)

  XVECEXP (X, 0, 0)

/* Extract the symbol type from UNSPEC wrapper X.  */

/* Extract the symbol type from UNSPEC wrapper X.  */

#define UNSPEC_ADDRESS_TYPE(X) \

#define UNSPEC_ADDRESS_TYPE(X) \

  ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))

  ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))

/* The maximum distance between the top of the stack frame and the

/* The maximum distance between the top of the stack frame and the

   value $sp has when we save & restore registers.

   value $sp has when we save & restore registers.

   Use a maximum gap of 0x100 in the mips16 case.  We can then use

   Use a maximum gap of 0x100 in the mips16 case.  We can then use

   unextended instructions to save and restore registers, and to

   unextended instructions to save and restore registers, and to

   allocate and deallocate the top part of the frame.

   allocate and deallocate the top part of the frame.

   The value in the !mips16 case must be a SMALL_OPERAND and must

   The value in the !mips16 case must be a SMALL_OPERAND and must

   preserve the maximum stack alignment.  */

   preserve the maximum stack alignment.  */

#define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)

#define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)

/* True if INSN is a mips.md pattern or asm statement.  */

/* True if INSN is a mips.md pattern or asm statement.  */

#define USEFUL_INSN_P(INSN)                                             \

#define USEFUL_INSN_P(INSN)                                             \

  (INSN_P (INSN)                                                        \

  (INSN_P (INSN)                                                        \

   && GET_CODE (PATTERN (INSN)) != USE                                  \

   && GET_CODE (PATTERN (INSN)) != USE                                  \

   && GET_CODE (PATTERN (INSN)) != CLOBBER                              \

   && GET_CODE (PATTERN (INSN)) != CLOBBER                              \

   && GET_CODE (PATTERN (INSN)) != ADDR_VEC                             \

   && GET_CODE (PATTERN (INSN)) != ADDR_VEC                             \

   && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)

   && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)

/* If INSN is a delayed branch sequence, return the first instruction

/* If INSN is a delayed branch sequence, return the first instruction

   in the sequence, otherwise return INSN itself.  */

   in the sequence, otherwise return INSN itself.  */

#define SEQ_BEGIN(INSN)                                                 \

#define SEQ_BEGIN(INSN)                                                 \

  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \

  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \

   ? XVECEXP (PATTERN (INSN), 0, 0)                                       \

   ? XVECEXP (PATTERN (INSN), 0, 0)                                       \

   : (INSN))

   : (INSN))

/* Likewise for the last instruction in a delayed branch sequence.  */

/* Likewise for the last instruction in a delayed branch sequence.  */

#define SEQ_END(INSN)                                                   \

#define SEQ_END(INSN)                                                   \

  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \

  (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE               \

   ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \

   ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \

   : (INSN))

   : (INSN))

/* Execute the following loop body with SUBINSN set to each instruction

/* Execute the following loop body with SUBINSN set to each instruction

   between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive.  */

   between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive.  */

#define FOR_EACH_SUBINSN(SUBINSN, INSN)                                 \

#define FOR_EACH_SUBINSN(SUBINSN, INSN)                                 \

  for ((SUBINSN) = SEQ_BEGIN (INSN);                                    \

  for ((SUBINSN) = SEQ_BEGIN (INSN);                                    \

       (SUBINSN) != NEXT_INSN (SEQ_END (INSN));                         \

       (SUBINSN) != NEXT_INSN (SEQ_END (INSN));                         \

       (SUBINSN) = NEXT_INSN (SUBINSN))

       (SUBINSN) = NEXT_INSN (SUBINSN))

/* Classifies an address.

/* Classifies an address.

   ADDRESS_REG

   ADDRESS_REG

       A natural register + offset address.  The register satisfies

       A natural register + offset address.  The register satisfies

       mips_valid_base_register_p and the offset is a const_arith_operand.

       mips_valid_base_register_p and the offset is a const_arith_operand.

   ADDRESS_LO_SUM

   ADDRESS_LO_SUM

       A LO_SUM rtx.  The first operand is a valid base register and

       A LO_SUM rtx.  The first operand is a valid base register and

       the second operand is a symbolic address.

       the second operand is a symbolic address.

   ADDRESS_CONST_INT

   ADDRESS_CONST_INT

       A signed 16-bit constant address.

       A signed 16-bit constant address.

   ADDRESS_SYMBOLIC:

   ADDRESS_SYMBOLIC:

       A constant symbolic address (equivalent to CONSTANT_SYMBOLIC).  */

       A constant symbolic address (equivalent to CONSTANT_SYMBOLIC).  */

enum mips_address_type {

enum mips_address_type {

  ADDRESS_REG,

  ADDRESS_REG,

  ADDRESS_LO_SUM,

  ADDRESS_LO_SUM,

  ADDRESS_CONST_INT,

  ADDRESS_CONST_INT,

  ADDRESS_SYMBOLIC

  ADDRESS_SYMBOLIC

};

};

/* Classifies the prototype of a builtin function.  */

/* Classifies the prototype of a builtin function.  */

enum mips_function_type

enum mips_function_type

{

{

  MIPS_V2SF_FTYPE_V2SF,

  MIPS_V2SF_FTYPE_V2SF,

  MIPS_V2SF_FTYPE_V2SF_V2SF,

  MIPS_V2SF_FTYPE_V2SF_V2SF,

  MIPS_V2SF_FTYPE_V2SF_V2SF_INT,

  MIPS_V2SF_FTYPE_V2SF_V2SF_INT,

  MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,

  MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,

  MIPS_V2SF_FTYPE_SF_SF,

  MIPS_V2SF_FTYPE_SF_SF,

  MIPS_INT_FTYPE_V2SF_V2SF,

  MIPS_INT_FTYPE_V2SF_V2SF,

  MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,

  MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,

  MIPS_INT_FTYPE_SF_SF,

  MIPS_INT_FTYPE_SF_SF,

  MIPS_INT_FTYPE_DF_DF,

  MIPS_INT_FTYPE_DF_DF,

  MIPS_SF_FTYPE_V2SF,

  MIPS_SF_FTYPE_V2SF,

  MIPS_SF_FTYPE_SF,

  MIPS_SF_FTYPE_SF,

  MIPS_SF_FTYPE_SF_SF,

  MIPS_SF_FTYPE_SF_SF,

  MIPS_DF_FTYPE_DF,

  MIPS_DF_FTYPE_DF,

  MIPS_DF_FTYPE_DF_DF,

  MIPS_DF_FTYPE_DF_DF,

  /* For MIPS DSP ASE  */

  /* For MIPS DSP ASE  */

  MIPS_DI_FTYPE_DI_SI,

  MIPS_DI_FTYPE_DI_SI,

  MIPS_DI_FTYPE_DI_SI_SI,

  MIPS_DI_FTYPE_DI_SI_SI,

  MIPS_DI_FTYPE_DI_V2HI_V2HI,

  MIPS_DI_FTYPE_DI_V2HI_V2HI,

  MIPS_DI_FTYPE_DI_V4QI_V4QI,

  MIPS_DI_FTYPE_DI_V4QI_V4QI,

  MIPS_SI_FTYPE_DI_SI,

  MIPS_SI_FTYPE_DI_SI,

  MIPS_SI_FTYPE_PTR_SI,

  MIPS_SI_FTYPE_PTR_SI,

  MIPS_SI_FTYPE_SI,

  MIPS_SI_FTYPE_SI,

  MIPS_SI_FTYPE_SI_SI,

  MIPS_SI_FTYPE_SI_SI,

  MIPS_SI_FTYPE_V2HI,

  MIPS_SI_FTYPE_V2HI,

  MIPS_SI_FTYPE_V2HI_V2HI,

  MIPS_SI_FTYPE_V2HI_V2HI,

  MIPS_SI_FTYPE_V4QI,

  MIPS_SI_FTYPE_V4QI,

  MIPS_SI_FTYPE_V4QI_V4QI,

  MIPS_SI_FTYPE_V4QI_V4QI,

  MIPS_SI_FTYPE_VOID,

  MIPS_SI_FTYPE_VOID,

  MIPS_V2HI_FTYPE_SI,

  MIPS_V2HI_FTYPE_SI,

  MIPS_V2HI_FTYPE_SI_SI,

  MIPS_V2HI_FTYPE_SI_SI,

  MIPS_V2HI_FTYPE_V2HI,

  MIPS_V2HI_FTYPE_V2HI,

  MIPS_V2HI_FTYPE_V2HI_SI,

  MIPS_V2HI_FTYPE_V2HI_SI,

  MIPS_V2HI_FTYPE_V2HI_V2HI,

  MIPS_V2HI_FTYPE_V2HI_V2HI,

  MIPS_V2HI_FTYPE_V4QI,

  MIPS_V2HI_FTYPE_V4QI,

  MIPS_V2HI_FTYPE_V4QI_V2HI,

  MIPS_V2HI_FTYPE_V4QI_V2HI,

  MIPS_V4QI_FTYPE_SI,

  MIPS_V4QI_FTYPE_SI,

  MIPS_V4QI_FTYPE_V2HI_V2HI,

  MIPS_V4QI_FTYPE_V2HI_V2HI,

  MIPS_V4QI_FTYPE_V4QI_SI,

  MIPS_V4QI_FTYPE_V4QI_SI,

  MIPS_V4QI_FTYPE_V4QI_V4QI,

  MIPS_V4QI_FTYPE_V4QI_V4QI,

  MIPS_VOID_FTYPE_SI_SI,

  MIPS_VOID_FTYPE_SI_SI,

  MIPS_VOID_FTYPE_V2HI_V2HI,

  MIPS_VOID_FTYPE_V2HI_V2HI,

  MIPS_VOID_FTYPE_V4QI_V4QI,

  MIPS_VOID_FTYPE_V4QI_V4QI,

  /* The last type.  */

  /* The last type.  */

  MIPS_MAX_FTYPE_MAX

  MIPS_MAX_FTYPE_MAX

};

};

/* Specifies how a builtin function should be converted into rtl.  */

/* Specifies how a builtin function should be converted into rtl.  */

enum mips_builtin_type

enum mips_builtin_type

{

{

  /* The builtin corresponds directly to an .md pattern.  The return

  /* The builtin corresponds directly to an .md pattern.  The return

     value is mapped to operand 0 and the arguments are mapped to

     value is mapped to operand 0 and the arguments are mapped to

     operands 1 and above.  */

     operands 1 and above.  */

  MIPS_BUILTIN_DIRECT,

  MIPS_BUILTIN_DIRECT,

  /* The builtin corresponds directly to an .md pattern.  There is no return

  /* The builtin corresponds directly to an .md pattern.  There is no return

     value and the arguments are mapped to operands 0 and above.  */

     value and the arguments are mapped to operands 0 and above.  */

  MIPS_BUILTIN_DIRECT_NO_TARGET,

  MIPS_BUILTIN_DIRECT_NO_TARGET,

  /* The builtin corresponds to a comparison instruction followed by

  /* The builtin corresponds to a comparison instruction followed by

     a mips_cond_move_tf_ps pattern.  The first two arguments are the

     a mips_cond_move_tf_ps pattern.  The first two arguments are the

     values to compare and the second two arguments are the vector

     values to compare and the second two arguments are the vector

     operands for the movt.ps or movf.ps instruction (in assembly order).  */

     operands for the movt.ps or movf.ps instruction (in assembly order).  */

  MIPS_BUILTIN_MOVF,

  MIPS_BUILTIN_MOVF,

  MIPS_BUILTIN_MOVT,

  MIPS_BUILTIN_MOVT,

  /* The builtin corresponds to a V2SF comparison instruction.  Operand 0

  /* The builtin corresponds to a V2SF comparison instruction.  Operand 0

     of this instruction is the result of the comparison, which has mode

     of this instruction is the result of the comparison, which has mode

     CCV2 or CCV4.  The function arguments are mapped to operands 1 and

     CCV2 or CCV4.  The function arguments are mapped to operands 1 and

     above.  The function's return value is an SImode boolean that is

     above.  The function's return value is an SImode boolean that is

     true under the following conditions:

     true under the following conditions:

     MIPS_BUILTIN_CMP_ANY: one of the registers is true

     MIPS_BUILTIN_CMP_ANY: one of the registers is true

     MIPS_BUILTIN_CMP_ALL: all of the registers are true

     MIPS_BUILTIN_CMP_ALL: all of the registers are true

     MIPS_BUILTIN_CMP_LOWER: the first register is true

     MIPS_BUILTIN_CMP_LOWER: the first register is true

     MIPS_BUILTIN_CMP_UPPER: the second register is true.  */

     MIPS_BUILTIN_CMP_UPPER: the second register is true.  */

  MIPS_BUILTIN_CMP_ANY,

  MIPS_BUILTIN_CMP_ANY,

  MIPS_BUILTIN_CMP_ALL,

  MIPS_BUILTIN_CMP_ALL,

  MIPS_BUILTIN_CMP_UPPER,

  MIPS_BUILTIN_CMP_UPPER,

  MIPS_BUILTIN_CMP_LOWER,

  MIPS_BUILTIN_CMP_LOWER,

  /* As above, but the instruction only sets a single $fcc register.  */

  /* As above, but the instruction only sets a single $fcc register.  */

  MIPS_BUILTIN_CMP_SINGLE,

  MIPS_BUILTIN_CMP_SINGLE,

  /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */

  /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */

  MIPS_BUILTIN_BPOSGE32

  MIPS_BUILTIN_BPOSGE32

};

};

/* Invokes MACRO (COND) for each c.cond.fmt condition.  */

/* Invokes MACRO (COND) for each c.cond.fmt condition.  */

#define MIPS_FP_CONDITIONS(MACRO) \

#define MIPS_FP_CONDITIONS(MACRO) \

  MACRO (f),    \

  MACRO (f),    \

  MACRO (un),   \

  MACRO (un),   \

  MACRO (eq),   \

  MACRO (eq),   \

  MACRO (ueq),  \

  MACRO (ueq),  \

  MACRO (olt),  \

  MACRO (olt),  \

  MACRO (ult),  \

  MACRO (ult),  \

  MACRO (ole),  \

  MACRO (ole),  \

  MACRO (ule),  \

  MACRO (ule),  \

  MACRO (sf),   \

  MACRO (sf),   \

  MACRO (ngle), \

  MACRO (ngle), \

  MACRO (seq),  \

  MACRO (seq),  \

  MACRO (ngl),  \

  MACRO (ngl),  \

  MACRO (lt),   \

  MACRO (lt),   \

  MACRO (nge),  \

  MACRO (nge),  \

  MACRO (le),   \

  MACRO (le),   \

  MACRO (ngt)

  MACRO (ngt)

/* Enumerates the codes above as MIPS_FP_COND_<X>.  */

/* Enumerates the codes above as MIPS_FP_COND_<X>.  */

#define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X

#define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X

enum mips_fp_condition {

enum mips_fp_condition {

  MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)

  MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)

};

};

/* Index X provides the string representation of MIPS_FP_COND_<X>.  */

/* Index X provides the string representation of MIPS_FP_COND_<X>.  */

#define STRINGIFY(X) #X

#define STRINGIFY(X) #X

static const char *const mips_fp_conditions[] = {

static const char *const mips_fp_conditions[] = {

  MIPS_FP_CONDITIONS (STRINGIFY)

  MIPS_FP_CONDITIONS (STRINGIFY)

};

};

/* A function to save or store a register.  The first argument is the

/* A function to save or store a register.  The first argument is the

   register and the second is the stack slot.  */

   register and the second is the stack slot.  */

typedef void (*mips_save_restore_fn) (rtx, rtx);

typedef void (*mips_save_restore_fn) (rtx, rtx);

struct mips16_constant;

struct mips16_constant;

struct mips_arg_info;

struct mips_arg_info;

struct mips_address_info;

struct mips_address_info;

struct mips_integer_op;

struct mips_integer_op;

struct mips_sim;

struct mips_sim;

static enum mips_symbol_type mips_classify_symbol (rtx);

static enum mips_symbol_type mips_classify_symbol (rtx);

static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);

static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);

static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);

static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);

static bool mips_valid_base_register_p (rtx, enum machine_mode, int);

static bool mips_valid_base_register_p (rtx, enum machine_mode, int);

static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);

static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);

static bool mips_classify_address (struct mips_address_info *, rtx,

static bool mips_classify_address (struct mips_address_info *, rtx,

                                   enum machine_mode, int);

                                   enum machine_mode, int);

static bool mips_cannot_force_const_mem (rtx);

static bool mips_cannot_force_const_mem (rtx);

static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);

static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);

static int mips_symbol_insns (enum mips_symbol_type);

static int mips_symbol_insns (enum mips_symbol_type);

static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);

static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);

static rtx mips_force_temporary (rtx, rtx);

static rtx mips_force_temporary (rtx, rtx);

static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);

static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);

static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);

static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);

static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);

static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);

static unsigned int mips_build_lower (struct mips_integer_op *,

static unsigned int mips_build_lower (struct mips_integer_op *,

                                      unsigned HOST_WIDE_INT);

                                      unsigned HOST_WIDE_INT);

static unsigned int mips_build_integer (struct mips_integer_op *,

static unsigned int mips_build_integer (struct mips_integer_op *,

                                        unsigned HOST_WIDE_INT);

                                        unsigned HOST_WIDE_INT);

static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);

static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);

static int m16_check_op (rtx, int, int, int);

static int m16_check_op (rtx, int, int, int);

static bool mips_rtx_costs (rtx, int, int, int *);

static bool mips_rtx_costs (rtx, int, int, int *);

static int mips_address_cost (rtx);

static int mips_address_cost (rtx);

static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);

static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);

static void mips_load_call_address (rtx, rtx, int);

static void mips_load_call_address (rtx, rtx, int);

static bool mips_function_ok_for_sibcall (tree, tree);

static bool mips_function_ok_for_sibcall (tree, tree);

static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);

static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);

static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);

static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);

static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);

static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);

static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,

static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,

                           tree, int, struct mips_arg_info *);

                           tree, int, struct mips_arg_info *);

static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);

static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);

static void mips_set_architecture (const struct mips_cpu_info *);

static void mips_set_architecture (const struct mips_cpu_info *);

static void mips_set_tune (const struct mips_cpu_info *);

static void mips_set_tune (const struct mips_cpu_info *);

static bool mips_handle_option (size_t, const char *, int);

static bool mips_handle_option (size_t, const char *, int);

static struct machine_function *mips_init_machine_status (void);

static struct machine_function *mips_init_machine_status (void);

static void print_operand_reloc (FILE *, rtx, const char **);

static void print_operand_reloc (FILE *, rtx, const char **);

#if TARGET_IRIX

#if TARGET_IRIX

static void irix_output_external_libcall (rtx);

static void irix_output_external_libcall (rtx);

#endif

#endif

static void mips_file_start (void);

static void mips_file_start (void);

static void mips_file_end (void);

static void mips_file_end (void);

static bool mips_rewrite_small_data_p (rtx);

static bool mips_rewrite_small_data_p (rtx);

static int mips_small_data_pattern_1 (rtx *, void *);

static int mips_small_data_pattern_1 (rtx *, void *);

static int mips_rewrite_small_data_1 (rtx *, void *);

static int mips_rewrite_small_data_1 (rtx *, void *);

static bool mips_function_has_gp_insn (void);

static bool mips_function_has_gp_insn (void);

static unsigned int mips_global_pointer (void);

static unsigned int mips_global_pointer (void);

static bool mips_save_reg_p (unsigned int);

static bool mips_save_reg_p (unsigned int);

static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,

static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,

                                   mips_save_restore_fn);

                                   mips_save_restore_fn);

static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);

static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);

static void mips_output_cplocal (void);

static void mips_output_cplocal (void);

static void mips_emit_loadgp (void);

static void mips_emit_loadgp (void);

static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);

static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);

static void mips_set_frame_expr (rtx);

static void mips_set_frame_expr (rtx);

static rtx mips_frame_set (rtx, rtx);

static rtx mips_frame_set (rtx, rtx);

static void mips_save_reg (rtx, rtx);

static void mips_save_reg (rtx, rtx);

static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);

static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);

static void mips_restore_reg (rtx, rtx);

static void mips_restore_reg (rtx, rtx);

static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,

static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,

                                  HOST_WIDE_INT, tree);

                                  HOST_WIDE_INT, tree);

static int symbolic_expression_p (rtx);

static int symbolic_expression_p (rtx);

static section *mips_select_rtx_section (enum machine_mode, rtx,

static section *mips_select_rtx_section (enum machine_mode, rtx,

                                         unsigned HOST_WIDE_INT);

                                         unsigned HOST_WIDE_INT);

static section *mips_function_rodata_section (tree);

static section *mips_function_rodata_section (tree);

static bool mips_in_small_data_p (tree);

static bool mips_in_small_data_p (tree);

static bool mips_use_anchors_for_symbol_p (rtx);

static bool mips_use_anchors_for_symbol_p (rtx);

static int mips_fpr_return_fields (tree, tree *);

static int mips_fpr_return_fields (tree, tree *);

static bool mips_return_in_msb (tree);

static bool mips_return_in_msb (tree);

static rtx mips_return_fpr_pair (enum machine_mode mode,

static rtx mips_return_fpr_pair (enum machine_mode mode,

                                 enum machine_mode mode1, HOST_WIDE_INT,

                                 enum machine_mode mode1, HOST_WIDE_INT,

                                 enum machine_mode mode2, HOST_WIDE_INT);

                                 enum machine_mode mode2, HOST_WIDE_INT);

static rtx mips16_gp_pseudo_reg (void);

static rtx mips16_gp_pseudo_reg (void);

static void mips16_fp_args (FILE *, int, int);

static void mips16_fp_args (FILE *, int, int);

static void build_mips16_function_stub (FILE *);

static void build_mips16_function_stub (FILE *);

static rtx dump_constants_1 (enum machine_mode, rtx, rtx);

static rtx dump_constants_1 (enum machine_mode, rtx, rtx);

static void dump_constants (struct mips16_constant *, rtx);

static void dump_constants (struct mips16_constant *, rtx);

static int mips16_insn_length (rtx);

static int mips16_insn_length (rtx);

static int mips16_rewrite_pool_refs (rtx *, void *);

static int mips16_rewrite_pool_refs (rtx *, void *);

static void mips16_lay_out_constants (void);

static void mips16_lay_out_constants (void);

static void mips_sim_reset (struct mips_sim *);

static void mips_sim_reset (struct mips_sim *);

static void mips_sim_init (struct mips_sim *, state_t);

static void mips_sim_init (struct mips_sim *, state_t);

static void mips_sim_next_cycle (struct mips_sim *);

static void mips_sim_next_cycle (struct mips_sim *);

static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);

static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);

static int mips_sim_wait_regs_2 (rtx *, void *);

static int mips_sim_wait_regs_2 (rtx *, void *);

static void mips_sim_wait_regs_1 (rtx *, void *);

static void mips_sim_wait_regs_1 (rtx *, void *);

static void mips_sim_wait_regs (struct mips_sim *, rtx);

static void mips_sim_wait_regs (struct mips_sim *, rtx);

static void mips_sim_wait_units (struct mips_sim *, rtx);

static void mips_sim_wait_units (struct mips_sim *, rtx);

static void mips_sim_wait_insn (struct mips_sim *, rtx);

static void mips_sim_wait_insn (struct mips_sim *, rtx);

static void mips_sim_record_set (rtx, rtx, void *);

static void mips_sim_record_set (rtx, rtx, void *);

static void mips_sim_issue_insn (struct mips_sim *, rtx);

static void mips_sim_issue_insn (struct mips_sim *, rtx);

static void mips_sim_issue_nop (struct mips_sim *);

static void mips_sim_issue_nop (struct mips_sim *);

static void mips_sim_finish_insn (struct mips_sim *, rtx);

static void mips_sim_finish_insn (struct mips_sim *, rtx);

static void vr4130_avoid_branch_rt_conflict (rtx);

static void vr4130_avoid_branch_rt_conflict (rtx);

static void vr4130_align_insns (void);

static void vr4130_align_insns (void);

static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);

static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);

static void mips_avoid_hazards (void);

static void mips_avoid_hazards (void);

static void mips_reorg (void);

static void mips_reorg (void);

static bool mips_strict_matching_cpu_name_p (const char *, const char *);

static bool mips_strict_matching_cpu_name_p (const char *, const char *);

static bool mips_matching_cpu_name_p (const char *, const char *);

static bool mips_matching_cpu_name_p (const char *, const char *);

static const struct mips_cpu_info *mips_parse_cpu (const char *);

static const struct mips_cpu_info *mips_parse_cpu (const char *);

static const struct mips_cpu_info *mips_cpu_info_from_isa (int);

static const struct mips_cpu_info *mips_cpu_info_from_isa (int);

static bool mips_return_in_memory (tree, tree);

static bool mips_return_in_memory (tree, tree);

static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);

static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);

static void mips_macc_chains_record (rtx);

static void mips_macc_chains_record (rtx);

static void mips_macc_chains_reorder (rtx *, int);

static void mips_macc_chains_reorder (rtx *, int);

static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);

static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);

static bool vr4130_true_reg_dependence_p (rtx);

static bool vr4130_true_reg_dependence_p (rtx);

static bool vr4130_swap_insns_p (rtx, rtx);

static bool vr4130_swap_insns_p (rtx, rtx);

static void vr4130_reorder (rtx *, int);

static void vr4130_reorder (rtx *, int);

static void mips_promote_ready (rtx *, int, int);

static void mips_promote_ready (rtx *, int, int);

static int mips_sched_reorder (FILE *, int, rtx *, int *, int);

static int mips_sched_reorder (FILE *, int, rtx *, int *, int);

static int mips_variable_issue (FILE *, int, rtx, int);

static int mips_variable_issue (FILE *, int, rtx, int);

static int mips_adjust_cost (rtx, rtx, rtx, int);

static int mips_adjust_cost (rtx, rtx, rtx, int);

static int mips_issue_rate (void);

static int mips_issue_rate (void);

static int mips_multipass_dfa_lookahead (void);

static int mips_multipass_dfa_lookahead (void);

static void mips_init_libfuncs (void);

static void mips_init_libfuncs (void);

static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,

static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,

                                         tree, int *, int);

                                         tree, int *, int);

static tree mips_build_builtin_va_list (void);

static tree mips_build_builtin_va_list (void);

static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);

static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);

static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,

static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,

                                    tree, bool);

                                    tree, bool);

static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,

static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,

                                tree, bool);

                                tree, bool);

static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,

static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,

                                   tree, bool);

                                   tree, bool);

static bool mips_valid_pointer_mode (enum machine_mode);

static bool mips_valid_pointer_mode (enum machine_mode);

static bool mips_vector_mode_supported_p (enum machine_mode);

static bool mips_vector_mode_supported_p (enum machine_mode);

static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);

static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);

static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);

static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);

static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);

static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);

static void mips_init_builtins (void);

static void mips_init_builtins (void);

static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);

static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);

static rtx mips_expand_builtin_movtf (enum mips_builtin_type,

static rtx mips_expand_builtin_movtf (enum mips_builtin_type,

                                      enum insn_code, enum mips_fp_condition,

                                      enum insn_code, enum mips_fp_condition,

                                      rtx, tree);

                                      rtx, tree);

static rtx mips_expand_builtin_compare (enum mips_builtin_type,

static rtx mips_expand_builtin_compare (enum mips_builtin_type,

                                        enum insn_code, enum mips_fp_condition,

                                        enum insn_code, enum mips_fp_condition,

                                        rtx, tree);

                                        rtx, tree);

static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);

static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);

static void mips_encode_section_info (tree, rtx, int);

static void mips_encode_section_info (tree, rtx, int);

static void mips_extra_live_on_entry (bitmap);

static void mips_extra_live_on_entry (bitmap);

static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);

static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);

/* Structure to be filled in by compute_frame_size with register

/* Structure to be filled in by compute_frame_size with register

   save masks, and offsets for the current function.  */

   save masks, and offsets for the current function.  */

struct mips_frame_info GTY(())

struct mips_frame_info GTY(())

{

{

  HOST_WIDE_INT total_size;     /* # bytes that the entire frame takes up */

  HOST_WIDE_INT total_size;     /* # bytes that the entire frame takes up */

  HOST_WIDE_INT var_size;       /* # bytes that variables take up */

  HOST_WIDE_INT var_size;       /* # bytes that variables take up */

  HOST_WIDE_INT args_size;      /* # bytes that outgoing arguments take up */

  HOST_WIDE_INT args_size;      /* # bytes that outgoing arguments take up */

  HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */

  HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */

  HOST_WIDE_INT gp_reg_size;    /* # bytes needed to store gp regs */

  HOST_WIDE_INT gp_reg_size;    /* # bytes needed to store gp regs */

  HOST_WIDE_INT fp_reg_size;    /* # bytes needed to store fp regs */

  HOST_WIDE_INT fp_reg_size;    /* # bytes needed to store fp regs */

  unsigned int mask;            /* mask of saved gp registers */

  unsigned int mask;            /* mask of saved gp registers */

  unsigned int fmask;           /* mask of saved fp registers */

  unsigned int fmask;           /* mask of saved fp registers */

  HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */

  HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */

  HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */

  HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */

  HOST_WIDE_INT gp_sp_offset;   /* offset from new sp to store gp registers */

  HOST_WIDE_INT gp_sp_offset;   /* offset from new sp to store gp registers */

  HOST_WIDE_INT fp_sp_offset;   /* offset from new sp to store fp registers */

  HOST_WIDE_INT fp_sp_offset;   /* offset from new sp to store fp registers */

  bool initialized;             /* true if frame size already calculated */

  bool initialized;             /* true if frame size already calculated */

  int num_gp;                   /* number of gp registers saved */

  int num_gp;                   /* number of gp registers saved */

  int num_fp;                   /* number of fp registers saved */

  int num_fp;                   /* number of fp registers saved */

};

};

struct machine_function GTY(()) {

struct machine_function GTY(()) {

  /* Pseudo-reg holding the value of $28 in a mips16 function which

  /* Pseudo-reg holding the value of $28 in a mips16 function which

     refers to GP relative global variables.  */

     refers to GP relative global variables.  */

  rtx mips16_gp_pseudo_rtx;

  rtx mips16_gp_pseudo_rtx;

  /* The number of extra stack bytes taken up by register varargs.

  /* The number of extra stack bytes taken up by register varargs.

     This area is allocated by the callee at the very top of the frame.  */

     This area is allocated by the callee at the very top of the frame.  */

  int varargs_size;

  int varargs_size;

  /* Current frame information, calculated by compute_frame_size.  */

  /* Current frame information, calculated by compute_frame_size.  */

  struct mips_frame_info frame;

  struct mips_frame_info frame;

  /* The register to use as the global pointer within this function.  */

  /* The register to use as the global pointer within this function.  */

  unsigned int global_pointer;

  unsigned int global_pointer;

  /* True if mips_adjust_insn_length should ignore an instruction's

  /* True if mips_adjust_insn_length should ignore an instruction's

     hazard attribute.  */

     hazard attribute.  */

  bool ignore_hazard_length_p;

  bool ignore_hazard_length_p;

  /* True if the whole function is suitable for .set noreorder and

  /* True if the whole function is suitable for .set noreorder and

     .set nomacro.  */

     .set nomacro.  */

  bool all_noreorder_p;

  bool all_noreorder_p;

  /* True if the function is known to have an instruction that needs $gp.  */

  /* True if the function is known to have an instruction that needs $gp.  */

  bool has_gp_insn_p;

  bool has_gp_insn_p;

};

};

/* Information about a single argument.  */

/* Information about a single argument.  */

struct mips_arg_info

struct mips_arg_info

{

{

  /* True if the argument is passed in a floating-point register, or

  /* True if the argument is passed in a floating-point register, or

     would have been if we hadn't run out of registers.  */

     would have been if we hadn't run out of registers.  */

  bool fpr_p;

  bool fpr_p;

  /* The number of words passed in registers, rounded up.  */

  /* The number of words passed in registers, rounded up.  */

  unsigned int reg_words;

  unsigned int reg_words;

  /* For EABI, the offset of the first register from GP_ARG_FIRST or

  /* For EABI, the offset of the first register from GP_ARG_FIRST or

     FP_ARG_FIRST.  For other ABIs, the offset of the first register from

     FP_ARG_FIRST.  For other ABIs, the offset of the first register from

     the start of the ABI's argument structure (see the CUMULATIVE_ARGS

     the start of the ABI's argument structure (see the CUMULATIVE_ARGS

     comment for details).

     comment for details).

     The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely

     The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely

     on the stack.  */

     on the stack.  */

  unsigned int reg_offset;

  unsigned int reg_offset;

  /* The number of words that must be passed on the stack, rounded up.  */

  /* The number of words that must be passed on the stack, rounded up.  */

  unsigned int stack_words;

  unsigned int stack_words;

  /* The offset from the start of the stack overflow area of the argument's

  /* The offset from the start of the stack overflow area of the argument's

     first stack word.  Only meaningful when STACK_WORDS is nonzero.  */

     first stack word.  Only meaningful when STACK_WORDS is nonzero.  */

  unsigned int stack_offset;

  unsigned int stack_offset;

};

};

/* Information about an address described by mips_address_type.

/* Information about an address described by mips_address_type.

   ADDRESS_CONST_INT

   ADDRESS_CONST_INT

       No fields are used.

       No fields are used.

   ADDRESS_REG

   ADDRESS_REG

       REG is the base register and OFFSET is the constant offset.

       REG is the base register and OFFSET is the constant offset.

   ADDRESS_LO_SUM

   ADDRESS_LO_SUM

       REG is the register that contains the high part of the address,

       REG is the register that contains the high part of the address,

       OFFSET is the symbolic address being referenced and SYMBOL_TYPE

       OFFSET is the symbolic address being referenced and SYMBOL_TYPE

       is the type of OFFSET's symbol.

       is the type of OFFSET's symbol.

   ADDRESS_SYMBOLIC

   ADDRESS_SYMBOLIC

       SYMBOL_TYPE is the type of symbol being referenced.  */

       SYMBOL_TYPE is the type of symbol being referenced.  */

struct mips_address_info

struct mips_address_info

{

{

  enum mips_address_type type;

  enum mips_address_type type;

  rtx reg;

  rtx reg;

  rtx offset;

  rtx offset;

  enum mips_symbol_type symbol_type;

  enum mips_symbol_type symbol_type;

};

};

/* One stage in a constant building sequence.  These sequences have

/* One stage in a constant building sequence.  These sequences have

   the form:

   the form:

        A = VALUE[0]

        A = VALUE[0]

        A = A CODE[1] VALUE[1]

        A = A CODE[1] VALUE[1]

        A = A CODE[2] VALUE[2]

        A = A CODE[2] VALUE[2]

        ...

        ...

   where A is an accumulator, each CODE[i] is a binary rtl operation

   where A is an accumulator, each CODE[i] is a binary rtl operation

   and each VALUE[i] is a constant integer.  */

   and each VALUE[i] is a constant integer.  */

struct mips_integer_op {

struct mips_integer_op {

  enum rtx_code code;

  enum rtx_code code;

  unsigned HOST_WIDE_INT value;

  unsigned HOST_WIDE_INT value;

};

};

/* The largest number of operations needed to load an integer constant.

/* The largest number of operations needed to load an integer constant.

   The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.

   The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.

   When the lowest bit is clear, we can try, but reject a sequence with

   When the lowest bit is clear, we can try, but reject a sequence with

   an extra SLL at the end.  */

   an extra SLL at the end.  */

#define MIPS_MAX_INTEGER_OPS 7

#define MIPS_MAX_INTEGER_OPS 7

/* Global variables for machine-dependent things.  */

/* Global variables for machine-dependent things.  */

/* Threshold for data being put into the small data/bss area, instead

/* Threshold for data being put into the small data/bss area, instead

   of the normal data area.  */

   of the normal data area.  */

int mips_section_threshold = -1;

int mips_section_threshold = -1;