;; e500 SPE description
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;; e500 SPE description
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;; Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
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;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
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;; This file is part of GCC.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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(define_constants
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(define_constants
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[(SPE_ACC_REGNO 111)
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[(SPE_ACC_REGNO 111)
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(SPEFSCR_REGNO 112)
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(SPEFSCR_REGNO 112)
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(CMPDFEQ_GPR 1006)
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(CMPDFEQ_GPR 1006)
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(TSTDFEQ_GPR 1007)
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(TSTDFEQ_GPR 1007)
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(CMPDFGT_GPR 1008)
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(CMPDFGT_GPR 1008)
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(TSTDFGT_GPR 1009)
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(TSTDFGT_GPR 1009)
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(CMPDFLT_GPR 1010)
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(CMPDFLT_GPR 1010)
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(TSTDFLT_GPR 1011)
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(TSTDFLT_GPR 1011)
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(E500_CR_IOR_COMPARE 1012)
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(E500_CR_IOR_COMPARE 1012)
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])
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])
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;; Modes using a 64-bit register.
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;; Modes using a 64-bit register.
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(define_mode_macro SPE64 [DF V4HI V2SF V1DI V2SI])
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(define_mode_macro SPE64 [DF V4HI V2SF V1DI V2SI])
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(define_insn "*negsf2_gpr"
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(define_insn "*negsf2_gpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
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(neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efsneg %0,%1"
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"efsneg %0,%1"
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[(set_attr "type" "fpsimple")])
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[(set_attr "type" "fpsimple")])
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(define_insn "*abssf2_gpr"
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(define_insn "*abssf2_gpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
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(abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efsabs %0,%1"
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"efsabs %0,%1"
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[(set_attr "type" "fpsimple")])
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[(set_attr "type" "fpsimple")])
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(define_insn "*nabssf2_gpr"
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(define_insn "*nabssf2_gpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
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(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efsnabs %0,%1"
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"efsnabs %0,%1"
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[(set_attr "type" "fpsimple")])
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[(set_attr "type" "fpsimple")])
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(define_insn "*addsf3_gpr"
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(define_insn "*addsf3_gpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
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(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
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(match_operand:SF 2 "gpc_reg_operand" "r")))]
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(match_operand:SF 2 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efsadd %0,%1,%2"
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"efsadd %0,%1,%2"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "*subsf3_gpr"
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(define_insn "*subsf3_gpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
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(minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
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(match_operand:SF 2 "gpc_reg_operand" "r")))]
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(match_operand:SF 2 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efssub %0,%1,%2"
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"efssub %0,%1,%2"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "*mulsf3_gpr"
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(define_insn "*mulsf3_gpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
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(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
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(match_operand:SF 2 "gpc_reg_operand" "r")))]
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(match_operand:SF 2 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efsmul %0,%1,%2"
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"efsmul %0,%1,%2"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "*divsf3_gpr"
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(define_insn "*divsf3_gpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
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(div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
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(match_operand:SF 2 "gpc_reg_operand" "r")))]
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(match_operand:SF 2 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efsdiv %0,%1,%2"
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"efsdiv %0,%1,%2"
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[(set_attr "type" "vecfdiv")])
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[(set_attr "type" "vecfdiv")])
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;; Floating point conversion instructions.
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;; Floating point conversion instructions.
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(define_insn "fixuns_truncdfsi2"
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(define_insn "fixuns_truncdfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
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(unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"efdctuiz %0,%1"
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"efdctuiz %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "spe_extendsfdf2"
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(define_insn "spe_extendsfdf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
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(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
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(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"efdcfs %0,%1"
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"efdcfs %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "spe_fixuns_truncsfsi2"
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(define_insn "spe_fixuns_truncsfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
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(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efsctuiz %0,%1"
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"efsctuiz %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "spe_fix_truncsfsi2"
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(define_insn "spe_fix_truncsfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
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(fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efsctsiz %0,%1"
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"efsctsiz %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "spe_fix_truncdfsi2"
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(define_insn "spe_fix_truncdfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"efdctsiz %0,%1"
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"efdctsiz %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "spe_floatunssisf2"
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(define_insn "spe_floatunssisf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efscfui %0,%1"
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"efscfui %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "spe_floatunssidf2"
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(define_insn "spe_floatunssidf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
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(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"efdcfui %0,%1"
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"efdcfui %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "spe_floatsisf2"
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(define_insn "spe_floatsisf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
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(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"efscfsi %0,%1"
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"efscfsi %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "spe_floatsidf2"
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(define_insn "spe_floatsidf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
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(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
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"efdcfsi %0,%1"
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"efdcfsi %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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;; SPE SIMD instructions
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;; SPE SIMD instructions
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(define_insn "spe_evabs"
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(define_insn "spe_evabs"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
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(abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evabs %0,%1"
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"evabs %0,%1"
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[(set_attr "type" "vecsimple")
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[(set_attr "type" "vecsimple")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evandc"
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(define_insn "spe_evandc"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
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(and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
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(not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
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(not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evandc %0,%1,%2"
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"evandc %0,%1,%2"
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[(set_attr "type" "vecsimple")
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[(set_attr "type" "vecsimple")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evand"
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(define_insn "spe_evand"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
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(and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
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(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
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(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evand %0,%1,%2"
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"evand %0,%1,%2"
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[(set_attr "type" "vecsimple")
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[(set_attr "type" "vecsimple")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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;; Vector compare instructions
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;; Vector compare instructions
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(define_insn "spe_evcmpeq"
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(define_insn "spe_evcmpeq"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evcmpeq %0,%1,%2"
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"evcmpeq %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evcmpgts"
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(define_insn "spe_evcmpgts"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evcmpgts %0,%1,%2"
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"evcmpgts %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evcmpgtu"
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(define_insn "spe_evcmpgtu"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evcmpgtu %0,%1,%2"
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"evcmpgtu %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evcmplts"
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(define_insn "spe_evcmplts"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evcmplts %0,%1,%2"
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"evcmplts %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evcmpltu"
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(define_insn "spe_evcmpltu"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
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(match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evcmpltu %0,%1,%2"
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"evcmpltu %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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;; Floating point vector compare instructions
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;; Floating point vector compare instructions
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(define_insn "spe_evfscmpeq"
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(define_insn "spe_evfscmpeq"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
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(clobber (reg:SI SPEFSCR_REGNO))]
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(clobber (reg:SI SPEFSCR_REGNO))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evfscmpeq %0,%1,%2"
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"evfscmpeq %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evfscmpgt"
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(define_insn "spe_evfscmpgt"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
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(clobber (reg:SI SPEFSCR_REGNO))]
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(clobber (reg:SI SPEFSCR_REGNO))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evfscmpgt %0,%1,%2"
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"evfscmpgt %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evfscmplt"
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(define_insn "spe_evfscmplt"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
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(clobber (reg:SI SPEFSCR_REGNO))]
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(clobber (reg:SI SPEFSCR_REGNO))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evfscmplt %0,%1,%2"
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"evfscmplt %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evfststeq"
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(define_insn "spe_evfststeq"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evfststeq %0,%1,%2"
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"evfststeq %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evfststgt"
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(define_insn "spe_evfststgt"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evfststgt %0,%1,%2"
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"evfststgt %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evfststlt"
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(define_insn "spe_evfststlt"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
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(match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evfststlt %0,%1,%2"
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"evfststlt %0,%1,%2"
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[(set_attr "type" "veccmp")
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[(set_attr "type" "veccmp")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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;; End of vector compare instructions
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;; End of vector compare instructions
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(define_insn "spe_evcntlsw"
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(define_insn "spe_evcntlsw"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
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(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evcntlsw %0,%1"
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"evcntlsw %0,%1"
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[(set_attr "type" "vecsimple")
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[(set_attr "type" "vecsimple")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evcntlzw"
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(define_insn "spe_evcntlzw"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
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(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evcntlzw %0,%1"
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"evcntlzw %0,%1"
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[(set_attr "type" "vecsimple")
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[(set_attr "type" "vecsimple")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_eveqv"
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(define_insn "spe_eveqv"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
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(not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
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(match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
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(match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
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"TARGET_SPE"
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"TARGET_SPE"
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"eveqv %0,%1,%2"
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"eveqv %0,%1,%2"
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[(set_attr "type" "vecsimple")
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[(set_attr "type" "vecsimple")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evextsb"
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(define_insn "spe_evextsb"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
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(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evextsb %0,%1"
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"evextsb %0,%1"
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[(set_attr "type" "vecsimple")
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[(set_attr "type" "vecsimple")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evextsh"
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(define_insn "spe_evextsh"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
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(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
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"TARGET_SPE"
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"TARGET_SPE"
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"evextsh %0,%1"
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"evextsh %0,%1"
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[(set_attr "type" "vecsimple")
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[(set_attr "type" "vecsimple")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evlhhesplat"
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(define_insn "spe_evlhhesplat"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand:QI 2 "immediate_operand" "i"))))
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(match_operand:QI 2 "immediate_operand" "i"))))
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(unspec [(const_int 0)] 509)]
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(unspec [(const_int 0)] 509)]
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"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
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"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
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"evlhhesplat %0,%2*2(%1)"
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"evlhhesplat %0,%2*2(%1)"
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[(set_attr "type" "vecload")
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[(set_attr "type" "vecload")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evlhhesplatx"
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(define_insn "spe_evlhhesplatx"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand:SI 2 "gpc_reg_operand" "r"))))
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(match_operand:SI 2 "gpc_reg_operand" "r"))))
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(unspec [(const_int 0)] 510)]
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(unspec [(const_int 0)] 510)]
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"TARGET_SPE"
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"TARGET_SPE"
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"evlhhesplatx %0,%1,%2"
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"evlhhesplatx %0,%1,%2"
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[(set_attr "type" "vecload")
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[(set_attr "type" "vecload")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evlhhossplat"
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(define_insn "spe_evlhhossplat"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand:QI 2 "immediate_operand" "i"))))
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(match_operand:QI 2 "immediate_operand" "i"))))
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(unspec [(const_int 0)] 511)]
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(unspec [(const_int 0)] 511)]
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"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
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"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
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"evlhhossplat %0,%2*2(%1)"
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"evlhhossplat %0,%2*2(%1)"
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[(set_attr "type" "vecload")
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[(set_attr "type" "vecload")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evlhhossplatx"
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(define_insn "spe_evlhhossplatx"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand:SI 2 "gpc_reg_operand" "r"))))
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(match_operand:SI 2 "gpc_reg_operand" "r"))))
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(unspec [(const_int 0)] 512)]
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(unspec [(const_int 0)] 512)]
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"TARGET_SPE"
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"TARGET_SPE"
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"evlhhossplatx %0,%1,%2"
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"evlhhossplatx %0,%1,%2"
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[(set_attr "type" "vecload")
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[(set_attr "type" "vecload")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evlhhousplat"
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(define_insn "spe_evlhhousplat"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand:QI 2 "immediate_operand" "i"))))
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(match_operand:QI 2 "immediate_operand" "i"))))
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(unspec [(const_int 0)] 513)]
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(unspec [(const_int 0)] 513)]
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"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
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"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
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"evlhhousplat %0,%2*2(%1)"
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"evlhhousplat %0,%2*2(%1)"
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[(set_attr "type" "vecload")
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[(set_attr "type" "vecload")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evlhhousplatx"
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(define_insn "spe_evlhhousplatx"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(match_operand:SI 2 "gpc_reg_operand" "r"))))
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(match_operand:SI 2 "gpc_reg_operand" "r"))))
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(unspec [(const_int 0)] 514)]
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(unspec [(const_int 0)] 514)]
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"TARGET_SPE"
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"TARGET_SPE"
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"evlhhousplatx %0,%1,%2"
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"evlhhousplatx %0,%1,%2"
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[(set_attr "type" "vecload")
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[(set_attr "type" "vecload")
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(set_attr "length" "4")])
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(set_attr "length" "4")])
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(define_insn "spe_evlwhsplat"
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(define_insn "spe_evlwhsplat"
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:QI 2 "immediate_operand" "i"))))
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(match_operand:QI 2 "immediate_operand" "i"))))
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(unspec [(const_int 0)] 515)]
|
(unspec [(const_int 0)] 515)]
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"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
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"evlwhsplat %0,%2*4(%1)"
|
"evlwhsplat %0,%2*4(%1)"
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[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
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(define_insn "spe_evlwhsplatx"
|
(define_insn "spe_evlwhsplatx"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(unspec [(const_int 0)] 516)]
|
(unspec [(const_int 0)] 516)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evlwhsplatx %0,%1,%2"
|
"evlwhsplatx %0,%1,%2"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evlwwsplat"
|
(define_insn "spe_evlwwsplat"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(unspec [(const_int 0)] 517)]
|
(unspec [(const_int 0)] 517)]
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"evlwwsplat %0,%2*4(%1)"
|
"evlwwsplat %0,%2*4(%1)"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evlwwsplatx"
|
(define_insn "spe_evlwwsplatx"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(unspec [(const_int 0)] 518)]
|
(unspec [(const_int 0)] 518)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evlwwsplatx %0,%1,%2"
|
"evlwwsplatx %0,%1,%2"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmergehi"
|
(define_insn "spe_evmergehi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(vec_select:V2SI
|
(vec_select:V2SI
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(parallel [(const_int 1)
|
(parallel [(const_int 1)
|
(const_int 0)]))
|
(const_int 0)]))
|
(const_int 2)))]
|
(const_int 2)))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmergehi %0,%1,%2"
|
"evmergehi %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmergehilo"
|
(define_insn "spe_evmergehilo"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(const_int 2)))]
|
(const_int 2)))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmergehilo %0,%1,%2"
|
"evmergehilo %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmergelo"
|
(define_insn "spe_evmergelo"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(vec_merge:V2SI (vec_select:V2SI
|
(vec_merge:V2SI (vec_select:V2SI
|
(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(parallel [(const_int 1)
|
(parallel [(const_int 1)
|
(const_int 0)]))
|
(const_int 0)]))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(const_int 2)))]
|
(const_int 2)))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmergelo %0,%1,%2"
|
"evmergelo %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmergelohi"
|
(define_insn "spe_evmergelohi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(vec_merge:V2SI (vec_select:V2SI
|
(vec_merge:V2SI (vec_select:V2SI
|
(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(parallel [(const_int 1)
|
(parallel [(const_int 1)
|
(const_int 0)]))
|
(const_int 0)]))
|
(vec_select:V2SI
|
(vec_select:V2SI
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(parallel [(const_int 1)
|
(parallel [(const_int 1)
|
(const_int 0)]))
|
(const_int 0)]))
|
(const_int 2)))]
|
(const_int 2)))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmergelohi %0,%1,%2"
|
"evmergelohi %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evnand"
|
(define_insn "spe_evnand"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evnand %0,%1,%2"
|
"evnand %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "negv2si2"
|
(define_insn "negv2si2"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
|
(neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evneg %0,%1"
|
"evneg %0,%1"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evnor"
|
(define_insn "spe_evnor"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evnor %0,%1,%2"
|
"evnor %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evorc"
|
(define_insn "spe_evorc"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
|
(not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evorc %0,%1,%2"
|
"evorc %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evor"
|
(define_insn "spe_evor"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evor %0,%1,%2"
|
"evor %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evrlwi"
|
(define_insn "spe_evrlwi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")] 519))]
|
(match_operand:QI 2 "immediate_operand" "i")] 519))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evrlwi %0,%1,%2"
|
"evrlwi %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evrlw"
|
(define_insn "spe_evrlw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evrlw %0,%1,%2"
|
"evrlw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evrndw"
|
(define_insn "spe_evrndw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evrndw %0,%1"
|
"evrndw %0,%1"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsel"
|
(define_insn "spe_evsel"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:CC 3 "cc_reg_operand" "y")] 522))]
|
(match_operand:CC 3 "cc_reg_operand" "y")] 522))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsel %0,%1,%2,%3"
|
"evsel %0,%1,%2,%3"
|
[(set_attr "type" "veccmp")
|
[(set_attr "type" "veccmp")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsel_fs"
|
(define_insn "spe_evsel_fs"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")
|
(match_operand:CC 3 "cc_reg_operand" "y")] 725))]
|
(match_operand:CC 3 "cc_reg_operand" "y")] 725))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsel %0,%1,%2,%3"
|
"evsel %0,%1,%2,%3"
|
[(set_attr "type" "veccmp")
|
[(set_attr "type" "veccmp")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evslwi"
|
(define_insn "spe_evslwi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")]
|
(match_operand:QI 2 "immediate_operand" "i")]
|
523))]
|
523))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evslwi %0,%1,%2"
|
"evslwi %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evslw"
|
(define_insn "spe_evslw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evslw %0,%1,%2"
|
"evslw %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsrwis"
|
(define_insn "spe_evsrwis"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")]
|
(match_operand:QI 2 "immediate_operand" "i")]
|
525))]
|
525))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsrwis %0,%1,%2"
|
"evsrwis %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsrwiu"
|
(define_insn "spe_evsrwiu"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")]
|
(match_operand:QI 2 "immediate_operand" "i")]
|
526))]
|
526))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsrwiu %0,%1,%2"
|
"evsrwiu %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsrws"
|
(define_insn "spe_evsrws"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsrws %0,%1,%2"
|
"evsrws %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsrwu"
|
(define_insn "spe_evsrwu"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsrwu %0,%1,%2"
|
"evsrwu %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
;; vector xors
|
;; vector xors
|
|
|
(define_insn "xorv2si3"
|
(define_insn "xorv2si3"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evxor %0,%1,%2"
|
"evxor %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "xorv4hi3"
|
(define_insn "xorv4hi3"
|
[(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
|
(xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
|
(xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
|
(match_operand:V4HI 2 "gpc_reg_operand" "r")))]
|
(match_operand:V4HI 2 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evxor %0,%1,%2"
|
"evxor %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "xorv1di3"
|
(define_insn "xorv1di3"
|
[(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
|
(xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
|
(xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
|
(match_operand:V1DI 2 "gpc_reg_operand" "r")))]
|
(match_operand:V1DI 2 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evxor %0,%1,%2"
|
"evxor %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
;; end of vector xors
|
;; end of vector xors
|
|
|
(define_insn "spe_evfsabs"
|
(define_insn "spe_evfsabs"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
|
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsabs %0,%1"
|
"evfsabs %0,%1"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsadd"
|
(define_insn "spe_evfsadd"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")))
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsadd %0,%1,%2"
|
"evfsadd %0,%1,%2"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfscfsf"
|
(define_insn "spe_evfscfsf"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfscfsf %0,%1"
|
"evfscfsf %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfscfsi"
|
(define_insn "spe_evfscfsi"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
|
(float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfscfsi %0,%1"
|
"evfscfsi %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfscfuf"
|
(define_insn "spe_evfscfuf"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfscfuf %0,%1"
|
"evfscfuf %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfscfui"
|
(define_insn "spe_evfscfui"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
|
(unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfscfui %0,%1"
|
"evfscfui %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsctsf"
|
(define_insn "spe_evfsctsf"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsctsf %0,%1"
|
"evfsctsf %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsctsi"
|
(define_insn "spe_evfsctsi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
|
(unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsctsi %0,%1"
|
"evfsctsi %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsctsiz"
|
(define_insn "spe_evfsctsiz"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
|
(unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsctsiz %0,%1"
|
"evfsctsiz %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsctuf"
|
(define_insn "spe_evfsctuf"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsctuf %0,%1"
|
"evfsctuf %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsctui"
|
(define_insn "spe_evfsctui"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
|
(unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsctui %0,%1"
|
"evfsctui %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsctuiz"
|
(define_insn "spe_evfsctuiz"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
|
(unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsctuiz %0,%1"
|
"evfsctuiz %0,%1"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsdiv"
|
(define_insn "spe_evfsdiv"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")))
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsdiv %0,%1,%2"
|
"evfsdiv %0,%1,%2"
|
[(set_attr "type" "vecfdiv")
|
[(set_attr "type" "vecfdiv")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsmul"
|
(define_insn "spe_evfsmul"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")))
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsmul %0,%1,%2"
|
"evfsmul %0,%1,%2"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsnabs"
|
(define_insn "spe_evfsnabs"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
|
(unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsnabs %0,%1"
|
"evfsnabs %0,%1"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfsneg"
|
(define_insn "spe_evfsneg"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
|
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfsneg %0,%1"
|
"evfsneg %0,%1"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evfssub"
|
(define_insn "spe_evfssub"
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
|
(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")))
|
(match_operand:V2SF 2 "gpc_reg_operand" "r")))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evfssub %0,%1,%2"
|
"evfssub %0,%1,%2"
|
[(set_attr "type" "vecfloat")
|
[(set_attr "type" "vecfloat")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
;; SPE SIMD load instructions.
|
;; SPE SIMD load instructions.
|
|
|
;; Only the hardware engineer who designed the SPE understands the
|
;; Only the hardware engineer who designed the SPE understands the
|
;; plethora of load and store instructions ;-). We have no way of
|
;; plethora of load and store instructions ;-). We have no way of
|
;; differentiating between them with RTL so use an unspec of const_int 0
|
;; differentiating between them with RTL so use an unspec of const_int 0
|
;; to avoid identical RTL.
|
;; to avoid identical RTL.
|
|
|
(define_insn "spe_evldd"
|
(define_insn "spe_evldd"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(unspec [(const_int 0)] 544)]
|
(unspec [(const_int 0)] 544)]
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"evldd %0,%2*8(%1)"
|
"evldd %0,%2*8(%1)"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evlddx"
|
(define_insn "spe_evlddx"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(unspec [(const_int 0)] 545)]
|
(unspec [(const_int 0)] 545)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evlddx %0,%1,%2"
|
"evlddx %0,%1,%2"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evldh"
|
(define_insn "spe_evldh"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(unspec [(const_int 0)] 546)]
|
(unspec [(const_int 0)] 546)]
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"evldh %0,%2*8(%1)"
|
"evldh %0,%2*8(%1)"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evldhx"
|
(define_insn "spe_evldhx"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(unspec [(const_int 0)] 547)]
|
(unspec [(const_int 0)] 547)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evldhx %0,%1,%2"
|
"evldhx %0,%1,%2"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evldw"
|
(define_insn "spe_evldw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(unspec [(const_int 0)] 548)]
|
(unspec [(const_int 0)] 548)]
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"evldw %0,%2*8(%1)"
|
"evldw %0,%2*8(%1)"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evldwx"
|
(define_insn "spe_evldwx"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(unspec [(const_int 0)] 549)]
|
(unspec [(const_int 0)] 549)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evldwx %0,%1,%2"
|
"evldwx %0,%1,%2"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evlwhe"
|
(define_insn "spe_evlwhe"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(unspec [(const_int 0)] 550)]
|
(unspec [(const_int 0)] 550)]
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"evlwhe %0,%2*4(%1)"
|
"evlwhe %0,%2*4(%1)"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evlwhex"
|
(define_insn "spe_evlwhex"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(unspec [(const_int 0)] 551)]
|
(unspec [(const_int 0)] 551)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evlwhex %0,%1,%2"
|
"evlwhex %0,%1,%2"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evlwhos"
|
(define_insn "spe_evlwhos"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(unspec [(const_int 0)] 552)]
|
(unspec [(const_int 0)] 552)]
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"evlwhos %0,%2*4(%1)"
|
"evlwhos %0,%2*4(%1)"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evlwhosx"
|
(define_insn "spe_evlwhosx"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(unspec [(const_int 0)] 553)]
|
(unspec [(const_int 0)] 553)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evlwhosx %0,%1,%2"
|
"evlwhosx %0,%1,%2"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evlwhou"
|
(define_insn "spe_evlwhou"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(match_operand:QI 2 "immediate_operand" "i"))))
|
(unspec [(const_int 0)] 554)]
|
(unspec [(const_int 0)] 554)]
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
|
"evlwhou %0,%2*4(%1)"
|
"evlwhou %0,%2*4(%1)"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evlwhoux"
|
(define_insn "spe_evlwhoux"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(match_operand:SI 2 "gpc_reg_operand" "r"))))
|
(unspec [(const_int 0)] 555)]
|
(unspec [(const_int 0)] 555)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evlwhoux %0,%1,%2"
|
"evlwhoux %0,%1,%2"
|
[(set_attr "type" "vecload")
|
[(set_attr "type" "vecload")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_brinc"
|
(define_insn "spe_brinc"
|
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
(unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
|
(unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
|
(match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
|
(match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"brinc %0,%1,%2"
|
"brinc %0,%1,%2"
|
[(set_attr "type" "brinc")
|
[(set_attr "type" "brinc")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhegsmfaa"
|
(define_insn "spe_evmhegsmfaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 557))
|
(reg:V2SI SPE_ACC_REGNO)] 557))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhegsmfaa %0,%1,%2"
|
"evmhegsmfaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhegsmfan"
|
(define_insn "spe_evmhegsmfan"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 558))
|
(reg:V2SI SPE_ACC_REGNO)] 558))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhegsmfan %0,%1,%2"
|
"evmhegsmfan %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhegsmiaa"
|
(define_insn "spe_evmhegsmiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 559))
|
(reg:V2SI SPE_ACC_REGNO)] 559))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhegsmiaa %0,%1,%2"
|
"evmhegsmiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhegsmian"
|
(define_insn "spe_evmhegsmian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 560))
|
(reg:V2SI SPE_ACC_REGNO)] 560))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhegsmian %0,%1,%2"
|
"evmhegsmian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhegumiaa"
|
(define_insn "spe_evmhegumiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 561))
|
(reg:V2SI SPE_ACC_REGNO)] 561))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhegumiaa %0,%1,%2"
|
"evmhegumiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhegumian"
|
(define_insn "spe_evmhegumian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 562))
|
(reg:V2SI SPE_ACC_REGNO)] 562))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhegumian %0,%1,%2"
|
"evmhegumian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhesmfaaw"
|
(define_insn "spe_evmhesmfaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 563))
|
(reg:V2SI SPE_ACC_REGNO)] 563))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhesmfaaw %0,%1,%2"
|
"evmhesmfaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhesmfanw"
|
(define_insn "spe_evmhesmfanw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 564))
|
(reg:V2SI SPE_ACC_REGNO)] 564))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhesmfanw %0,%1,%2"
|
"evmhesmfanw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhesmfa"
|
(define_insn "spe_evmhesmfa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhesmfa %0,%1,%2"
|
"evmhesmfa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhesmf"
|
(define_insn "spe_evmhesmf"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhesmf %0,%1,%2"
|
"evmhesmf %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhesmiaaw"
|
(define_insn "spe_evmhesmiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 567))
|
(reg:V2SI SPE_ACC_REGNO)] 567))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhesmiaaw %0,%1,%2"
|
"evmhesmiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhesmianw"
|
(define_insn "spe_evmhesmianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 568))
|
(reg:V2SI SPE_ACC_REGNO)] 568))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhesmianw %0,%1,%2"
|
"evmhesmianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhesmia"
|
(define_insn "spe_evmhesmia"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhesmia %0,%1,%2"
|
"evmhesmia %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhesmi"
|
(define_insn "spe_evmhesmi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhesmi %0,%1,%2"
|
"evmhesmi %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhessfaaw"
|
(define_insn "spe_evmhessfaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 571))
|
(reg:V2SI SPE_ACC_REGNO)] 571))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhessfaaw %0,%1,%2"
|
"evmhessfaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhessfanw"
|
(define_insn "spe_evmhessfanw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 572))
|
(reg:V2SI SPE_ACC_REGNO)] 572))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhessfanw %0,%1,%2"
|
"evmhessfanw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhessfa"
|
(define_insn "spe_evmhessfa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhessfa %0,%1,%2"
|
"evmhessfa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhessf"
|
(define_insn "spe_evmhessf"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhessf %0,%1,%2"
|
"evmhessf %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhessiaaw"
|
(define_insn "spe_evmhessiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 575))
|
(reg:V2SI SPE_ACC_REGNO)] 575))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhessiaaw %0,%1,%2"
|
"evmhessiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhessianw"
|
(define_insn "spe_evmhessianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 576))
|
(reg:V2SI SPE_ACC_REGNO)] 576))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhessianw %0,%1,%2"
|
"evmhessianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmheumiaaw"
|
(define_insn "spe_evmheumiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 577))
|
(reg:V2SI SPE_ACC_REGNO)] 577))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmheumiaaw %0,%1,%2"
|
"evmheumiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmheumianw"
|
(define_insn "spe_evmheumianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 578))
|
(reg:V2SI SPE_ACC_REGNO)] 578))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmheumianw %0,%1,%2"
|
"evmheumianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmheumia"
|
(define_insn "spe_evmheumia"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmheumia %0,%1,%2"
|
"evmheumia %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmheumi"
|
(define_insn "spe_evmheumi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmheumi %0,%1,%2"
|
"evmheumi %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmheusiaaw"
|
(define_insn "spe_evmheusiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 581))
|
(reg:V2SI SPE_ACC_REGNO)] 581))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmheusiaaw %0,%1,%2"
|
"evmheusiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmheusianw"
|
(define_insn "spe_evmheusianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 582))
|
(reg:V2SI SPE_ACC_REGNO)] 582))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmheusianw %0,%1,%2"
|
"evmheusianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhogsmfaa"
|
(define_insn "spe_evmhogsmfaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 583))
|
(reg:V2SI SPE_ACC_REGNO)] 583))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhogsmfaa %0,%1,%2"
|
"evmhogsmfaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhogsmfan"
|
(define_insn "spe_evmhogsmfan"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 584))
|
(reg:V2SI SPE_ACC_REGNO)] 584))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhogsmfan %0,%1,%2"
|
"evmhogsmfan %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhogsmiaa"
|
(define_insn "spe_evmhogsmiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 585))
|
(reg:V2SI SPE_ACC_REGNO)] 585))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhogsmiaa %0,%1,%2"
|
"evmhogsmiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhogsmian"
|
(define_insn "spe_evmhogsmian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 586))
|
(reg:V2SI SPE_ACC_REGNO)] 586))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhogsmian %0,%1,%2"
|
"evmhogsmian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhogumiaa"
|
(define_insn "spe_evmhogumiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 587))
|
(reg:V2SI SPE_ACC_REGNO)] 587))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhogumiaa %0,%1,%2"
|
"evmhogumiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhogumian"
|
(define_insn "spe_evmhogumian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 588))
|
(reg:V2SI SPE_ACC_REGNO)] 588))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhogumian %0,%1,%2"
|
"evmhogumian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhosmfaaw"
|
(define_insn "spe_evmhosmfaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 589))
|
(reg:V2SI SPE_ACC_REGNO)] 589))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhosmfaaw %0,%1,%2"
|
"evmhosmfaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhosmfanw"
|
(define_insn "spe_evmhosmfanw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 590))
|
(reg:V2SI SPE_ACC_REGNO)] 590))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhosmfanw %0,%1,%2"
|
"evmhosmfanw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhosmfa"
|
(define_insn "spe_evmhosmfa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhosmfa %0,%1,%2"
|
"evmhosmfa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhosmf"
|
(define_insn "spe_evmhosmf"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhosmf %0,%1,%2"
|
"evmhosmf %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhosmiaaw"
|
(define_insn "spe_evmhosmiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 593))
|
(reg:V2SI SPE_ACC_REGNO)] 593))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhosmiaaw %0,%1,%2"
|
"evmhosmiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhosmianw"
|
(define_insn "spe_evmhosmianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 594))
|
(reg:V2SI SPE_ACC_REGNO)] 594))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhosmianw %0,%1,%2"
|
"evmhosmianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhosmia"
|
(define_insn "spe_evmhosmia"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhosmia %0,%1,%2"
|
"evmhosmia %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhosmi"
|
(define_insn "spe_evmhosmi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhosmi %0,%1,%2"
|
"evmhosmi %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhossfaaw"
|
(define_insn "spe_evmhossfaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 597))
|
(reg:V2SI SPE_ACC_REGNO)] 597))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhossfaaw %0,%1,%2"
|
"evmhossfaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhossfanw"
|
(define_insn "spe_evmhossfanw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 598))
|
(reg:V2SI SPE_ACC_REGNO)] 598))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhossfanw %0,%1,%2"
|
"evmhossfanw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhossfa"
|
(define_insn "spe_evmhossfa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 599))
|
(reg:V2SI SPE_ACC_REGNO)] 599))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhossfa %0,%1,%2"
|
"evmhossfa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhossf"
|
(define_insn "spe_evmhossf"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhossf %0,%1,%2"
|
"evmhossf %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhossiaaw"
|
(define_insn "spe_evmhossiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 601))
|
(reg:V2SI SPE_ACC_REGNO)] 601))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhossiaaw %0,%1,%2"
|
"evmhossiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhossianw"
|
(define_insn "spe_evmhossianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 602))
|
(reg:V2SI SPE_ACC_REGNO)] 602))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhossianw %0,%1,%2"
|
"evmhossianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhoumiaaw"
|
(define_insn "spe_evmhoumiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 603))
|
(reg:V2SI SPE_ACC_REGNO)] 603))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhoumiaaw %0,%1,%2"
|
"evmhoumiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhoumianw"
|
(define_insn "spe_evmhoumianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 604))
|
(reg:V2SI SPE_ACC_REGNO)] 604))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhoumianw %0,%1,%2"
|
"evmhoumianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhoumia"
|
(define_insn "spe_evmhoumia"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhoumia %0,%1,%2"
|
"evmhoumia %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhoumi"
|
(define_insn "spe_evmhoumi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhoumi %0,%1,%2"
|
"evmhoumi %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhousiaaw"
|
(define_insn "spe_evmhousiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 607))
|
(reg:V2SI SPE_ACC_REGNO)] 607))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhousiaaw %0,%1,%2"
|
"evmhousiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmhousianw"
|
(define_insn "spe_evmhousianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 608))
|
(reg:V2SI SPE_ACC_REGNO)] 608))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmhousianw %0,%1,%2"
|
"evmhousianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmmlssfa"
|
(define_insn "spe_evmmlssfa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmmlssfa %0,%1,%2"
|
"evmmlssfa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmmlssf"
|
(define_insn "spe_evmmlssf"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmmlssf %0,%1,%2"
|
"evmmlssf %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhsmfa"
|
(define_insn "spe_evmwhsmfa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhsmfa %0,%1,%2"
|
"evmwhsmfa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhsmf"
|
(define_insn "spe_evmwhsmf"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhsmf %0,%1,%2"
|
"evmwhsmf %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhsmia"
|
(define_insn "spe_evmwhsmia"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhsmia %0,%1,%2"
|
"evmwhsmia %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhsmi"
|
(define_insn "spe_evmwhsmi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhsmi %0,%1,%2"
|
"evmwhsmi %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhssfa"
|
(define_insn "spe_evmwhssfa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhssfa %0,%1,%2"
|
"evmwhssfa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhusian"
|
(define_insn "spe_evmwhusian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhusian %0,%1,%2"
|
"evmwhusian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhssf"
|
(define_insn "spe_evmwhssf"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhssf %0,%1,%2"
|
"evmwhssf %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhumia"
|
(define_insn "spe_evmwhumia"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhumia %0,%1,%2"
|
"evmwhumia %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhumi"
|
(define_insn "spe_evmwhumi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhumi %0,%1,%2"
|
"evmwhumi %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlsmiaaw"
|
(define_insn "spe_evmwlsmiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 635))
|
(reg:V2SI SPE_ACC_REGNO)] 635))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlsmiaaw %0,%1,%2"
|
"evmwlsmiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlsmianw"
|
(define_insn "spe_evmwlsmianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 636))
|
(reg:V2SI SPE_ACC_REGNO)] 636))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlsmianw %0,%1,%2"
|
"evmwlsmianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlssiaaw"
|
(define_insn "spe_evmwlssiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 641))
|
(reg:V2SI SPE_ACC_REGNO)] 641))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlssiaaw %0,%1,%2"
|
"evmwlssiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlssianw"
|
(define_insn "spe_evmwlssianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 642))
|
(reg:V2SI SPE_ACC_REGNO)] 642))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlssianw %0,%1,%2"
|
"evmwlssianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlumiaaw"
|
(define_insn "spe_evmwlumiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 643))
|
(reg:V2SI SPE_ACC_REGNO)] 643))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlumiaaw %0,%1,%2"
|
"evmwlumiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlumianw"
|
(define_insn "spe_evmwlumianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 644))
|
(reg:V2SI SPE_ACC_REGNO)] 644))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlumianw %0,%1,%2"
|
"evmwlumianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlumia"
|
(define_insn "spe_evmwlumia"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlumia %0,%1,%2"
|
"evmwlumia %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlumi"
|
(define_insn "spe_evmwlumi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlumi %0,%1,%2"
|
"evmwlumi %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlusiaaw"
|
(define_insn "spe_evmwlusiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 647))
|
(reg:V2SI SPE_ACC_REGNO)] 647))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlusiaaw %0,%1,%2"
|
"evmwlusiaaw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwlusianw"
|
(define_insn "spe_evmwlusianw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 648))
|
(reg:V2SI SPE_ACC_REGNO)] 648))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwlusianw %0,%1,%2"
|
"evmwlusianw %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwsmfaa"
|
(define_insn "spe_evmwsmfaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 649))
|
(reg:V2SI SPE_ACC_REGNO)] 649))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwsmfaa %0,%1,%2"
|
"evmwsmfaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwsmfan"
|
(define_insn "spe_evmwsmfan"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 650))
|
(reg:V2SI SPE_ACC_REGNO)] 650))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwsmfan %0,%1,%2"
|
"evmwsmfan %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwsmfa"
|
(define_insn "spe_evmwsmfa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwsmfa %0,%1,%2"
|
"evmwsmfa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwsmf"
|
(define_insn "spe_evmwsmf"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwsmf %0,%1,%2"
|
"evmwsmf %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwsmiaa"
|
(define_insn "spe_evmwsmiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 653))
|
(reg:V2SI SPE_ACC_REGNO)] 653))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwsmiaa %0,%1,%2"
|
"evmwsmiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwsmian"
|
(define_insn "spe_evmwsmian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 654))
|
(reg:V2SI SPE_ACC_REGNO)] 654))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwsmian %0,%1,%2"
|
"evmwsmian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwsmia"
|
(define_insn "spe_evmwsmia"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwsmia %0,%1,%2"
|
"evmwsmia %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwsmi"
|
(define_insn "spe_evmwsmi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwsmi %0,%1,%2"
|
"evmwsmi %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwssfaa"
|
(define_insn "spe_evmwssfaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 657))
|
(reg:V2SI SPE_ACC_REGNO)] 657))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwssfaa %0,%1,%2"
|
"evmwssfaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwssfan"
|
(define_insn "spe_evmwssfan"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 658))
|
(reg:V2SI SPE_ACC_REGNO)] 658))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwssfan %0,%1,%2"
|
"evmwssfan %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwssfa"
|
(define_insn "spe_evmwssfa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwssfa %0,%1,%2"
|
"evmwssfa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwssf"
|
(define_insn "spe_evmwssf"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwssf %0,%1,%2"
|
"evmwssf %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwumiaa"
|
(define_insn "spe_evmwumiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 661))
|
(reg:V2SI SPE_ACC_REGNO)] 661))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwumiaa %0,%1,%2"
|
"evmwumiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwumian"
|
(define_insn "spe_evmwumian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 662))
|
(reg:V2SI SPE_ACC_REGNO)] 662))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwumian %0,%1,%2"
|
"evmwumian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwumia"
|
(define_insn "spe_evmwumia"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwumia %0,%1,%2"
|
"evmwumia %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwumi"
|
(define_insn "spe_evmwumi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwumi %0,%1,%2"
|
"evmwumi %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evaddw"
|
(define_insn "spe_evaddw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evaddw %0,%1,%2"
|
"evaddw %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evaddusiaaw"
|
(define_insn "spe_evaddusiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 673))
|
(reg:V2SI SPE_ACC_REGNO)] 673))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evaddusiaaw %0,%1"
|
"evaddusiaaw %0,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evaddumiaaw"
|
(define_insn "spe_evaddumiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 674))
|
(reg:V2SI SPE_ACC_REGNO)] 674))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evaddumiaaw %0,%1"
|
"evaddumiaaw %0,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evaddssiaaw"
|
(define_insn "spe_evaddssiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 675))
|
(reg:V2SI SPE_ACC_REGNO)] 675))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evaddssiaaw %0,%1"
|
"evaddssiaaw %0,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evaddsmiaaw"
|
(define_insn "spe_evaddsmiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 676))
|
(reg:V2SI SPE_ACC_REGNO)] 676))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evaddsmiaaw %0,%1"
|
"evaddsmiaaw %0,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evaddiw"
|
(define_insn "spe_evaddiw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")] 677))]
|
(match_operand:QI 2 "immediate_operand" "i")] 677))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evaddiw %0,%1,%2"
|
"evaddiw %0,%1,%2"
|
[(set_attr "type" "vecsimple")
|
[(set_attr "type" "vecsimple")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsubifw"
|
(define_insn "spe_evsubifw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:QI 2 "immediate_operand" "i")] 678))]
|
(match_operand:QI 2 "immediate_operand" "i")] 678))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsubifw %0,%2,%1"
|
"evsubifw %0,%2,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsubfw"
|
(define_insn "spe_evsubfw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsubfw %0,%2,%1"
|
"evsubfw %0,%2,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsubfusiaaw"
|
(define_insn "spe_evsubfusiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 679))
|
(reg:V2SI SPE_ACC_REGNO)] 679))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsubfusiaaw %0,%1"
|
"evsubfusiaaw %0,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsubfumiaaw"
|
(define_insn "spe_evsubfumiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 680))
|
(reg:V2SI SPE_ACC_REGNO)] 680))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsubfumiaaw %0,%1"
|
"evsubfumiaaw %0,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsubfssiaaw"
|
(define_insn "spe_evsubfssiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 681))
|
(reg:V2SI SPE_ACC_REGNO)] 681))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsubfssiaaw %0,%1"
|
"evsubfssiaaw %0,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsubfsmiaaw"
|
(define_insn "spe_evsubfsmiaaw"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(reg:V2SI SPE_ACC_REGNO)] 682))
|
(reg:V2SI SPE_ACC_REGNO)] 682))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsubfsmiaaw %0,%1"
|
"evsubfsmiaaw %0,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmra"
|
(define_insn "spe_evmra"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(match_operand:V2SI 1 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 1 "gpc_reg_operand" "r"))
|
(set (reg:V2SI SPE_ACC_REGNO)
|
(set (reg:V2SI SPE_ACC_REGNO)
|
(unspec:V2SI [(match_dup 1)] 726))]
|
(unspec:V2SI [(match_dup 1)] 726))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmra %0,%1"
|
"evmra %0,%1"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evdivws"
|
(define_insn "spe_evdivws"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evdivws %0,%1,%2"
|
"evdivws %0,%1,%2"
|
[(set_attr "type" "vecdiv")
|
[(set_attr "type" "vecdiv")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evdivwu"
|
(define_insn "spe_evdivwu"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")))
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
(clobber (reg:SI SPEFSCR_REGNO))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evdivwu %0,%1,%2"
|
"evdivwu %0,%1,%2"
|
[(set_attr "type" "vecdiv")
|
[(set_attr "type" "vecdiv")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsplatfi"
|
(define_insn "spe_evsplatfi"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
|
(unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsplatfi %0,%1"
|
"evsplatfi %0,%1"
|
[(set_attr "type" "vecperm")
|
[(set_attr "type" "vecperm")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evsplati"
|
(define_insn "spe_evsplati"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
|
(unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evsplati %0,%1"
|
"evsplati %0,%1"
|
[(set_attr "type" "vecperm")
|
[(set_attr "type" "vecperm")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstdd"
|
(define_insn "spe_evstdd"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 686)]
|
(unspec [(const_int 0)] 686)]
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"evstdd %2,%1*8(%0)"
|
"evstdd %2,%1*8(%0)"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstddx"
|
(define_insn "spe_evstddx"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 687)]
|
(unspec [(const_int 0)] 687)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evstddx %2,%0,%1"
|
"evstddx %2,%0,%1"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstdh"
|
(define_insn "spe_evstdh"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 688)]
|
(unspec [(const_int 0)] 688)]
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"evstdh %2,%1*8(%0)"
|
"evstdh %2,%1*8(%0)"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstdhx"
|
(define_insn "spe_evstdhx"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 689)]
|
(unspec [(const_int 0)] 689)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evstdhx %2,%0,%1"
|
"evstdhx %2,%0,%1"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstdw"
|
(define_insn "spe_evstdw"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 690)]
|
(unspec [(const_int 0)] 690)]
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"evstdw %2,%1*8(%0)"
|
"evstdw %2,%1*8(%0)"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstdwx"
|
(define_insn "spe_evstdwx"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 691)]
|
(unspec [(const_int 0)] 691)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evstdwx %2,%0,%1"
|
"evstdwx %2,%0,%1"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstwhe"
|
(define_insn "spe_evstwhe"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 692)]
|
(unspec [(const_int 0)] 692)]
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"evstwhe %2,%1*4(%0)"
|
"evstwhe %2,%1*4(%0)"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstwhex"
|
(define_insn "spe_evstwhex"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 693)]
|
(unspec [(const_int 0)] 693)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evstwhex %2,%0,%1"
|
"evstwhex %2,%0,%1"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstwho"
|
(define_insn "spe_evstwho"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 694)]
|
(unspec [(const_int 0)] 694)]
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"evstwho %2,%1*4(%0)"
|
"evstwho %2,%1*4(%0)"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstwhox"
|
(define_insn "spe_evstwhox"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 695)]
|
(unspec [(const_int 0)] 695)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evstwhox %2,%0,%1"
|
"evstwhox %2,%0,%1"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstwwe"
|
(define_insn "spe_evstwwe"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 696)]
|
(unspec [(const_int 0)] 696)]
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"evstwwe %2,%1*4(%0)"
|
"evstwwe %2,%1*4(%0)"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstwwex"
|
(define_insn "spe_evstwwex"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 697)]
|
(unspec [(const_int 0)] 697)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evstwwex %2,%0,%1"
|
"evstwwex %2,%0,%1"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstwwo"
|
(define_insn "spe_evstwwo"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:QI 1 "immediate_operand" "i")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 698)]
|
(unspec [(const_int 0)] 698)]
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
|
"evstwwo %2,%1*4(%0)"
|
"evstwwo %2,%1*4(%0)"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evstwwox"
|
(define_insn "spe_evstwwox"
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
[(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:SI 1 "gpc_reg_operand" "r")))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
|
(unspec [(const_int 0)] 699)]
|
(unspec [(const_int 0)] 699)]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evstwwox %2,%0,%1"
|
"evstwwox %2,%0,%1"
|
[(set_attr "type" "vecstore")
|
[(set_attr "type" "vecstore")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
;; Double-precision floating point instructions.
|
;; Double-precision floating point instructions.
|
|
|
;; FIXME: Add o=r option.
|
;; FIXME: Add o=r option.
|
(define_insn "*frob_df_di"
|
(define_insn "*frob_df_di"
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r")
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r")
|
(subreg:DF (match_operand:DI 1 "input_operand" "r,m") 0))]
|
(subreg:DF (match_operand:DI 1 "input_operand" "r,m") 0))]
|
"TARGET_E500_DOUBLE"
|
"TARGET_E500_DOUBLE"
|
"@
|
"@
|
evmergelo %0,%1,%L1
|
evmergelo %0,%1,%L1
|
evldd%X1 %0,%y1")
|
evldd%X1 %0,%y1")
|
|
|
(define_insn "*frob_di_df"
|
(define_insn "*frob_di_df"
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
|
(subreg:DI (match_operand:DF 1 "input_operand" "r") 0))]
|
(subreg:DI (match_operand:DF 1 "input_operand" "r") 0))]
|
"TARGET_E500_DOUBLE"
|
"TARGET_E500_DOUBLE"
|
"evmergehi %0,%1,%1\;mr %L0,%1"
|
"evmergehi %0,%1,%1\;mr %L0,%1"
|
[(set_attr "length" "8")])
|
[(set_attr "length" "8")])
|
|
|
(define_insn "*frob_di_df_2"
|
(define_insn "*frob_di_df_2"
|
[(set (subreg:DF (match_operand:DI 0 "register_operand" "=&r,r") 0)
|
[(set (subreg:DF (match_operand:DI 0 "register_operand" "=&r,r") 0)
|
(match_operand:DF 1 "input_operand" "r,m"))]
|
(match_operand:DF 1 "input_operand" "r,m"))]
|
"TARGET_E500_DOUBLE"
|
"TARGET_E500_DOUBLE"
|
"*
|
"*
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
default:
|
default:
|
gcc_unreachable ();
|
gcc_unreachable ();
|
case 0:
|
case 0:
|
return \"evmergehi %0,%1,%1\;mr %L0,%1\";
|
return \"evmergehi %0,%1,%1\;mr %L0,%1\";
|
case 1:
|
case 1:
|
/* If the address is not offsettable we need to load the whole
|
/* If the address is not offsettable we need to load the whole
|
doubleword into a 64-bit register and then copy the high word
|
doubleword into a 64-bit register and then copy the high word
|
to form the correct output layout. */
|
to form the correct output layout. */
|
if (!offsettable_nonstrict_memref_p (operands[1]))
|
if (!offsettable_nonstrict_memref_p (operands[1]))
|
return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
|
return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
|
/* If the low-address word is used in the address, we must load
|
/* If the low-address word is used in the address, we must load
|
it last. Otherwise, load it first. Note that we cannot have
|
it last. Otherwise, load it first. Note that we cannot have
|
auto-increment in that case since the address register is
|
auto-increment in that case since the address register is
|
known to be dead. */
|
known to be dead. */
|
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
|
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
|
operands[1], 0))
|
operands[1], 0))
|
return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
|
return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
|
else
|
else
|
return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
|
return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
|
}
|
}
|
}"
|
}"
|
[(set_attr "length" "8,8")])
|
[(set_attr "length" "8,8")])
|
|
|
(define_insn "*mov_si_e500_subreg0"
|
(define_insn "*mov_si_e500_subreg0"
|
[(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,&r") 0)
|
[(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,&r") 0)
|
(match_operand:SI 1 "input_operand" "r,m"))]
|
(match_operand:SI 1 "input_operand" "r,m"))]
|
"(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
|
"(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
|
"@
|
"@
|
evmergelo %0,%1,%0
|
evmergelo %0,%1,%0
|
evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0")
|
evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0")
|
|
|
;; ??? Could use evstwwe for memory stores in some cases, depending on
|
;; ??? Could use evstwwe for memory stores in some cases, depending on
|
;; the offset.
|
;; the offset.
|
(define_insn "*mov_si_e500_subreg0_2"
|
(define_insn "*mov_si_e500_subreg0_2"
|
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
|
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
|
(subreg:SI (match_operand:SPE64 1 "register_operand" "+r,&r") 0))]
|
(subreg:SI (match_operand:SPE64 1 "register_operand" "+r,&r") 0))]
|
"(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
|
"(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
|
"@
|
"@
|
evmergehi %0,%0,%1
|
evmergehi %0,%0,%1
|
evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0")
|
evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0")
|
|
|
(define_insn "*mov_si_e500_subreg4"
|
(define_insn "*mov_si_e500_subreg4"
|
[(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,r") 4)
|
[(set (subreg:SI (match_operand:SPE64 0 "register_operand" "+r,r") 4)
|
(match_operand:SI 1 "input_operand" "r,m"))]
|
(match_operand:SI 1 "input_operand" "r,m"))]
|
"(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
|
"(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
|
"@
|
"@
|
mr %0,%1
|
mr %0,%1
|
{l%U1%X1|lwz%U1%X1} %0,%1")
|
{l%U1%X1|lwz%U1%X1} %0,%1")
|
|
|
(define_insn "*mov_si_e500_subreg4_2"
|
(define_insn "*mov_si_e500_subreg4_2"
|
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
|
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
|
(subreg:SI (match_operand:SPE64 1 "register_operand" "r,r") 4))]
|
(subreg:SI (match_operand:SPE64 1 "register_operand" "r,r") 4))]
|
"(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
|
"(TARGET_E500_DOUBLE && mode == DFmode) || (TARGET_SPE && mode != DFmode)"
|
"@
|
"@
|
mr %0,%1
|
mr %0,%1
|
{st%U0%X0|stw%U0%X0} %1,%0")
|
{st%U0%X0|stw%U0%X0} %1,%0")
|
|
|
;; FIXME: Allow r=CONST0.
|
;; FIXME: Allow r=CONST0.
|
(define_insn "*movdf_e500_double"
|
(define_insn "*movdf_e500_double"
|
[(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
|
[(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
|
(match_operand:DF 1 "input_operand" "r,m,r"))]
|
(match_operand:DF 1 "input_operand" "r,m,r"))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
|
&& (gpc_reg_operand (operands[0], DFmode)
|
&& (gpc_reg_operand (operands[0], DFmode)
|
|| gpc_reg_operand (operands[1], DFmode))"
|
|| gpc_reg_operand (operands[1], DFmode))"
|
"*
|
"*
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0:
|
case 0:
|
return \"evor %0,%1,%1\";
|
return \"evor %0,%1,%1\";
|
case 1:
|
case 1:
|
return \"evldd%X1 %0,%y1\";
|
return \"evldd%X1 %0,%y1\";
|
case 2:
|
case 2:
|
return \"evstdd%X0 %1,%y0\";
|
return \"evstdd%X0 %1,%y0\";
|
default:
|
default:
|
gcc_unreachable ();
|
gcc_unreachable ();
|
}
|
}
|
}"
|
}"
|
[(set_attr "type" "*,vecload,vecstore")
|
[(set_attr "type" "*,vecload,vecstore")
|
(set_attr "length" "*,*,*")])
|
(set_attr "length" "*,*,*")])
|
|
|
(define_insn "spe_truncdfsf2"
|
(define_insn "spe_truncdfsf2"
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
|
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
|
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"efscfd %0,%1")
|
"efscfd %0,%1")
|
|
|
(define_insn "spe_absdf2"
|
(define_insn "spe_absdf2"
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
|
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"efdabs %0,%1")
|
"efdabs %0,%1")
|
|
|
(define_insn "spe_nabsdf2"
|
(define_insn "spe_nabsdf2"
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
|
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"efdnabs %0,%1")
|
"efdnabs %0,%1")
|
|
|
(define_insn "spe_negdf2"
|
(define_insn "spe_negdf2"
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
|
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"efdneg %0,%1")
|
"efdneg %0,%1")
|
|
|
(define_insn "spe_adddf3"
|
(define_insn "spe_adddf3"
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
|
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r")))]
|
(match_operand:DF 2 "gpc_reg_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"efdadd %0,%1,%2")
|
"efdadd %0,%1,%2")
|
|
|
(define_insn "spe_subdf3"
|
(define_insn "spe_subdf3"
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
|
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r")))]
|
(match_operand:DF 2 "gpc_reg_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"efdsub %0,%1,%2")
|
"efdsub %0,%1,%2")
|
|
|
(define_insn "spe_muldf3"
|
(define_insn "spe_muldf3"
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
|
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r")))]
|
(match_operand:DF 2 "gpc_reg_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"efdmul %0,%1,%2")
|
"efdmul %0,%1,%2")
|
|
|
(define_insn "spe_divdf3"
|
(define_insn "spe_divdf3"
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
|
(div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
|
(div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r")))]
|
(match_operand:DF 2 "gpc_reg_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
|
"efddiv %0,%1,%2")
|
"efddiv %0,%1,%2")
|
|
|
;; Vector move instructions.
|
;; Vector move instructions.
|
|
|
(define_expand "movv2si"
|
(define_expand "movv2si"
|
[(set (match_operand:V2SI 0 "nonimmediate_operand" "")
|
[(set (match_operand:V2SI 0 "nonimmediate_operand" "")
|
(match_operand:V2SI 1 "any_operand" ""))]
|
(match_operand:V2SI 1 "any_operand" ""))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
|
"{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
|
|
|
(define_insn "*movv2si_internal"
|
(define_insn "*movv2si_internal"
|
[(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
|
[(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
|
(match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
|
(match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
|
"TARGET_SPE
|
"TARGET_SPE
|
&& (gpc_reg_operand (operands[0], V2SImode)
|
&& (gpc_reg_operand (operands[0], V2SImode)
|
|| gpc_reg_operand (operands[1], V2SImode))"
|
|| gpc_reg_operand (operands[1], V2SImode))"
|
"*
|
"*
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"evstdd%X0 %1,%y0\";
|
case 0: return \"evstdd%X0 %1,%y0\";
|
case 1: return \"evldd%X1 %0,%y1\";
|
case 1: return \"evldd%X1 %0,%y1\";
|
case 2: return \"evor %0,%1,%1\";
|
case 2: return \"evor %0,%1,%1\";
|
case 3: return output_vec_const_move (operands);
|
case 3: return output_vec_const_move (operands);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}"
|
}"
|
[(set_attr "type" "vecload,vecstore,*,*")
|
[(set_attr "type" "vecload,vecstore,*,*")
|
(set_attr "length" "*,*,*,12")])
|
(set_attr "length" "*,*,*,12")])
|
|
|
(define_split
|
(define_split
|
[(set (match_operand:V2SI 0 "register_operand" "")
|
[(set (match_operand:V2SI 0 "register_operand" "")
|
(match_operand:V2SI 1 "zero_constant" ""))]
|
(match_operand:V2SI 1 "zero_constant" ""))]
|
"TARGET_SPE && reload_completed"
|
"TARGET_SPE && reload_completed"
|
[(set (match_dup 0)
|
[(set (match_dup 0)
|
(xor:V2SI (match_dup 0) (match_dup 0)))]
|
(xor:V2SI (match_dup 0) (match_dup 0)))]
|
"")
|
"")
|
|
|
(define_expand "movv1di"
|
(define_expand "movv1di"
|
[(set (match_operand:V1DI 0 "nonimmediate_operand" "")
|
[(set (match_operand:V1DI 0 "nonimmediate_operand" "")
|
(match_operand:V1DI 1 "any_operand" ""))]
|
(match_operand:V1DI 1 "any_operand" ""))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
|
"{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
|
|
|
(define_insn "*movv1di_internal"
|
(define_insn "*movv1di_internal"
|
[(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
|
[(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
|
(match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
|
(match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
|
"TARGET_SPE
|
"TARGET_SPE
|
&& (gpc_reg_operand (operands[0], V1DImode)
|
&& (gpc_reg_operand (operands[0], V1DImode)
|
|| gpc_reg_operand (operands[1], V1DImode))"
|
|| gpc_reg_operand (operands[1], V1DImode))"
|
"@
|
"@
|
evstdd%X0 %1,%y0
|
evstdd%X0 %1,%y0
|
evldd%X1 %0,%y1
|
evldd%X1 %0,%y1
|
evor %0,%1,%1
|
evor %0,%1,%1
|
evxor %0,%0,%0"
|
evxor %0,%0,%0"
|
[(set_attr "type" "vecload,vecstore,*,*")
|
[(set_attr "type" "vecload,vecstore,*,*")
|
(set_attr "length" "*,*,*,*")])
|
(set_attr "length" "*,*,*,*")])
|
|
|
(define_expand "movv4hi"
|
(define_expand "movv4hi"
|
[(set (match_operand:V4HI 0 "nonimmediate_operand" "")
|
[(set (match_operand:V4HI 0 "nonimmediate_operand" "")
|
(match_operand:V4HI 1 "any_operand" ""))]
|
(match_operand:V4HI 1 "any_operand" ""))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
|
"{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
|
|
|
(define_insn "*movv4hi_internal"
|
(define_insn "*movv4hi_internal"
|
[(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r")
|
[(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r")
|
(match_operand:V4HI 1 "input_operand" "r,m,r,W"))]
|
(match_operand:V4HI 1 "input_operand" "r,m,r,W"))]
|
"TARGET_SPE
|
"TARGET_SPE
|
&& (gpc_reg_operand (operands[0], V4HImode)
|
&& (gpc_reg_operand (operands[0], V4HImode)
|
|| gpc_reg_operand (operands[1], V4HImode))"
|
|| gpc_reg_operand (operands[1], V4HImode))"
|
"@
|
"@
|
evstdd%X0 %1,%y0
|
evstdd%X0 %1,%y0
|
evldd%X1 %0,%y1
|
evldd%X1 %0,%y1
|
evor %0,%1,%1
|
evor %0,%1,%1
|
evxor %0,%0,%0"
|
evxor %0,%0,%0"
|
[(set_attr "type" "vecload")])
|
[(set_attr "type" "vecload")])
|
|
|
(define_expand "movv2sf"
|
(define_expand "movv2sf"
|
[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
|
[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
|
(match_operand:V2SF 1 "any_operand" ""))]
|
(match_operand:V2SF 1 "any_operand" ""))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
|
"{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
|
|
|
(define_insn "*movv2sf_internal"
|
(define_insn "*movv2sf_internal"
|
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
|
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
|
(match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
|
(match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
|
"TARGET_SPE
|
"TARGET_SPE
|
&& (gpc_reg_operand (operands[0], V2SFmode)
|
&& (gpc_reg_operand (operands[0], V2SFmode)
|
|| gpc_reg_operand (operands[1], V2SFmode))"
|
|| gpc_reg_operand (operands[1], V2SFmode))"
|
"@
|
"@
|
evstdd%X0 %1,%y0
|
evstdd%X0 %1,%y0
|
evldd%X1 %0,%y1
|
evldd%X1 %0,%y1
|
evor %0,%1,%1
|
evor %0,%1,%1
|
evxor %0,%0,%0"
|
evxor %0,%0,%0"
|
[(set_attr "type" "vecload,vecstore,*,*")
|
[(set_attr "type" "vecload,vecstore,*,*")
|
(set_attr "length" "*,*,*,*")])
|
(set_attr "length" "*,*,*,*")])
|
|
|
;; End of vector move instructions.
|
;; End of vector move instructions.
|
|
|
(define_insn "spe_evmwhssfaa"
|
(define_insn "spe_evmwhssfaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhssfaa %0,%1,%2"
|
"evmwhssfaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhssmaa"
|
(define_insn "spe_evmwhssmaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhssmaa %0,%1,%2"
|
"evmwhssmaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhsmfaa"
|
(define_insn "spe_evmwhsmfaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhsmfaa %0,%1,%2"
|
"evmwhsmfaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhsmiaa"
|
(define_insn "spe_evmwhsmiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhsmiaa %0,%1,%2"
|
"evmwhsmiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhusiaa"
|
(define_insn "spe_evmwhusiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhusiaa %0,%1,%2"
|
"evmwhusiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhumiaa"
|
(define_insn "spe_evmwhumiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhumiaa %0,%1,%2"
|
"evmwhumiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhssfan"
|
(define_insn "spe_evmwhssfan"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhssfan %0,%1,%2"
|
"evmwhssfan %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhssian"
|
(define_insn "spe_evmwhssian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhssian %0,%1,%2"
|
"evmwhssian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhsmfan"
|
(define_insn "spe_evmwhsmfan"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhsmfan %0,%1,%2"
|
"evmwhsmfan %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhsmian"
|
(define_insn "spe_evmwhsmian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhsmian %0,%1,%2"
|
"evmwhsmian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhumian"
|
(define_insn "spe_evmwhumian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhumian %0,%1,%2"
|
"evmwhumian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhgssfaa"
|
(define_insn "spe_evmwhgssfaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhgssfaa %0,%1,%2"
|
"evmwhgssfaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhgsmfaa"
|
(define_insn "spe_evmwhgsmfaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhgsmfaa %0,%1,%2"
|
"evmwhgsmfaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhgsmiaa"
|
(define_insn "spe_evmwhgsmiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhgsmiaa %0,%1,%2"
|
"evmwhgsmiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhgumiaa"
|
(define_insn "spe_evmwhgumiaa"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhgumiaa %0,%1,%2"
|
"evmwhgumiaa %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhgssfan"
|
(define_insn "spe_evmwhgssfan"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(clobber (reg:SI SPEFSCR_REGNO))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhgssfan %0,%1,%2"
|
"evmwhgssfan %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhgsmfan"
|
(define_insn "spe_evmwhgsmfan"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhgsmfan %0,%1,%2"
|
"evmwhgsmfan %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhgsmian"
|
(define_insn "spe_evmwhgsmian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhgsmian %0,%1,%2"
|
"evmwhgsmian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_evmwhgumian"
|
(define_insn "spe_evmwhgumian"
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
|
(match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
(set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"evmwhgumian %0,%1,%2"
|
"evmwhgumian %0,%1,%2"
|
[(set_attr "type" "veccomplex")
|
[(set_attr "type" "veccomplex")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "spe_mtspefscr"
|
(define_insn "spe_mtspefscr"
|
[(set (reg:SI SPEFSCR_REGNO)
|
[(set (reg:SI SPEFSCR_REGNO)
|
(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
|
(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
|
722))]
|
722))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"mtspefscr %0"
|
"mtspefscr %0"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
(define_insn "spe_mfspefscr"
|
(define_insn "spe_mfspefscr"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
|
(unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
|
"TARGET_SPE"
|
"TARGET_SPE"
|
"mfspefscr %0"
|
"mfspefscr %0"
|
[(set_attr "type" "vecsimple")])
|
[(set_attr "type" "vecsimple")])
|
|
|
;; FP comparison stuff.
|
;; FP comparison stuff.
|
|
|
;; Flip the GT bit.
|
;; Flip the GT bit.
|
(define_insn "e500_flip_gt_bit"
|
(define_insn "e500_flip_gt_bit"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
|
[(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
|
"!TARGET_FPRS && TARGET_HARD_FLOAT"
|
"!TARGET_FPRS && TARGET_HARD_FLOAT"
|
"*
|
"*
|
{
|
{
|
return output_e500_flip_gt_bit (operands[0], operands[1]);
|
return output_e500_flip_gt_bit (operands[0], operands[1]);
|
}"
|
}"
|
[(set_attr "type" "cr_logical")])
|
[(set_attr "type" "cr_logical")])
|
|
|
;; MPC8540 single-precision FP instructions on GPRs.
|
;; MPC8540 single-precision FP instructions on GPRs.
|
;; We have 2 variants for each. One for IEEE compliant math and one
|
;; We have 2 variants for each. One for IEEE compliant math and one
|
;; for non IEEE compliant math.
|
;; for non IEEE compliant math.
|
|
|
(define_insn "cmpsfeq_gpr"
|
(define_insn "cmpsfeq_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
1000))]
|
1000))]
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
|
"efscmpeq %0,%1,%2"
|
"efscmpeq %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "tstsfeq_gpr"
|
(define_insn "tstsfeq_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
1001))]
|
1001))]
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
|
"efststeq %0,%1,%2"
|
"efststeq %0,%1,%2"
|
[(set_attr "type" "veccmpsimple")])
|
[(set_attr "type" "veccmpsimple")])
|
|
|
(define_insn "cmpsfgt_gpr"
|
(define_insn "cmpsfgt_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
1002))]
|
1002))]
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
|
"efscmpgt %0,%1,%2"
|
"efscmpgt %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "tstsfgt_gpr"
|
(define_insn "tstsfgt_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
1003))]
|
1003))]
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
|
"efststgt %0,%1,%2"
|
"efststgt %0,%1,%2"
|
[(set_attr "type" "veccmpsimple")])
|
[(set_attr "type" "veccmpsimple")])
|
|
|
(define_insn "cmpsflt_gpr"
|
(define_insn "cmpsflt_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
1004))]
|
1004))]
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
|
"efscmplt %0,%1,%2"
|
"efscmplt %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "tstsflt_gpr"
|
(define_insn "tstsflt_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
(match_operand:SF 2 "gpc_reg_operand" "r"))]
|
1005))]
|
1005))]
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
|
"efststlt %0,%1,%2"
|
"efststlt %0,%1,%2"
|
[(set_attr "type" "veccmpsimple")])
|
[(set_attr "type" "veccmpsimple")])
|
|
|
;; Same thing, but for double-precision.
|
;; Same thing, but for double-precision.
|
|
|
(define_insn "cmpdfeq_gpr"
|
(define_insn "cmpdfeq_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
CMPDFEQ_GPR))]
|
CMPDFEQ_GPR))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
|
"efdcmpeq %0,%1,%2"
|
"efdcmpeq %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "tstdfeq_gpr"
|
(define_insn "tstdfeq_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
TSTDFEQ_GPR))]
|
TSTDFEQ_GPR))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
|
"efdtsteq %0,%1,%2"
|
"efdtsteq %0,%1,%2"
|
[(set_attr "type" "veccmpsimple")])
|
[(set_attr "type" "veccmpsimple")])
|
|
|
(define_insn "cmpdfgt_gpr"
|
(define_insn "cmpdfgt_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
CMPDFGT_GPR))]
|
CMPDFGT_GPR))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
|
"efdcmpgt %0,%1,%2"
|
"efdcmpgt %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "tstdfgt_gpr"
|
(define_insn "tstdfgt_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
TSTDFGT_GPR))]
|
TSTDFGT_GPR))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
|
"efdtstgt %0,%1,%2"
|
"efdtstgt %0,%1,%2"
|
[(set_attr "type" "veccmpsimple")])
|
[(set_attr "type" "veccmpsimple")])
|
|
|
(define_insn "cmpdflt_gpr"
|
(define_insn "cmpdflt_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
CMPDFLT_GPR))]
|
CMPDFLT_GPR))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
|
"efdcmplt %0,%1,%2"
|
"efdcmplt %0,%1,%2"
|
[(set_attr "type" "veccmp")])
|
[(set_attr "type" "veccmp")])
|
|
|
(define_insn "tstdflt_gpr"
|
(define_insn "tstdflt_gpr"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP
|
(unspec:CCFP
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
[(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
(match_operand:DF 2 "gpc_reg_operand" "r"))]
|
TSTDFLT_GPR))]
|
TSTDFLT_GPR))]
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
|
"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
|
"efdtstlt %0,%1,%2"
|
"efdtstlt %0,%1,%2"
|
[(set_attr "type" "veccmpsimple")])
|
[(set_attr "type" "veccmpsimple")])
|
|
|
;; Like cceq_ior_compare, but compare the GT bits.
|
;; Like cceq_ior_compare, but compare the GT bits.
|
(define_insn "e500_cr_ior_compare"
|
(define_insn "e500_cr_ior_compare"
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
(unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
|
(unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
|
(match_operand 2 "cc_reg_operand" "y")]
|
(match_operand 2 "cc_reg_operand" "y")]
|
E500_CR_IOR_COMPARE))]
|
E500_CR_IOR_COMPARE))]
|
"TARGET_E500"
|
"TARGET_E500"
|
"cror 4*%0+gt,4*%1+gt,4*%2+gt"
|
"cror 4*%0+gt,4*%1+gt,4*%2+gt"
|
[(set_attr "type" "cr_logical")])
|
[(set_attr "type" "cr_logical")])
|
|
|
