/* Definitions of target machine for GNU compiler, for IBM S/390
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/* Definitions of target machine for GNU compiler, for IBM S/390
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Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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Ulrich Weigand (uweigand@de.ibm.com).
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Ulrich Weigand (uweigand@de.ibm.com).
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This file is part of GCC.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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Software Foundation; either version 3, or (at your option) any later
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version.
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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along with GCC; see the file COPYING3. If not see
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. */
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. */
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/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */
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/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */
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INT_MODE (OI, 32);
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INT_MODE (OI, 32);
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/* Define TFmode to work around reload problem PR 20927. */
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/* Define TFmode to work around reload problem PR 20927. */
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FLOAT_MODE (TF, 16, ieee_quad_format);
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FLOAT_MODE (TF, 16, ieee_quad_format);
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/* Add any extra modes needed to represent the condition code. */
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/* Add any extra modes needed to represent the condition code. */
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/*
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/*
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Condition Codes
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Condition Codes
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Check for zero
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Check for zero
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CCZ: EQ NE NE NE
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CCZ: EQ NE NE NE
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CCZ1: EQ NE (CS)
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CCZ1: EQ NE (CS)
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Unsigned compares
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Unsigned compares
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CCU: EQ LTU GTU NE (CLG/R, CL/R/Y, CLM/Y, CLI/Y)
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CCU: EQ LTU GTU NE (CLG/R, CL/R/Y, CLM/Y, CLI/Y)
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CCUR: EQ GTU LTU NE (CLGF/R)
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CCUR: EQ GTU LTU NE (CLGF/R)
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Signed compares
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Signed compares
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CCS: EQ LT GT UNORDERED (LTGFR, LTGR, LTR, ICM/Y,
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CCS: EQ LT GT UNORDERED (LTGFR, LTGR, LTR, ICM/Y,
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LTDBR, LTDR, LTEBR, LTER,
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LTDBR, LTDR, LTEBR, LTER,
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CG/R, C/R/Y, CGHI, CHI,
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CG/R, C/R/Y, CGHI, CHI,
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CDB/R, CD/R, CEB/R, CE/R,
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CDB/R, CD/R, CEB/R, CE/R,
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ADB/R, AEB/R, SDB/R, SEB/R,
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ADB/R, AEB/R, SDB/R, SEB/R,
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SRAG, SRA, SRDA)
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SRAG, SRA, SRDA)
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CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y)
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CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y)
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Condition codes resulting from add with overflow
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Condition codes resulting from add with overflow
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CCA: EQ LT GT Overflow
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CCA: EQ LT GT Overflow
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CCAP: EQ LT GT LT (AGHI, AHI)
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CCAP: EQ LT GT LT (AGHI, AHI)
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CCAN: EQ LT GT GT (AGHI, AHI)
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CCAN: EQ LT GT GT (AGHI, AHI)
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Condition codes of unsigned adds and subs
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Condition codes of unsigned adds and subs
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CCL: EQ NE EQ NE (ALGF/R, ALG/R, AL/R/Y,
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CCL: EQ NE EQ NE (ALGF/R, ALG/R, AL/R/Y,
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ALCG/R, ALC/R,
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ALCG/R, ALC/R,
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SLGF/R, SLG/R, SL/R/Y,
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SLGF/R, SLG/R, SL/R/Y,
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SLBG/R, SLB/R)
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SLBG/R, SLB/R)
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CCL1: GEU GEU LTU LTU (ALG/R, AL/R/Y)
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CCL1: GEU GEU LTU LTU (ALG/R, AL/R/Y)
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CCL2: GTU GTU LEU LEU (SLG/R, SL/R/Y)
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CCL2: GTU GTU LEU LEU (SLG/R, SL/R/Y)
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CCL3: EQ LTU EQ GTU (SLG/R, SL/R/Y)
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CCL3: EQ LTU EQ GTU (SLG/R, SL/R/Y)
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Test under mask checks
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Test under mask checks
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CCT: EQ NE NE NE (ICM/Y, TML, CG/R, CGHI,
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CCT: EQ NE NE NE (ICM/Y, TML, CG/R, CGHI,
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C/R/Y, CHI, NG/R, N/R/Y,
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C/R/Y, CHI, NG/R, N/R/Y,
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OG/R, O/R/Y, XG/R, X/R/Y)
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OG/R, O/R/Y, XG/R, X/R/Y)
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CCT1: NE EQ NE NE (TMH, TML)
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CCT1: NE EQ NE NE (TMH, TML)
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CCT2: NE NE EQ NE (TMH, TML)
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CCT2: NE NE EQ NE (TMH, TML)
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CCT3: NE NE NE EQ (TMH, TML)
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CCT3: NE NE NE EQ (TMH, TML)
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CCA and CCT modes are request only modes. These modes are never returned by
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CCA and CCT modes are request only modes. These modes are never returned by
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s390_select_cc_mode. They are only intended to match other modes.
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s390_select_cc_mode. They are only intended to match other modes.
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Requested mode -> Destination CC register mode
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Requested mode -> Destination CC register mode
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CCS, CCU, CCT, CCSR, CCUR -> CCZ
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CCS, CCU, CCT, CCSR, CCUR -> CCZ
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CCA -> CCAP, CCAN
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CCA -> CCAP, CCAN
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*** Comments ***
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*** Comments ***
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CCAP, CCAN
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CCAP, CCAN
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The CC obtained from add instruction usually can't be used for comparisons
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The CC obtained from add instruction usually can't be used for comparisons
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because its coupling with overflow flag. In case of an overflow the
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because its coupling with overflow flag. In case of an overflow the
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less than/greater than data are lost. Nevertheless a comparison can be done
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less than/greater than data are lost. Nevertheless a comparison can be done
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whenever immediate values are involved because they are known at compile time.
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whenever immediate values are involved because they are known at compile time.
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If you know whether the used constant is positive or negative you can predict
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If you know whether the used constant is positive or negative you can predict
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the sign of the result even in case of an overflow.
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the sign of the result even in case of an overflow.
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CCT, CCT1, CCT2, CCT3
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CCT, CCT1, CCT2, CCT3
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If bits of an integer masked with an AND instruction are checked, the test under
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If bits of an integer masked with an AND instruction are checked, the test under
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mask instructions turn out to be very handy for a set of special cases.
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mask instructions turn out to be very handy for a set of special cases.
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The simple cases are checks whether all masked bits are zero or ones:
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The simple cases are checks whether all masked bits are zero or ones:
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int a;
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int a;
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if ((a & (16 + 128)) == 0) -> CCT/CCZ
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if ((a & (16 + 128)) == 0) -> CCT/CCZ
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if ((a & (16 + 128)) == 16 + 128) -> CCT3
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if ((a & (16 + 128)) == 16 + 128) -> CCT3
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Using two extra modes makes it possible to do complete checks on two bits of an
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Using two extra modes makes it possible to do complete checks on two bits of an
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integer (This is possible on register operands only. TM does not provide the
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integer (This is possible on register operands only. TM does not provide the
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information necessary for CCT1 and CCT2 modes.):
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information necessary for CCT1 and CCT2 modes.):
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int a;
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int a;
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if ((a & (16 + 128)) == 16) -> CCT1
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if ((a & (16 + 128)) == 16) -> CCT1
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if ((a & (16 + 128)) == 128) -> CCT2
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if ((a & (16 + 128)) == 128) -> CCT2
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CCSR, CCUR
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CCSR, CCUR
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There are several instructions comparing 32 bit with 64 bit unsigned/signed
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There are several instructions comparing 32 bit with 64 bit unsigned/signed
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values. Such instructions can be considered to have a builtin zero/sign_extend.
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values. Such instructions can be considered to have a builtin zero/sign_extend.
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The problem is that in the RTL (to be canonical) the zero/sign extended operand
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The problem is that in the RTL (to be canonical) the zero/sign extended operand
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has to be the first one but the machine instructions like it the other way
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has to be the first one but the machine instructions like it the other way
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around. The following both modes can be considered as CCS and CCU modes with
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around. The following both modes can be considered as CCS and CCU modes with
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exchanged operands.
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exchanged operands.
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CCL1, CCL2
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CCL1, CCL2
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These modes represent the result of overflow checks.
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These modes represent the result of overflow checks.
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if (a + b < a) -> CCL1 state of the carry bit (CC2 | CC3)
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if (a + b < a) -> CCL1 state of the carry bit (CC2 | CC3)
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if (a - b > a) -> CCL2 state of the borrow bit (CC0 | CC1)
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if (a - b > a) -> CCL2 state of the borrow bit (CC0 | CC1)
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They are used when multi word numbers are computed dealing one SImode part after
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They are used when multi word numbers are computed dealing one SImode part after
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another or whenever manual overflow checks like the examples above are
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another or whenever manual overflow checks like the examples above are
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compiled.
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compiled.
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CCL3
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CCL3
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A logical subtract instruction sets the borrow bit in case of an overflow.
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A logical subtract instruction sets the borrow bit in case of an overflow.
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The resulting condition code of those instructions is represented by the
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The resulting condition code of those instructions is represented by the
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CCL3 mode. Together with the CCU mode this mode is used for jumpless
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CCL3 mode. Together with the CCU mode this mode is used for jumpless
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implementations of several if-constructs - see s390_expand_addcc for more
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implementations of several if-constructs - see s390_expand_addcc for more
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details.
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details.
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CCZ1
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CCZ1
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The compare and swap instructions sets the condition code to 0/1 if the
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The compare and swap instructions sets the condition code to 0/1 if the
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operands were equal/unequal. The CCZ1 mode ensures the result can be
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operands were equal/unequal. The CCZ1 mode ensures the result can be
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effectively placed into a register.
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effectively placed into a register.
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*/
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*/
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CC_MODE (CCZ);
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CC_MODE (CCZ);
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CC_MODE (CCZ1);
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CC_MODE (CCZ1);
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CC_MODE (CCA);
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CC_MODE (CCA);
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CC_MODE (CCAP);
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CC_MODE (CCAP);
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CC_MODE (CCAN);
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CC_MODE (CCAN);
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CC_MODE (CCL);
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CC_MODE (CCL);
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CC_MODE (CCL1);
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CC_MODE (CCL1);
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CC_MODE (CCL2);
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CC_MODE (CCL2);
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CC_MODE (CCL3);
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CC_MODE (CCL3);
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CC_MODE (CCU);
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CC_MODE (CCU);
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CC_MODE (CCUR);
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CC_MODE (CCUR);
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CC_MODE (CCS);
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CC_MODE (CCS);
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CC_MODE (CCSR);
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CC_MODE (CCSR);
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CC_MODE (CCT);
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CC_MODE (CCT);
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CC_MODE (CCT1);
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CC_MODE (CCT1);
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CC_MODE (CCT2);
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CC_MODE (CCT2);
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CC_MODE (CCT3);
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CC_MODE (CCT3);
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