;; Machine description for Sunplus S+CORE
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;; Machine description for Sunplus S+CORE
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;; Copyright (C) 2005, 2007
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;; Copyright (C) 2005, 2007
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;; Free Software Foundation, Inc.
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;; Free Software Foundation, Inc.
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;; Contributed by Sunnorth.
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;; Contributed by Sunnorth.
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;; This file is part of GCC.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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; branch conditional branch
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; branch conditional branch
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; jump unconditional jump
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; jump unconditional jump
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; call unconditional call
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; call unconditional call
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; load load instruction(s)
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; load load instruction(s)
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; store store instruction(s)
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; store store instruction(s)
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; cmp integer compare
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; cmp integer compare
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; arith integer arithmetic instruction
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; arith integer arithmetic instruction
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; move data movement within same register set
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; move data movement within same register set
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; const load constant
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; const load constant
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; nop no operation
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; nop no operation
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; mul integer multiply
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; mul integer multiply
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; div integer divide
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; div integer divide
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; cndmv conditional moves
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; cndmv conditional moves
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; fce transfer from hi/lo registers
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; fce transfer from hi/lo registers
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; tce transfer to hi/lo registers
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; tce transfer to hi/lo registers
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; fsr transfer from special registers
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; fsr transfer from special registers
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; tsr transfer to special registers
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; tsr transfer to special registers
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; pseudo pseudo instruction
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; pseudo pseudo instruction
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(define_constants
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(define_constants
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[(CC_REGNUM 33)
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[(CC_REGNUM 33)
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(T_REGNUM 34)
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(T_REGNUM 34)
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(RA_REGNUM 3)
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(RA_REGNUM 3)
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(SP_REGNUM 0)
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(SP_REGNUM 0)
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(AT_REGNUM 1)
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(AT_REGNUM 1)
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(FP_REGNUM 2)
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(FP_REGNUM 2)
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(RT_REGNUM 4)
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(RT_REGNUM 4)
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(GP_REGNUM 28)
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(GP_REGNUM 28)
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(EH_REGNUM 29)
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(EH_REGNUM 29)
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(HI_REGNUM 48)
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(HI_REGNUM 48)
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(LO_REGNUM 49)
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(LO_REGNUM 49)
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(CN_REGNUM 50)
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(CN_REGNUM 50)
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(LC_REGNUM 51)
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(LC_REGNUM 51)
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(SC_REGNUM 52)])
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(SC_REGNUM 52)])
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(define_constants
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(define_constants
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[(BITTST 0)
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[(BITTST 0)
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(CPLOAD 1)
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(CPLOAD 1)
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(CPRESTORE 2)
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(CPRESTORE 2)
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(SCB 3)
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(SCB 3)
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(SCW 4)
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(SCW 4)
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(SCE 5)
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(SCE 5)
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(SCLC 6)
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(SCLC 6)
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(LCB 7)
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(LCB 7)
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(LCW 8)
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(LCW 8)
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(LCE 9)
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(LCE 9)
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(SFFS 10)])
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(SFFS 10)])
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(define_attr "type"
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(define_attr "type"
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"unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr,pseudo"
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"unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr,pseudo"
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(const_string "unknown"))
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(const_string "unknown"))
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(define_attr "mode" "unknown,none,QI,HI,SI,DI"
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(define_attr "mode" "unknown,none,QI,HI,SI,DI"
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(const_string "unknown"))
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(const_string "unknown"))
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(define_attr "up_c" "yes,no"
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(define_attr "up_c" "yes,no"
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(const_string "no"))
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(const_string "no"))
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(include "score7.md")
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(include "score7.md")
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(include "predicates.md")
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(include "predicates.md")
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(include "misc.md")
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(include "misc.md")
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(include "mac.md")
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(include "mac.md")
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(define_expand "movqi"
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(define_expand "movqi"
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[(set (match_operand:QI 0 "nonimmediate_operand")
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[(set (match_operand:QI 0 "nonimmediate_operand")
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(match_operand:QI 1 "general_operand"))]
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(match_operand:QI 1 "general_operand"))]
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""
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""
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{
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{
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if (MEM_P (operands[0])
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if (MEM_P (operands[0])
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&& !register_operand (operands[1], QImode))
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&& !register_operand (operands[1], QImode))
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{
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{
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operands[1] = force_reg (QImode, operands[1]);
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operands[1] = force_reg (QImode, operands[1]);
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}
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}
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})
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})
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(define_insn "*movqi_insns"
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(define_insn "*movqi_insns"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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(match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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(match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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"!MEM_P (operands[0]) || register_operand (operands[1], QImode)"
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"!MEM_P (operands[0]) || register_operand (operands[1], QImode)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0: return mdp_limm (operands);
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case 0: return mdp_limm (operands);
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case 1: return mdp_move (operands);
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case 1: return mdp_move (operands);
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case 2: return mdp_linsn (operands, MDA_BYTE, false);
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case 2: return mdp_linsn (operands, MDA_BYTE, false);
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case 3: return mdp_sinsn (operands, MDA_BYTE);
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case 3: return mdp_sinsn (operands, MDA_BYTE);
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case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 6: return \"mfsr %0, %1\";
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case 6: return \"mfsr %0, %1\";
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case 7: return \"mtsr %1, %0\";
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case 7: return \"mtsr %1, %0\";
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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(set_attr "mode" "QI")])
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(set_attr "mode" "QI")])
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(define_expand "movhi"
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(define_expand "movhi"
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[(set (match_operand:HI 0 "nonimmediate_operand")
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[(set (match_operand:HI 0 "nonimmediate_operand")
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(match_operand:HI 1 "general_operand"))]
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(match_operand:HI 1 "general_operand"))]
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""
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""
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{
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{
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if (MEM_P (operands[0])
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if (MEM_P (operands[0])
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&& !register_operand (operands[1], HImode))
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&& !register_operand (operands[1], HImode))
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{
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{
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operands[1] = force_reg (HImode, operands[1]);
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operands[1] = force_reg (HImode, operands[1]);
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}
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}
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})
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})
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(define_insn "*movhi_insns"
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(define_insn "*movhi_insns"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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(match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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(match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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"!MEM_P (operands[0]) || register_operand (operands[1], HImode)"
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"!MEM_P (operands[0]) || register_operand (operands[1], HImode)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0: return mdp_limm (operands);
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case 0: return mdp_limm (operands);
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case 1: return mdp_move (operands);
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case 1: return mdp_move (operands);
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case 2: return mdp_linsn (operands, MDA_HWORD, false);
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case 2: return mdp_linsn (operands, MDA_HWORD, false);
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case 3: return mdp_sinsn (operands, MDA_HWORD);
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case 3: return mdp_sinsn (operands, MDA_HWORD);
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case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 6: return \"mfsr %0, %1\";
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case 6: return \"mfsr %0, %1\";
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case 7: return \"mtsr %1, %0\";
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case 7: return \"mtsr %1, %0\";
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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(set_attr "mode" "HI")])
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(set_attr "mode" "HI")])
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(define_expand "movsi"
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(define_expand "movsi"
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[(set (match_operand:SI 0 "nonimmediate_operand")
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[(set (match_operand:SI 0 "nonimmediate_operand")
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(match_operand:SI 1 "general_operand"))]
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(match_operand:SI 1 "general_operand"))]
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""
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""
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{
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{
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if (MEM_P (operands[0])
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if (MEM_P (operands[0])
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&& !register_operand (operands[1], SImode))
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&& !register_operand (operands[1], SImode))
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{
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{
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operands[1] = force_reg (SImode, operands[1]);
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operands[1] = force_reg (SImode, operands[1]);
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}
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}
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})
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})
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(define_insn "*movsi_insns"
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(define_insn "*movsi_insns"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a,d,*c")
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[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a,d,*c")
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(match_operand:SI 1 "general_operand" "i,d,m,d,*x,d,*a,d,*c,d"))]
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(match_operand:SI 1 "general_operand" "i,d,m,d,*x,d,*a,d,*c,d"))]
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"!MEM_P (operands[0]) || register_operand (operands[1], SImode)"
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"!MEM_P (operands[0]) || register_operand (operands[1], SImode)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0:
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case 0:
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if (GET_CODE (operands[1]) != CONST_INT)
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if (GET_CODE (operands[1]) != CONST_INT)
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return \"la %0, %1\";
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return \"la %0, %1\";
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else
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else
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return mdp_limm (operands);
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return mdp_limm (operands);
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case 1: return mdp_move (operands);
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case 1: return mdp_move (operands);
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case 2: return mdp_linsn (operands, MDA_WORD, false);
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case 2: return mdp_linsn (operands, MDA_WORD, false);
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case 3: return mdp_sinsn (operands, MDA_WORD);
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case 3: return mdp_sinsn (operands, MDA_WORD);
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case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 6: return \"mfsr %0, %1\";
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case 6: return \"mfsr %0, %1\";
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case 7: return \"mtsr %1, %0\";
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case 7: return \"mtsr %1, %0\";
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case 8: return \"mfcr %0, %1\";
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case 8: return \"mfcr %0, %1\";
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case 9: return \"mtcr %1, %0\";
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case 9: return \"mtcr %1, %0\";
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr,fcr,tcr")
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr,fcr,tcr")
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(set_attr "mode" "SI")])
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(set_attr "mode" "SI")])
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(define_insn_and_split "movdi"
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(define_insn_and_split "movdi"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,d,*x")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,d,*x")
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(match_operand:DI 1 "general_operand" "i,d,m,d,*x,d"))]
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(match_operand:DI 1 "general_operand" "i,d,m,d,*x,d"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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{
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{
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mds_movdi (operands);
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mds_movdi (operands);
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DONE;
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DONE;
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})
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})
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(define_expand "movsf"
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(define_expand "movsf"
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[(set (match_operand:SF 0 "nonimmediate_operand")
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[(set (match_operand:SF 0 "nonimmediate_operand")
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(match_operand:SF 1 "general_operand"))]
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(match_operand:SF 1 "general_operand"))]
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""
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""
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{
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{
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if (MEM_P (operands[0])
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if (MEM_P (operands[0])
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&& !register_operand (operands[1], SFmode))
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&& !register_operand (operands[1], SFmode))
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{
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{
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operands[1] = force_reg (SFmode, operands[1]);
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operands[1] = force_reg (SFmode, operands[1]);
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}
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}
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})
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})
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(define_insn "*movsf_insns"
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(define_insn "*movsf_insns"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
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[(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
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(match_operand:SF 1 "general_operand" "i,d,m,d"))]
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(match_operand:SF 1 "general_operand" "i,d,m,d"))]
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"!MEM_P (operands[0]) || register_operand (operands[1], SFmode)"
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"!MEM_P (operands[0]) || register_operand (operands[1], SFmode)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0: return \"li %0, %D1\";;
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case 0: return \"li %0, %D1\";;
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case 1: return mdp_move (operands);
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case 1: return mdp_move (operands);
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case 2: return mdp_linsn (operands, MDA_WORD, false);
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case 2: return mdp_linsn (operands, MDA_WORD, false);
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case 3: return mdp_sinsn (operands, MDA_WORD);
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case 3: return mdp_sinsn (operands, MDA_WORD);
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith,move,load,store")
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[(set_attr "type" "arith,move,load,store")
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(set_attr "mode" "SI")])
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(set_attr "mode" "SI")])
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(define_insn_and_split "movdf"
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(define_insn_and_split "movdf"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,m")
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[(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,m")
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(match_operand:DF 1 "general_operand" "i,d,m,d"))]
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(match_operand:DF 1 "general_operand" "i,d,m,d"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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{
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{
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mds_movdi (operands);
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mds_movdi (operands);
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DONE;
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DONE;
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})
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})
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(define_insn "addsi3"
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(define_insn "addsi3"
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[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
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[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
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(plus:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
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(plus:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
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(match_operand:SI 2 "arith_operand" "I,L,N,d")))]
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(match_operand:SI 2 "arith_operand" "I,L,N,d")))]
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""
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""
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0: return \"addis %0, %U2\";
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case 0: return \"addis %0, %U2\";
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case 1: return mdp_select_add_imm (operands, false);
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case 1: return mdp_select_add_imm (operands, false);
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case 2: return \"addri %0, %1, %c2\";
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case 2: return \"addri %0, %1, %c2\";
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case 3: return mdp_select (operands, "add", true, "", false);
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case 3: return mdp_select (operands, "add", true, "", false);
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith")
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(set_attr "mode" "SI")])
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(define_insn "*addsi3_cmp"
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(define_insn "*addsi3_cmp"
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[(set (reg:CC_NZ CC_REGNUM)
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ (plus:SI
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(compare:CC_NZ (plus:SI
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(match_operand:SI 1 "register_operand" "0,0,d,d")
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(match_operand:SI 1 "register_operand" "0,0,d,d")
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(match_operand:SI 2 "arith_operand" "I,L,N,d"))
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(match_operand:SI 2 "arith_operand" "I,L,N,d"))
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(const_int 0)))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=d,d,d,d"))]
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(clobber (match_scratch:SI 0 "=d,d,d,d"))]
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""
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""
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
|
{
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case 0: return \"addis.c %0, %U2\";
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case 0: return \"addis.c %0, %U2\";
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case 1: return mdp_select_add_imm (operands, true);
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case 1: return mdp_select_add_imm (operands, true);
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case 2: return \"addri.c %0, %1, %c2\";
|
case 2: return \"addri.c %0, %1, %c2\";
|
case 3: return mdp_select (operands, "add", true, "", true);
|
case 3: return mdp_select (operands, "add", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*addsi3_ucc"
|
(define_insn "*addsi3_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (plus:SI
|
(compare:CC_NZ (plus:SI
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"addis.c %0, %U2\";
|
case 0: return \"addis.c %0, %U2\";
|
case 1: return mdp_select_add_imm (operands, true);
|
case 1: return mdp_select_add_imm (operands, true);
|
case 2: return \"addri.c %0, %1, %c2\";
|
case 2: return \"addri.c %0, %1, %c2\";
|
case 3: return mdp_select (operands, "add", true, "", true);
|
case 3: return mdp_select (operands, "add", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "adddi3"
|
(define_insn "adddi3"
|
[(set (match_operand:DI 0 "register_operand" "=e,d")
|
[(set (match_operand:DI 0 "register_operand" "=e,d")
|
(plus:DI (match_operand:DI 1 "register_operand" "0,d")
|
(plus:DI (match_operand:DI 1 "register_operand" "0,d")
|
(match_operand:DI 2 "register_operand" "e,d")))
|
(match_operand:DI 2 "register_operand" "e,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
""
|
""
|
"@
|
"@
|
add! %L0, %L2\;addc! %H0, %H2
|
add! %L0, %L2\;addc! %H0, %H2
|
add.c %L0, %L1, %L2\;addc %H0, %H1, %H2"
|
add.c %L0, %L1, %L2\;addc %H0, %H1, %H2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_insn "subsi3"
|
(define_insn "subsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(minus:SI (match_operand:SI 1 "register_operand" "d")
|
(minus:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))]
|
(match_operand:SI 2 "register_operand" "d")))]
|
""
|
""
|
{
|
{
|
return mdp_select (operands, "sub", false, "", false);
|
return mdp_select (operands, "sub", false, "", false);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*subsi3_cmp"
|
(define_insn "*subsi3_cmp"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d"))
|
(match_operand:SI 2 "register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
""
|
""
|
{
|
{
|
return mdp_select (operands, "sub", false, "", true);
|
return mdp_select (operands, "sub", false, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_peephole2
|
(define_peephole2
|
[(set (match_operand:SI 0 "g32reg_operand" "")
|
[(set (match_operand:SI 0 "g32reg_operand" "")
|
(minus:SI (match_operand:SI 1 "g32reg_operand" "")
|
(minus:SI (match_operand:SI 1 "g32reg_operand" "")
|
(match_operand:SI 2 "g32reg_operand" "")))
|
(match_operand:SI 2 "g32reg_operand" "")))
|
(set (reg:CC CC_REGNUM)
|
(set (reg:CC CC_REGNUM)
|
(compare:CC (match_dup 1) (match_dup 2)))]
|
(compare:CC (match_dup 1) (match_dup 2)))]
|
""
|
""
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (match_dup 1) (match_dup 2)))
|
(compare:CC (match_dup 1) (match_dup 2)))
|
(set (match_dup 0)
|
(set (match_dup 0)
|
(minus:SI (match_dup 1) (match_dup 2)))])
|
(minus:SI (match_dup 1) (match_dup 2)))])
|
|
|
(define_insn "subsi3_ucc_pcmp"
|
(define_insn "subsi3_ucc_pcmp"
|
[(parallel
|
[(parallel
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (match_operand:SI 1 "register_operand" "d")
|
(compare:CC (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))
|
(match_operand:SI 2 "register_operand" "d")))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(minus:SI (match_dup 1) (match_dup 2)))])]
|
(minus:SI (match_dup 1) (match_dup 2)))])]
|
""
|
""
|
{
|
{
|
return mdp_select (operands, "sub", false, "", true);
|
return mdp_select (operands, "sub", false, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "subsi3_ucc"
|
(define_insn "subsi3_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d"))
|
(match_operand:SI 2 "register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(minus:SI (match_dup 1) (match_dup 2)))]
|
(minus:SI (match_dup 1) (match_dup 2)))]
|
""
|
""
|
{
|
{
|
return mdp_select (operands, "sub", false, "", true);
|
return mdp_select (operands, "sub", false, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "subdi3"
|
(define_insn "subdi3"
|
[(set (match_operand:DI 0 "register_operand" "=e,d")
|
[(set (match_operand:DI 0 "register_operand" "=e,d")
|
(minus:DI (match_operand:DI 1 "register_operand" "0,d")
|
(minus:DI (match_operand:DI 1 "register_operand" "0,d")
|
(match_operand:DI 2 "register_operand" "e,d")))
|
(match_operand:DI 2 "register_operand" "e,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
""
|
""
|
"@
|
"@
|
sub! %L0, %L2\;subc %H0, %H1, %H2
|
sub! %L0, %L2\;subc %H0, %H1, %H2
|
sub.c %L0, %L1, %L2\;subc %H0, %H1, %H2"
|
sub.c %L0, %L1, %L2\;subc %H0, %H1, %H2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_insn "andsi3"
|
(define_insn "andsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(and:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(and:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d")))]
|
(match_operand:SI 2 "arith_operand" "I,K,M,d")))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"andis %0, %U2\";
|
case 0: return \"andis %0, %U2\";
|
case 1: return \"andi %0, %c2";
|
case 1: return \"andi %0, %c2";
|
case 2: return \"andri %0, %1, %c2\";
|
case 2: return \"andri %0, %1, %c2\";
|
case 3: return mdp_select (operands, "and", true, "", false);
|
case 3: return mdp_select (operands, "and", true, "", false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "andsi3_cmp"
|
(define_insn "andsi3_cmp"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (and:SI (match_operand:SI 1 "register_operand" "0,0,0,d")
|
(compare:CC_NZ (and:SI (match_operand:SI 1 "register_operand" "0,0,0,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"andis.c %0, %U2\";
|
case 0: return \"andis.c %0, %U2\";
|
case 1: return \"andi.c %0, %c2";
|
case 1: return \"andi.c %0, %c2";
|
case 2: return \"andri.c %0, %1, %c2\";
|
case 2: return \"andri.c %0, %1, %c2\";
|
case 3: return mdp_select (operands, "and", true, "", true);
|
case 3: return mdp_select (operands, "and", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*andsi3_ucc"
|
(define_insn "*andsi3_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (and:SI
|
(compare:CC_NZ (and:SI
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(and:SI (match_dup 1) (match_dup 2)))]
|
(and:SI (match_dup 1) (match_dup 2)))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"andis.c %0, %U2\";
|
case 0: return \"andis.c %0, %U2\";
|
case 1: return \"andi.c %0, %c2";
|
case 1: return \"andi.c %0, %c2";
|
case 2: return \"andri.c %0, %1, %c2\";
|
case 2: return \"andri.c %0, %1, %c2\";
|
case 3: return mdp_select (operands, "and", true, "", true);
|
case 3: return mdp_select (operands, "and", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn_and_split "*zero_extract_andi"
|
(define_insn_and_split "*zero_extract_andi"
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (zero_extract:SI
|
(compare:CC (zero_extract:SI
|
(match_operand:SI 0 "register_operand" "d")
|
(match_operand:SI 0 "register_operand" "d")
|
(match_operand:SI 1 "const_uimm5" "")
|
(match_operand:SI 1 "const_uimm5" "")
|
(match_operand:SI 2 "const_uimm5" ""))
|
(match_operand:SI 2 "const_uimm5" ""))
|
(const_int 0)))]
|
(const_int 0)))]
|
""
|
""
|
"#"
|
"#"
|
""
|
""
|
[(const_int 1)]
|
[(const_int 1)]
|
{
|
{
|
mds_zero_extract_andi (operands);
|
mds_zero_extract_andi (operands);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "iorsi3"
|
(define_insn "iorsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(ior:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(ior:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d")))]
|
(match_operand:SI 2 "arith_operand" "I,K,M,d")))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"oris %0, %U2\";
|
case 0: return \"oris %0, %U2\";
|
case 1: return \"ori %0, %c2\";
|
case 1: return \"ori %0, %c2\";
|
case 2: return \"orri %0, %1, %c2\";
|
case 2: return \"orri %0, %1, %c2\";
|
case 3: return mdp_select (operands, "or", true, "", false);
|
case 3: return mdp_select (operands, "or", true, "", false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "iorsi3_ucc"
|
(define_insn "iorsi3_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ior:SI
|
(compare:CC_NZ (ior:SI
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(ior:SI (match_dup 1) (match_dup 2)))]
|
(ior:SI (match_dup 1) (match_dup 2)))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"oris.c %0, %U2\";
|
case 0: return \"oris.c %0, %U2\";
|
case 1: return \"ori.c %0, %c2\";
|
case 1: return \"ori.c %0, %c2\";
|
case 2: return \"orri.c %0, %1, %c2\";
|
case 2: return \"orri.c %0, %1, %c2\";
|
case 3: return mdp_select (operands, "or", true, "", true);
|
case 3: return mdp_select (operands, "or", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "iorsi3_cmp"
|
(define_insn "iorsi3_cmp"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ior:SI
|
(compare:CC_NZ (ior:SI
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"oris.c %0, %U2\";
|
case 0: return \"oris.c %0, %U2\";
|
case 1: return \"ori.c %0, %c2\";
|
case 1: return \"ori.c %0, %c2\";
|
case 2: return \"orri.c %0, %1, %c2\";
|
case 2: return \"orri.c %0, %1, %c2\";
|
case 3: return mdp_select (operands, "or", true, "", true);
|
case 3: return mdp_select (operands, "or", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "xorsi3"
|
(define_insn "xorsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(xor:SI (match_operand:SI 1 "register_operand" "d")
|
(xor:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))]
|
(match_operand:SI 2 "register_operand" "d")))]
|
""
|
""
|
{
|
{
|
return mdp_select (operands, "xor", true, "", false);
|
return mdp_select (operands, "xor", true, "", false);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "xorsi3_ucc"
|
(define_insn "xorsi3_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d"))
|
(match_operand:SI 2 "register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(xor:SI (match_dup 1) (match_dup 2)))]
|
(xor:SI (match_dup 1) (match_dup 2)))]
|
""
|
""
|
{
|
{
|
return mdp_select (operands, "xor", true, "", true);
|
return mdp_select (operands, "xor", true, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "xorsi3_cmp"
|
(define_insn "xorsi3_cmp"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d"))
|
(match_operand:SI 2 "register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
""
|
""
|
{
|
{
|
return mdp_select (operands, "xor", true, "", true);
|
return mdp_select (operands, "xor", true, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "extendqisi2"
|
(define_insn "extendqisi2"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extsb %0, %1\";
|
case 0: return \"extsb %0, %1\";
|
case 1: return mdp_linsn (operands, MDA_BYTE, true);
|
case 1: return mdp_linsn (operands, MDA_BYTE, true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith,load")
|
[(set_attr "type" "arith,load")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendqisi2_ucc"
|
(define_insn "*extendqisi2_ucc"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(sign_extend:SI (match_operand:QI 2 "register_operand" "0")))]
|
(sign_extend:SI (match_operand:QI 2 "register_operand" "0")))]
|
""
|
""
|
"extsb.c %0, %1"
|
"extsb.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendqisi2_cmp"
|
(define_insn "*extendqisi2_cmp"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
""
|
""
|
"extsb.c %0, %1"
|
"extsb.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "extendhisi2"
|
(define_insn "extendhisi2"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extsh %0, %1\";
|
case 0: return \"extsh %0, %1\";
|
case 1: return mdp_linsn (operands, MDA_HWORD, true);
|
case 1: return mdp_linsn (operands, MDA_HWORD, true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith, load")
|
[(set_attr "type" "arith, load")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendhisi2_ucc"
|
(define_insn "*extendhisi2_ucc"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(sign_extend:SI (match_operand:HI 2 "register_operand" "0")))]
|
(sign_extend:SI (match_operand:HI 2 "register_operand" "0")))]
|
""
|
""
|
"extsh.c %0, %1"
|
"extsh.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendhisi2_cmp"
|
(define_insn "*extendhisi2_cmp"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
""
|
""
|
"extsh.c %0, %1"
|
"extsh.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "zero_extendqisi2"
|
(define_insn "zero_extendqisi2"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extzb %0, %1\";
|
case 0: return \"extzb %0, %1\";
|
case 1: return mdp_linsn (operands, MDA_BYTE, false);
|
case 1: return mdp_linsn (operands, MDA_BYTE, false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith, load")
|
[(set_attr "type" "arith, load")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendqisi2_ucc"
|
(define_insn "*zero_extendqisi2_ucc"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(zero_extend:SI (match_operand:QI 2 "register_operand" "0")))]
|
(zero_extend:SI (match_operand:QI 2 "register_operand" "0")))]
|
""
|
""
|
"extzb.c %0, %1"
|
"extzb.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendqisi2_cmp"
|
(define_insn "*zero_extendqisi2_cmp"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
""
|
""
|
"extzb.c %0, %1"
|
"extzb.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "zero_extendhisi2"
|
(define_insn "zero_extendhisi2"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extzh %0, %1\";
|
case 0: return \"extzh %0, %1\";
|
case 1: return mdp_linsn (operands, MDA_HWORD, false);
|
case 1: return mdp_linsn (operands, MDA_HWORD, false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith, load")
|
[(set_attr "type" "arith, load")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendhisi2_ucc"
|
(define_insn "*zero_extendhisi2_ucc"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(zero_extend:SI (match_operand:HI 2 "register_operand" "0")))]
|
(zero_extend:SI (match_operand:HI 2 "register_operand" "0")))]
|
""
|
""
|
"extzh.c %0, %1"
|
"extzh.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendhisi2_cmp"
|
(define_insn "*zero_extendhisi2_cmp"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
""
|
""
|
"extzh.c %0, %1"
|
"extzh.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mulsi3"
|
(define_insn "mulsi3"
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
(mult:SI (match_operand:SI 1 "register_operand" "d")
|
(mult:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))
|
(match_operand:SI 2 "register_operand" "d")))
|
(clobber (reg:SI HI_REGNUM))]
|
(clobber (reg:SI HI_REGNUM))]
|
"!TARGET_SCORE5U"
|
"!TARGET_SCORE5U"
|
"mul %1, %2"
|
"mul %1, %2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mulsidi3"
|
(define_insn "mulsidi3"
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
(mult:DI (sign_extend:DI
|
(mult:DI (sign_extend:DI
|
(match_operand:SI 1 "register_operand" "d"))
|
(match_operand:SI 1 "register_operand" "d"))
|
(sign_extend:DI
|
(sign_extend:DI
|
(match_operand:SI 2 "register_operand" "d"))))]
|
(match_operand:SI 2 "register_operand" "d"))))]
|
"!TARGET_SCORE5U"
|
"!TARGET_SCORE5U"
|
"mul %1, %2"
|
"mul %1, %2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_insn "umulsidi3"
|
(define_insn "umulsidi3"
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
(mult:DI (zero_extend:DI
|
(mult:DI (zero_extend:DI
|
(match_operand:SI 1 "register_operand" "d"))
|
(match_operand:SI 1 "register_operand" "d"))
|
(zero_extend:DI
|
(zero_extend:DI
|
(match_operand:SI 2 "register_operand" "d"))))]
|
(match_operand:SI 2 "register_operand" "d"))))]
|
"!TARGET_SCORE5U"
|
"!TARGET_SCORE5U"
|
"mulu %1, %2"
|
"mulu %1, %2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_insn "divmodsi4"
|
(define_insn "divmodsi4"
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
(div:SI (match_operand:SI 1 "register_operand" "d")
|
(div:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))
|
(match_operand:SI 2 "register_operand" "d")))
|
(set (match_operand:SI 3 "register_operand" "=h")
|
(set (match_operand:SI 3 "register_operand" "=h")
|
(mod:SI (match_dup 1) (match_dup 2)))]
|
(mod:SI (match_dup 1) (match_dup 2)))]
|
"!TARGET_SCORE5U"
|
"!TARGET_SCORE5U"
|
"div %1, %2"
|
"div %1, %2"
|
[(set_attr "type" "div")
|
[(set_attr "type" "div")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "udivmodsi4"
|
(define_insn "udivmodsi4"
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
(udiv:SI (match_operand:SI 1 "register_operand" "d")
|
(udiv:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))
|
(match_operand:SI 2 "register_operand" "d")))
|
(set (match_operand:SI 3 "register_operand" "=h")
|
(set (match_operand:SI 3 "register_operand" "=h")
|
(umod:SI (match_dup 1) (match_dup 2)))]
|
(umod:SI (match_dup 1) (match_dup 2)))]
|
"!TARGET_SCORE5U"
|
"!TARGET_SCORE5U"
|
"divu %1, %2"
|
"divu %1, %2"
|
[(set_attr "type" "div")
|
[(set_attr "type" "div")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "ashlsi3"
|
(define_insn "ashlsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d,d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
""
|
""
|
"@
|
"@
|
slli %0, %1, %c2
|
slli %0, %1, %c2
|
sll %0, %1, %2"
|
sll %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "ashlsi3_ucc"
|
(define_insn "ashlsi3_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashift:SI
|
(compare:CC_NZ (ashift:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(ashift:SI (match_dup 1) (match_dup 2)))]
|
(ashift:SI (match_dup 1) (match_dup 2)))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return mdp_select (operands, "slli", false, "c", true);
|
case 0: return mdp_select (operands, "slli", false, "c", true);
|
case 1: return mdp_select (operands, "sll", false, "", true);
|
case 1: return mdp_select (operands, "sll", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "ashlsi3_cmp"
|
(define_insn "ashlsi3_cmp"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashift:SI
|
(compare:CC_NZ (ashift:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return mdp_select (operands, "slli", false, "c", true);
|
case 0: return mdp_select (operands, "slli", false, "c", true);
|
case 1: return mdp_select (operands, "sll", false, "", true);
|
case 1: return mdp_select (operands, "sll", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "ashrsi3"
|
(define_insn "ashrsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
""
|
""
|
"@
|
"@
|
srai %0, %1, %c2
|
srai %0, %1, %c2
|
sra %0, %1, %2"
|
sra %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "ashrsi3_ucc"
|
(define_insn "ashrsi3_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashiftrt:SI
|
(compare:CC_NZ (ashiftrt:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
|
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"srai.c %0, %1, %c2\";
|
case 0: return \"srai.c %0, %1, %c2\";
|
case 1: return mdp_select (operands, "sra", false, "", true);
|
case 1: return mdp_select (operands, "sra", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "ashrsi3_cmp"
|
(define_insn "ashrsi3_cmp"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashiftrt:SI
|
(compare:CC_NZ (ashiftrt:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"srai.c %0, %1, %c2\";
|
case 0: return \"srai.c %0, %1, %c2\";
|
case 1: return mdp_select (operands, "sra", false, "", true);
|
case 1: return mdp_select (operands, "sra", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "lshrsi3"
|
(define_insn "lshrsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
""
|
""
|
"@
|
"@
|
srli %0, %1, %c2
|
srli %0, %1, %c2
|
srl %0, %1, %2"
|
srl %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "lshrsi3_ucc"
|
(define_insn "lshrsi3_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (lshiftrt:SI
|
(compare:CC_NZ (lshiftrt:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
|
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return mdp_select (operands, "srli", false, "c", true);
|
case 0: return mdp_select (operands, "srli", false, "c", true);
|
case 1: return mdp_select (operands, "srl", false, "", true);
|
case 1: return mdp_select (operands, "srl", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "lshrsi3_cmp"
|
(define_insn "lshrsi3_cmp"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (lshiftrt:SI
|
(compare:CC_NZ (lshiftrt:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return mdp_select (operands, "srli", false, "c", true);
|
case 0: return mdp_select (operands, "srli", false, "c", true);
|
case 1: return mdp_select (operands, "srl", false, "", true);
|
case 1: return mdp_select (operands, "srl", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "negsi2"
|
(define_insn "negsi2"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(neg:SI (match_operand:SI 1 "register_operand" "d")))]
|
(neg:SI (match_operand:SI 1 "register_operand" "d")))]
|
""
|
""
|
"neg %0, %1"
|
"neg %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*negsi2_cmp"
|
(define_insn "*negsi2_cmp"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
""
|
""
|
"@
|
"@
|
neg! %0, %1
|
neg! %0, %1
|
neg.c %0, %1"
|
neg.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "negsi2_ucc"
|
(define_insn "negsi2_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=e,d")
|
(set (match_operand:SI 0 "register_operand" "=e,d")
|
(neg:SI (match_dup 1)))]
|
(neg:SI (match_dup 1)))]
|
""
|
""
|
"@
|
"@
|
neg! %0, %1
|
neg! %0, %1
|
neg.c %0, %1"
|
neg.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "one_cmplsi2"
|
(define_insn "one_cmplsi2"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(not:SI (match_operand:SI 1 "register_operand" "d")))]
|
(not:SI (match_operand:SI 1 "register_operand" "d")))]
|
""
|
""
|
"not %0, %1"
|
"not %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "one_cmplsi2_ucc"
|
(define_insn "one_cmplsi2_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=e,d")
|
(set (match_operand:SI 0 "register_operand" "=e,d")
|
(not:SI (match_dup 1)))]
|
(not:SI (match_dup 1)))]
|
""
|
""
|
"@
|
"@
|
not! %0, %1
|
not! %0, %1
|
not.c %0, %1"
|
not.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "one_cmplsi2_cmp"
|
(define_insn "one_cmplsi2_cmp"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
""
|
""
|
"@
|
"@
|
not! %0, %1
|
not! %0, %1
|
not.c %0, %1"
|
not.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "rotlsi3"
|
(define_insn "rotlsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(rotate:SI (match_operand:SI 1 "register_operand" "d,d")
|
(rotate:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
""
|
""
|
"@
|
"@
|
roli.c %0, %1, %c2
|
roli.c %0, %1, %c2
|
rol.c %0, %1, %2"
|
rol.c %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "rotrsi3"
|
(define_insn "rotrsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(rotatert:SI (match_operand:SI 1 "register_operand" "d,d")
|
(rotatert:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
""
|
""
|
"@
|
"@
|
rori.c %0, %1, %c2
|
rori.c %0, %1, %c2
|
ror.c %0, %1, %2"
|
ror.c %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "cmpsi"
|
(define_expand "cmpsi"
|
[(match_operand:SI 0 "register_operand" "")
|
[(match_operand:SI 0 "register_operand" "")
|
(match_operand:SI 1 "arith_operand" "")]
|
(match_operand:SI 1 "arith_operand" "")]
|
""
|
""
|
{
|
{
|
cmp_op0 = operands[0];
|
cmp_op0 = operands[0];
|
cmp_op1 = operands[1];
|
cmp_op1 = operands[1];
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "cmpsi_nz"
|
(define_insn "cmpsi_nz"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (match_operand:SI 0 "register_operand" "d,e,d")
|
(compare:CC_NZ (match_operand:SI 0 "register_operand" "d,e,d")
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
""
|
""
|
"@
|
"@
|
cmpi.c %0, %c1
|
cmpi.c %0, %c1
|
cmp! %0, %1
|
cmp! %0, %1
|
cmp.c %0, %1"
|
cmp.c %0, %1"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "cmpsi_n"
|
(define_insn "cmpsi_n"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (match_operand:SI 0 "register_operand" "d,e,d")
|
(compare:CC_N (match_operand:SI 0 "register_operand" "d,e,d")
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
""
|
""
|
"@
|
"@
|
cmpi.c %0, %c1
|
cmpi.c %0, %c1
|
cmp! %0, %1
|
cmp! %0, %1
|
cmp.c %0, %1"
|
cmp.c %0, %1"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*cmpsi_to_addsi"
|
(define_insn "*cmpsi_to_addsi"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (match_operand:SI 1 "register_operand" "0,d")
|
(compare:CC_NZ (match_operand:SI 1 "register_operand" "0,d")
|
(neg:SI (match_operand:SI 2 "register_operand" "e,d"))))
|
(neg:SI (match_operand:SI 2 "register_operand" "e,d"))))
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
""
|
""
|
"@
|
"@
|
add! %0, %2
|
add! %0, %2
|
add.c %0, %1, %2"
|
add.c %0, %1, %2"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "cmpsi_cc"
|
(define_insn "cmpsi_cc"
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (match_operand:SI 0 "register_operand" "d,e,d")
|
(compare:CC (match_operand:SI 0 "register_operand" "d,e,d")
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
""
|
""
|
"@
|
"@
|
cmpi.c %0, %c1
|
cmpi.c %0, %c1
|
cmp! %0, %1
|
cmp! %0, %1
|
cmp.c %0, %1"
|
cmp.c %0, %1"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "beq"
|
(define_expand "beq"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (eq (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (eq (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_expand "bne"
|
(define_expand "bne"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (ne (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (ne (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_expand "bgt"
|
(define_expand "bgt"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (gt (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (gt (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_expand "ble"
|
(define_expand "ble"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (le (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (le (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_expand "bge"
|
(define_expand "bge"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (ge (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (ge (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_expand "blt"
|
(define_expand "blt"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (lt (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (lt (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_expand "bgtu"
|
(define_expand "bgtu"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (gtu (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (gtu (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_expand "bleu"
|
(define_expand "bleu"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (leu (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (leu (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_expand "bgeu"
|
(define_expand "bgeu"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (geu (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (geu (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_expand "bltu"
|
(define_expand "bltu"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (ltu (reg:CC CC_REGNUM) (const_int 0))
|
(if_then_else (ltu (reg:CC CC_REGNUM) (const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
mda_gen_cmp (CCmode);
|
mda_gen_cmp (CCmode);
|
})
|
})
|
|
|
(define_insn "branch_n"
|
(define_insn "branch_n"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "branch_n_operator"
|
(match_operator 0 "branch_n_operator"
|
[(reg:CC_N CC_REGNUM)
|
[(reg:CC_N CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
"b%C0 %1"
|
"b%C0 %1"
|
[(set_attr "type" "branch")])
|
[(set_attr "type" "branch")])
|
|
|
(define_insn "branch_nz"
|
(define_insn "branch_nz"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "branch_nz_operator"
|
(match_operator 0 "branch_nz_operator"
|
[(reg:CC_NZ CC_REGNUM)
|
[(reg:CC_NZ CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
"b%C0 %1"
|
"b%C0 %1"
|
[(set_attr "type" "branch")])
|
[(set_attr "type" "branch")])
|
|
|
(define_insn "branch_cc"
|
(define_insn "branch_cc"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "comparison_operator"
|
(match_operator 0 "comparison_operator"
|
[(reg:CC CC_REGNUM)
|
[(reg:CC CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
"b%C0 %1"
|
"b%C0 %1"
|
[(set_attr "type" "branch")])
|
[(set_attr "type" "branch")])
|
|
|
(define_insn "jump"
|
(define_insn "jump"
|
[(set (pc)
|
[(set (pc)
|
(label_ref (match_operand 0 "" "")))]
|
(label_ref (match_operand 0 "" "")))]
|
""
|
""
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
return \"j %0\";
|
return \"j %0\";
|
else
|
else
|
return \"b %0\";
|
return \"b %0\";
|
}
|
}
|
[(set_attr "type" "jump")])
|
[(set_attr "type" "jump")])
|
|
|
(define_expand "sibcall"
|
(define_expand "sibcall"
|
[(parallel [(call (match_operand 0 "" "")
|
[(parallel [(call (match_operand 0 "" "")
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(use (match_operand 2 "" ""))])]
|
(use (match_operand 2 "" ""))])]
|
""
|
""
|
{
|
{
|
mdx_call (operands, true);
|
mdx_call (operands, true);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "sibcall_internal"
|
(define_insn "sibcall_internal"
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(clobber (reg:SI RT_REGNUM))]
|
(clobber (reg:SI RT_REGNUM))]
|
"SIBLING_CALL_P (insn)"
|
"SIBLING_CALL_P (insn)"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"br%S0 %0\";
|
case 0: return \"br%S0 %0\";
|
case 1: return \"j %0\";
|
case 1: return \"j %0\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv r29, %0\;br r29\";
|
case 0: return \"mv r29, %0\;br r29\";
|
case 1: return \"la r29, %0\;br r29\";
|
case 1: return \"la r29, %0\;br r29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "call")])
|
[(set_attr "type" "call")])
|
|
|
(define_expand "sibcall_value"
|
(define_expand "sibcall_value"
|
[(parallel [(set (match_operand 0 "" "")
|
[(parallel [(set (match_operand 0 "" "")
|
(call (match_operand 1 "" "") (match_operand 2 "" "")))
|
(call (match_operand 1 "" "") (match_operand 2 "" "")))
|
(use (match_operand 3 "" ""))])]
|
(use (match_operand 3 "" ""))])]
|
""
|
""
|
{
|
{
|
mdx_call_value (operands, true);
|
mdx_call_value (operands, true);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "sibcall_value_internal"
|
(define_insn "sibcall_value_internal"
|
[(set (match_operand 0 "register_operand" "=d,d")
|
[(set (match_operand 0 "register_operand" "=d,d")
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
|
(match_operand 2 "" "")))
|
(match_operand 2 "" "")))
|
(clobber (reg:SI RT_REGNUM))]
|
(clobber (reg:SI RT_REGNUM))]
|
"SIBLING_CALL_P (insn)"
|
"SIBLING_CALL_P (insn)"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"br%S1 %1\";
|
case 0: return \"br%S1 %1\";
|
case 1: return \"j %1\";
|
case 1: return \"j %1\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv r29, %1\;br r29\";
|
case 0: return \"mv r29, %1\;br r29\";
|
case 1: return \"la r29, %1\;br r29\";
|
case 1: return \"la r29, %1\;br r29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "call")])
|
[(set_attr "type" "call")])
|
|
|
(define_expand "call"
|
(define_expand "call"
|
[(parallel [(call (match_operand 0 "" "") (match_operand 1 "" ""))
|
[(parallel [(call (match_operand 0 "" "") (match_operand 1 "" ""))
|
(use (match_operand 2 "" ""))])]
|
(use (match_operand 2 "" ""))])]
|
""
|
""
|
{
|
{
|
mdx_call (operands, false);
|
mdx_call (operands, false);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "call_internal"
|
(define_insn "call_internal"
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(clobber (reg:SI RA_REGNUM))]
|
(clobber (reg:SI RA_REGNUM))]
|
""
|
""
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"brl%S0 %0\";
|
case 0: return \"brl%S0 %0\";
|
case 1: return \"jl %0\";
|
case 1: return \"jl %0\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv r29, %0\;brl r29\";
|
case 0: return \"mv r29, %0\;brl r29\";
|
case 1: return \"la r29, %0\;brl r29\";
|
case 1: return \"la r29, %0\;brl r29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "call")])
|
[(set_attr "type" "call")])
|
|
|
(define_expand "call_value"
|
(define_expand "call_value"
|
[(parallel [(set (match_operand 0 "" "")
|
[(parallel [(set (match_operand 0 "" "")
|
(call (match_operand 1 "" "") (match_operand 2 "" "")))
|
(call (match_operand 1 "" "") (match_operand 2 "" "")))
|
(use (match_operand 3 "" ""))])]
|
(use (match_operand 3 "" ""))])]
|
""
|
""
|
{
|
{
|
mdx_call_value (operands, false);
|
mdx_call_value (operands, false);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "call_value_internal"
|
(define_insn "call_value_internal"
|
[(set (match_operand 0 "register_operand" "=d,d")
|
[(set (match_operand 0 "register_operand" "=d,d")
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
|
(match_operand 2 "" "")))
|
(match_operand 2 "" "")))
|
(clobber (reg:SI RA_REGNUM))]
|
(clobber (reg:SI RA_REGNUM))]
|
""
|
""
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"brl%S1 %1\";
|
case 0: return \"brl%S1 %1\";
|
case 1: return \"jl %1\";
|
case 1: return \"jl %1\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv r29, %1\;brl r29\";
|
case 0: return \"mv r29, %1\;brl r29\";
|
case 1: return \"la r29, %1\;brl r29\";
|
case 1: return \"la r29, %1\;brl r29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "call")])
|
[(set_attr "type" "call")])
|
|
|
(define_expand "indirect_jump"
|
(define_expand "indirect_jump"
|
[(set (pc) (match_operand 0 "register_operand" "d"))]
|
[(set (pc) (match_operand 0 "register_operand" "d"))]
|
""
|
""
|
{
|
{
|
rtx dest;
|
rtx dest;
|
dest = operands[0];
|
dest = operands[0];
|
if (GET_CODE (dest) != REG
|
if (GET_CODE (dest) != REG
|
|| GET_MODE (dest) != Pmode)
|
|| GET_MODE (dest) != Pmode)
|
operands[0] = copy_to_mode_reg (Pmode, dest);
|
operands[0] = copy_to_mode_reg (Pmode, dest);
|
|
|
emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
|
emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "indirect_jump_internal1"
|
(define_insn "indirect_jump_internal1"
|
[(set (pc) (match_operand:SI 0 "register_operand" "d"))]
|
[(set (pc) (match_operand:SI 0 "register_operand" "d"))]
|
""
|
""
|
"br%S0 %0"
|
"br%S0 %0"
|
[(set_attr "type" "jump")])
|
[(set_attr "type" "jump")])
|
|
|
(define_expand "tablejump"
|
(define_expand "tablejump"
|
[(set (pc)
|
[(set (pc)
|
(match_operand 0 "register_operand" "d"))
|
(match_operand 0 "register_operand" "d"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
""
|
""
|
{
|
{
|
emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
|
emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "tablejump_internal1"
|
(define_insn "tablejump_internal1"
|
[(set (pc)
|
[(set (pc)
|
(match_operand:SI 0 "register_operand" "d"))
|
(match_operand:SI 0 "register_operand" "d"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
""
|
""
|
"*
|
"*
|
if (flag_pic)
|
if (flag_pic)
|
return \"mv r29, %0\;.cpadd r29\;br r29\";
|
return \"mv r29, %0\;.cpadd r29\;br r29\";
|
else
|
else
|
return \"br%S0 %0\";
|
return \"br%S0 %0\";
|
"
|
"
|
[(set_attr "type" "jump")])
|
[(set_attr "type" "jump")])
|
|
|
(define_expand "prologue"
|
(define_expand "prologue"
|
[(const_int 1)]
|
[(const_int 1)]
|
""
|
""
|
{
|
{
|
mdx_prologue ();
|
mdx_prologue ();
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "epilogue"
|
(define_expand "epilogue"
|
[(const_int 2)]
|
[(const_int 2)]
|
""
|
""
|
{
|
{
|
mdx_epilogue (false);
|
mdx_epilogue (false);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "sibcall_epilogue"
|
(define_expand "sibcall_epilogue"
|
[(const_int 2)]
|
[(const_int 2)]
|
""
|
""
|
{
|
{
|
mdx_epilogue (true);
|
mdx_epilogue (true);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "return_internal"
|
(define_insn "return_internal"
|
[(return)
|
[(return)
|
(use (match_operand 0 "pmode_register_operand" "d"))]
|
(use (match_operand 0 "pmode_register_operand" "d"))]
|
""
|
""
|
"br%S0 %0")
|
"br%S0 %0")
|
|
|
(define_insn "nop"
|
(define_insn "nop"
|
[(const_int 0)]
|
[(const_int 0)]
|
""
|
""
|
"#nop!"
|
"#nop!"
|
)
|
)
|
|
|
(define_insn "cpload"
|
(define_insn "cpload"
|
[(unspec_volatile:SI [(const_int 1)] CPLOAD)]
|
[(unspec_volatile:SI [(const_int 1)] CPLOAD)]
|
"flag_pic"
|
"flag_pic"
|
".cpload r29"
|
".cpload r29"
|
)
|
)
|
|
|
(define_insn "cprestore_use_fp"
|
(define_insn "cprestore_use_fp"
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
(use (reg:SI FP_REGNUM))]
|
(use (reg:SI FP_REGNUM))]
|
"flag_pic"
|
"flag_pic"
|
".cprestore r2, %0"
|
".cprestore r2, %0"
|
)
|
)
|
|
|
(define_insn "cprestore_use_sp"
|
(define_insn "cprestore_use_sp"
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
(use (reg:SI SP_REGNUM))]
|
(use (reg:SI SP_REGNUM))]
|
"flag_pic"
|
"flag_pic"
|
".cprestore r0, %0"
|
".cprestore r0, %0"
|
)
|
)
|
|
|
(define_expand "doloop_end"
|
(define_expand "doloop_end"
|
[(use (match_operand 0 "" "")) ; loop pseudo
|
[(use (match_operand 0 "" "")) ; loop pseudo
|
(use (match_operand 1 "" "")) ; iterations; zero if unknown
|
(use (match_operand 1 "" "")) ; iterations; zero if unknown
|
(use (match_operand 2 "" "")) ; max iterations
|
(use (match_operand 2 "" "")) ; max iterations
|
(use (match_operand 3 "" "")) ; loop level
|
(use (match_operand 3 "" "")) ; loop level
|
(use (match_operand 4 "" ""))] ; label
|
(use (match_operand 4 "" ""))] ; label
|
"!TARGET_NHWLOOP"
|
"!TARGET_NHWLOOP"
|
{
|
{
|
if (INTVAL (operands[3]) > 1)
|
if (INTVAL (operands[3]) > 1)
|
FAIL;
|
FAIL;
|
|
|
if (GET_MODE (operands[0]) == SImode)
|
if (GET_MODE (operands[0]) == SImode)
|
{
|
{
|
rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM);
|
rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM);
|
emit_jump_insn (gen_doloop_end_si (sr0, operands[4]));
|
emit_jump_insn (gen_doloop_end_si (sr0, operands[4]));
|
}
|
}
|
else
|
else
|
FAIL;
|
FAIL;
|
|
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "doloop_end_si"
|
(define_insn "doloop_end_si"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(ne (match_operand:SI 0 "sr0_operand" "")
|
(ne (match_operand:SI 0 "sr0_operand" "")
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))
|
(pc)))
|
(set (match_dup 0)
|
(set (match_dup 0)
|
(plus:SI (match_dup 0)
|
(plus:SI (match_dup 0)
|
(const_int -1)))
|
(const_int -1)))
|
(clobber (reg:CC CC_REGNUM))
|
(clobber (reg:CC CC_REGNUM))
|
]
|
]
|
"!TARGET_NHWLOOP"
|
"!TARGET_NHWLOOP"
|
"bcnz %1"
|
"bcnz %1"
|
[(set_attr "type" "branch")])
|
[(set_attr "type" "branch")])
|
|
|