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[/] [openrisc/] [trunk/] [gnu-src/] [gcc-4.2.2/] [gcc/] [config/] [score/] [score7.md] - Diff between revs 38 and 154

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;;  Machine description for Sunplus S+CORE
;;  Machine description for Sunplus S+CORE
;;  Sunplus S+CORE 7 Pipeline Description
;;  Sunplus S+CORE 7 Pipeline Description
;;  Copyright (C) 2005, 2007
;;  Copyright (C) 2005, 2007
;;  Free Software Foundation, Inc.
;;  Free Software Foundation, Inc.
;;  Contributed by Sunnorth.
;;  Contributed by Sunnorth.
;; This file is part of GCC.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; along with GCC; see the file COPYING3.  If not see
;; .
;; .
(define_automaton "score")
(define_automaton "score")
(define_cpu_unit "core" "score")
(define_cpu_unit "core" "score")
(define_insn_reservation "memory" 3
(define_insn_reservation "memory" 3
                         (eq_attr "type" "load")
                         (eq_attr "type" "load")
                         "core")
                         "core")
(define_insn_reservation "mul" 3
(define_insn_reservation "mul" 3
                         (eq_attr "type" "mul,div")
                         (eq_attr "type" "mul,div")
                         "core")
                         "core")
(define_insn_reservation "fce" 1
(define_insn_reservation "fce" 1
                         (eq_attr "type" "fce")
                         (eq_attr "type" "fce")
                         "core")
                         "core")
(define_insn_reservation "tsr" 1
(define_insn_reservation "tsr" 1
                         (eq_attr "type" "tsr,fsr")
                         (eq_attr "type" "tsr,fsr")
                         "core")
                         "core")
(define_insn_reservation "up_c" 1
(define_insn_reservation "up_c" 1
                         (eq_attr "up_c" "yes")
                         (eq_attr "up_c" "yes")
                         "core")
                         "core")
 
 

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