;; Predicate definitions for Renesas / SuperH SH.
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;; Predicate definitions for Renesas / SuperH SH.
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;; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "trapping_target_operand"
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(define_predicate "trapping_target_operand"
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(match_code "if_then_else")
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(match_code "if_then_else")
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{
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{
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rtx cond, mem, res, tar, and;
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rtx cond, mem, res, tar, and;
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if (GET_MODE (op) != PDImode)
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if (GET_MODE (op) != PDImode)
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return 0;
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return 0;
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cond = XEXP (op, 0);
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cond = XEXP (op, 0);
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mem = XEXP (op, 1);
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mem = XEXP (op, 1);
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res = XEXP (op, 2);
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res = XEXP (op, 2);
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if (GET_CODE (mem) != MEM
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if (GET_CODE (mem) != MEM
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|| (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
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|| (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
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return 0;
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return 0;
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tar = XEXP (res, 0);
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tar = XEXP (res, 0);
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if (!rtx_equal_p (XEXP (mem, 0), tar)
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if (!rtx_equal_p (XEXP (mem, 0), tar)
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|| GET_MODE (tar) != Pmode)
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|| GET_MODE (tar) != Pmode)
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return 0;
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return 0;
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if (GET_CODE (cond) == CONST)
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if (GET_CODE (cond) == CONST)
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{
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{
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cond = XEXP (cond, 0);
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cond = XEXP (cond, 0);
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if (!EXTRA_CONSTRAINT_Csy (tar))
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if (!EXTRA_CONSTRAINT_Csy (tar))
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return 0;
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return 0;
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if (GET_CODE (tar) == CONST)
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if (GET_CODE (tar) == CONST)
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tar = XEXP (tar, 0);
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tar = XEXP (tar, 0);
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}
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}
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else if (!arith_reg_operand (tar, VOIDmode)
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else if (!arith_reg_operand (tar, VOIDmode)
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&& ! EXTRA_CONSTRAINT_Csy (tar))
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&& ! EXTRA_CONSTRAINT_Csy (tar))
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return 0;
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return 0;
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if (GET_CODE (cond) != EQ)
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if (GET_CODE (cond) != EQ)
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return 0;
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return 0;
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and = XEXP (cond, 0);
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and = XEXP (cond, 0);
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return (GET_CODE (and) == AND
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return (GET_CODE (and) == AND
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&& rtx_equal_p (XEXP (and, 0), tar)
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&& rtx_equal_p (XEXP (and, 0), tar)
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&& GET_CODE (XEXP (and, 1)) == CONST_INT
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&& GET_CODE (XEXP (and, 1)) == CONST_INT
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&& GET_CODE (XEXP (cond, 1)) == CONST_INT
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&& GET_CODE (XEXP (cond, 1)) == CONST_INT
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&& INTVAL (XEXP (and, 1)) == 3
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&& INTVAL (XEXP (and, 1)) == 3
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&& INTVAL (XEXP (cond, 1)) == 3);
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&& INTVAL (XEXP (cond, 1)) == 3);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "and_operand"
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(define_predicate "and_operand"
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(match_code "subreg,reg,const_int")
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(match_code "subreg,reg,const_int")
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{
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{
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if (logical_operand (op, mode))
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if (logical_operand (op, mode))
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return 1;
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return 1;
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/* Check mshflo.l / mshflhi.l opportunities. */
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/* Check mshflo.l / mshflhi.l opportunities. */
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if (TARGET_SHMEDIA
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if (TARGET_SHMEDIA
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&& mode == DImode
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&& mode == DImode
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&& GET_CODE (op) == CONST_INT
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&& GET_CODE (op) == CONST_INT
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&& CONST_OK_FOR_J16 (INTVAL (op)))
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&& CONST_OK_FOR_J16 (INTVAL (op)))
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; Like arith_reg_dest, but this predicate is defined with
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;; Like arith_reg_dest, but this predicate is defined with
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;; define_special_predicate, not define_predicate.
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;; define_special_predicate, not define_predicate.
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(define_special_predicate "any_arith_reg_dest"
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(define_special_predicate "any_arith_reg_dest"
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(match_code "subreg,reg")
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(match_code "subreg,reg")
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{
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{
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return arith_reg_dest (op, mode);
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return arith_reg_dest (op, mode);
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})
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})
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;; Like register_operand, but this predicate is defined with
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;; Like register_operand, but this predicate is defined with
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;; define_special_predicate, not define_predicate.
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;; define_special_predicate, not define_predicate.
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(define_special_predicate "any_register_operand"
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(define_special_predicate "any_register_operand"
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(match_code "subreg,reg")
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(match_code "subreg,reg")
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{
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{
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return register_operand (op, mode);
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return register_operand (op, mode);
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})
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})
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;; Returns 1 if OP is a valid source operand for an arithmetic insn.
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;; Returns 1 if OP is a valid source operand for an arithmetic insn.
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(define_predicate "arith_operand"
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(define_predicate "arith_operand"
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(match_code "subreg,reg,const_int,truncate")
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(match_code "subreg,reg,const_int,truncate")
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{
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{
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if (arith_reg_operand (op, mode))
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if (arith_reg_operand (op, mode))
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return 1;
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return 1;
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if (TARGET_SHMEDIA)
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if (TARGET_SHMEDIA)
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{
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{
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/* FIXME: We should be checking whether the CONST_INT fits in a
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/* FIXME: We should be checking whether the CONST_INT fits in a
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CONST_OK_FOR_I16 here, but this causes reload_cse to crash when
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CONST_OK_FOR_I16 here, but this causes reload_cse to crash when
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attempting to transform a sequence of two 64-bit sets of the
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attempting to transform a sequence of two 64-bit sets of the
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same register from literal constants into a set and an add,
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same register from literal constants into a set and an add,
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when the difference is too wide for an add. */
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when the difference is too wide for an add. */
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if (GET_CODE (op) == CONST_INT
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if (GET_CODE (op) == CONST_INT
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|| EXTRA_CONSTRAINT_Css (op))
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|| EXTRA_CONSTRAINT_Css (op))
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return 1;
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return 1;
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else if (GET_CODE (op) == TRUNCATE
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else if (GET_CODE (op) == TRUNCATE
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&& ! system_reg_operand (XEXP (op, 0), VOIDmode)
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&& ! system_reg_operand (XEXP (op, 0), VOIDmode)
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&& (mode == VOIDmode || mode == GET_MODE (op))
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&& (mode == VOIDmode || mode == GET_MODE (op))
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&& (GET_MODE_SIZE (GET_MODE (op))
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&& (GET_MODE_SIZE (GET_MODE (op))
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< GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
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< GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
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&& (! FP_REGISTER_P (REGNO (XEXP (op, 0)))
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&& (! FP_REGISTER_P (REGNO (XEXP (op, 0)))
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|| GET_MODE_SIZE (GET_MODE (op)) == 4))
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|| GET_MODE_SIZE (GET_MODE (op)) == 4))
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return register_operand (XEXP (op, 0), VOIDmode);
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return register_operand (XEXP (op, 0), VOIDmode);
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else
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else
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return 0;
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return 0;
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}
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}
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else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (op)))
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else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (op)))
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; Like above, but for DImode destinations: forbid paradoxical DImode
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;; Like above, but for DImode destinations: forbid paradoxical DImode
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;; subregs, because this would lead to missing sign extensions when
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;; subregs, because this would lead to missing sign extensions when
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;; truncating from DImode to SImode.
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;; truncating from DImode to SImode.
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(define_predicate "arith_reg_dest"
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(define_predicate "arith_reg_dest"
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(match_code "subreg,reg")
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(match_code "subreg,reg")
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{
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{
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if (mode == DImode && GET_CODE (op) == SUBREG
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if (mode == DImode && GET_CODE (op) == SUBREG
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&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
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&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
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&& TARGET_SHMEDIA)
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&& TARGET_SHMEDIA)
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return 0;
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return 0;
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return arith_reg_operand (op, mode);
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return arith_reg_operand (op, mode);
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})
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})
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;; Returns 1 if OP is a normal arithmetic register.
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;; Returns 1 if OP is a normal arithmetic register.
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(define_predicate "arith_reg_operand"
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(define_predicate "arith_reg_operand"
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(match_code "subreg,reg,sign_extend")
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(match_code "subreg,reg,sign_extend")
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{
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{
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if (register_operand (op, mode))
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if (register_operand (op, mode))
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{
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{
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int regno;
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int regno;
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if (GET_CODE (op) == REG)
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if (GET_CODE (op) == REG)
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regno = REGNO (op);
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regno = REGNO (op);
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else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
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else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
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regno = REGNO (SUBREG_REG (op));
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regno = REGNO (SUBREG_REG (op));
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else
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else
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return 1;
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return 1;
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return (regno != T_REG && regno != PR_REG
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return (regno != T_REG && regno != PR_REG
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&& ! TARGET_REGISTER_P (regno)
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&& ! TARGET_REGISTER_P (regno)
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&& (regno != FPUL_REG || TARGET_SH4)
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&& (regno != FPUL_REG || TARGET_SH4)
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&& regno != MACH_REG && regno != MACL_REG);
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&& regno != MACH_REG && regno != MACL_REG);
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}
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}
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/* Allow a no-op sign extension - compare LOAD_EXTEND_OP.
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/* Allow a no-op sign extension - compare LOAD_EXTEND_OP.
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We allow SImode here, as not using an FP register is just a matter of
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We allow SImode here, as not using an FP register is just a matter of
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proper register allocation. */
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proper register allocation. */
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if (TARGET_SHMEDIA
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if (TARGET_SHMEDIA
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&& GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND
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&& GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND
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&& GET_MODE (XEXP (op, 0)) == SImode
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&& GET_MODE (XEXP (op, 0)) == SImode
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&& GET_CODE (XEXP (op, 0)) != SUBREG)
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&& GET_CODE (XEXP (op, 0)) != SUBREG)
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return register_operand (XEXP (op, 0), VOIDmode);
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return register_operand (XEXP (op, 0), VOIDmode);
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#if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */
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#if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */
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if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
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if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
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&& GET_MODE (XEXP (op, 0)) == HImode
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&& GET_MODE (XEXP (op, 0)) == HImode
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&& GET_CODE (XEXP (op, 0)) == REG
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&& GET_CODE (XEXP (op, 0)) == REG
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&& REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
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&& REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
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return register_operand (XEXP (op, 0), VOIDmode);
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return register_operand (XEXP (op, 0), VOIDmode);
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#endif
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#endif
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if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
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if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
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&& GET_CODE (op) == SUBREG
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&& GET_CODE (op) == SUBREG
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&& GET_MODE (SUBREG_REG (op)) == DImode
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&& GET_MODE (SUBREG_REG (op)) == DImode
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&& GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
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&& GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
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&& GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
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&& GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
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&& GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
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&& GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
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return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
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return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
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return 0;
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return 0;
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})
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})
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;; Returns 1 if OP is a valid source operand for a compare insn.
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;; Returns 1 if OP is a valid source operand for a compare insn.
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(define_predicate "arith_reg_or_0_operand"
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(define_predicate "arith_reg_or_0_operand"
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(match_code "subreg,reg,const_int,const_vector")
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(match_code "subreg,reg,const_int,const_vector")
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{
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{
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if (arith_reg_operand (op, mode))
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if (arith_reg_operand (op, mode))
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return 1;
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return 1;
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if (EXTRA_CONSTRAINT_Z (op))
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if (EXTRA_CONSTRAINT_Z (op))
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return 1;
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return 1;
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return 0;
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return 0;
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "binary_float_operator"
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(define_predicate "binary_float_operator"
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(and (match_code "plus,minus,mult,div")
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(and (match_code "plus,minus,mult,div")
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(match_test "GET_MODE (op) == mode")))
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(match_test "GET_MODE (op) == mode")))
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "binary_logical_operator"
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(define_predicate "binary_logical_operator"
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(and (match_code "and,ior,xor")
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(and (match_code "and,ior,xor")
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(match_test "GET_MODE (op) == mode")))
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(match_test "GET_MODE (op) == mode")))
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;; Return 1 of OP is an address suitable for a cache manipulation operation.
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;; Return 1 of OP is an address suitable for a cache manipulation operation.
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;; MODE has the meaning as in address_operand.
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;; MODE has the meaning as in address_operand.
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(define_special_predicate "cache_address_operand"
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(define_special_predicate "cache_address_operand"
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(match_code "plus,reg")
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(match_code "plus,reg")
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{
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{
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if (GET_CODE (op) == PLUS)
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if (GET_CODE (op) == PLUS)
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{
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{
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if (GET_CODE (XEXP (op, 0)) != REG)
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if (GET_CODE (XEXP (op, 0)) != REG)
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return 0;
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return 0;
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if (GET_CODE (XEXP (op, 1)) != CONST_INT
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if (GET_CODE (XEXP (op, 1)) != CONST_INT
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|| (INTVAL (XEXP (op, 1)) & 31))
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|| (INTVAL (XEXP (op, 1)) & 31))
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return 0;
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return 0;
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}
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}
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else if (GET_CODE (op) != REG)
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else if (GET_CODE (op) != REG)
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return 0;
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return 0;
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return address_operand (op, mode);
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return address_operand (op, mode);
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})
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})
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;; Return 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
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;; Return 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
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(define_predicate "cmp_operand"
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(define_predicate "cmp_operand"
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(match_code "subreg,reg,const_int")
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(match_code "subreg,reg,const_int")
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{
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{
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
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if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_N (INTVAL (op)))
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return 1;
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return 1;
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if (TARGET_SHMEDIA
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if (TARGET_SHMEDIA
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&& mode != DImode && GET_CODE (op) == SUBREG
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&& mode != DImode && GET_CODE (op) == SUBREG
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&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
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&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
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return 0;
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return 0;
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return arith_reg_operand (op, mode);
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return arith_reg_operand (op, mode);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "cmpsi_operand"
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(define_predicate "cmpsi_operand"
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(match_code "subreg,reg,const_int")
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(match_code "subreg,reg,const_int")
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{
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{
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if (GET_CODE (op) == REG && REGNO (op) == T_REG
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if (GET_CODE (op) == REG && REGNO (op) == T_REG
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&& GET_MODE (op) == SImode
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&& GET_MODE (op) == SImode
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&& TARGET_SH1)
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&& TARGET_SH1)
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return 1;
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return 1;
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return arith_operand (op, mode);
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return arith_operand (op, mode);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "commutative_float_operator"
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(define_predicate "commutative_float_operator"
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(and (match_code "plus,mult")
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(and (match_code "plus,mult")
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(match_test "GET_MODE (op) == mode")))
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(match_test "GET_MODE (op) == mode")))
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "equality_comparison_operator"
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(define_predicate "equality_comparison_operator"
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(match_code "eq,ne"))
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(match_code "eq,ne"))
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "extend_reg_operand"
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(define_predicate "extend_reg_operand"
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(match_code "subreg,reg,truncate")
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(match_code "subreg,reg,truncate")
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{
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{
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return (GET_CODE (op) == TRUNCATE
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return (GET_CODE (op) == TRUNCATE
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? arith_operand
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? arith_operand
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: arith_reg_operand) (op, mode);
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: arith_reg_operand) (op, mode);
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})
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})
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;; TODO: Add a comment here.
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;; TODO: Add a comment here.
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(define_predicate "extend_reg_or_0_operand"
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(define_predicate "extend_reg_or_0_operand"
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(match_code "subreg,reg,truncate,const_int")
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(match_code "subreg,reg,truncate,const_int")
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{
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{
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return (GET_CODE (op) == TRUNCATE
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return (GET_CODE (op) == TRUNCATE
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? arith_operand
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? arith_operand
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: arith_reg_or_0_operand) (op, mode);
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: arith_reg_or_0_operand) (op, mode);
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})
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})
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;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
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;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
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|
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(define_predicate "ext_dest_operand"
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(define_predicate "ext_dest_operand"
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(match_code "subreg,reg")
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(match_code "subreg,reg")
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{
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{
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return arith_reg_operand (op, mode);
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return arith_reg_operand (op, mode);
|
})
|
})
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;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "fp_arith_reg_dest"
|
(define_predicate "fp_arith_reg_dest"
|
(match_code "subreg,reg")
|
(match_code "subreg,reg")
|
{
|
{
|
if (mode == DImode && GET_CODE (op) == SUBREG
|
if (mode == DImode && GET_CODE (op) == SUBREG
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
|
return 0;
|
return 0;
|
return fp_arith_reg_operand (op, mode);
|
return fp_arith_reg_operand (op, mode);
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "fp_arith_reg_operand"
|
(define_predicate "fp_arith_reg_operand"
|
(match_code "subreg,reg")
|
(match_code "subreg,reg")
|
{
|
{
|
if (register_operand (op, mode))
|
if (register_operand (op, mode))
|
{
|
{
|
int regno;
|
int regno;
|
|
|
if (GET_CODE (op) == REG)
|
if (GET_CODE (op) == REG)
|
regno = REGNO (op);
|
regno = REGNO (op);
|
else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
|
else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
|
regno = REGNO (SUBREG_REG (op));
|
regno = REGNO (SUBREG_REG (op));
|
else
|
else
|
return 1;
|
return 1;
|
|
|
return (regno >= FIRST_PSEUDO_REGISTER
|
return (regno >= FIRST_PSEUDO_REGISTER
|
|| FP_REGISTER_P (regno));
|
|| FP_REGISTER_P (regno));
|
}
|
}
|
return 0;
|
return 0;
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "fpscr_operand"
|
(define_predicate "fpscr_operand"
|
(match_code "reg")
|
(match_code "reg")
|
{
|
{
|
return (GET_CODE (op) == REG
|
return (GET_CODE (op) == REG
|
&& (REGNO (op) == FPSCR_REG
|
&& (REGNO (op) == FPSCR_REG
|
|| (REGNO (op) >= FIRST_PSEUDO_REGISTER
|
|| (REGNO (op) >= FIRST_PSEUDO_REGISTER
|
&& !(reload_in_progress || reload_completed)))
|
&& !(reload_in_progress || reload_completed)))
|
&& GET_MODE (op) == PSImode);
|
&& GET_MODE (op) == PSImode);
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "fpul_operand"
|
(define_predicate "fpul_operand"
|
(match_code "reg")
|
(match_code "reg")
|
{
|
{
|
if (TARGET_SHMEDIA)
|
if (TARGET_SHMEDIA)
|
return fp_arith_reg_operand (op, mode);
|
return fp_arith_reg_operand (op, mode);
|
|
|
return (GET_CODE (op) == REG
|
return (GET_CODE (op) == REG
|
&& (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
|
&& (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
|
&& GET_MODE (op) == mode);
|
&& GET_MODE (op) == mode);
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "general_extend_operand"
|
(define_predicate "general_extend_operand"
|
(match_code "subreg,reg,mem,truncate")
|
(match_code "subreg,reg,mem,truncate")
|
{
|
{
|
return (GET_CODE (op) == TRUNCATE
|
return (GET_CODE (op) == TRUNCATE
|
? arith_operand
|
? arith_operand
|
: nonimmediate_operand) (op, mode);
|
: nonimmediate_operand) (op, mode);
|
})
|
})
|
|
|
;; Returns 1 if OP can be source of a simple move operation. Same as
|
;; Returns 1 if OP can be source of a simple move operation. Same as
|
;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
|
;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
|
;; are subregs of system registers.
|
;; are subregs of system registers.
|
|
|
(define_predicate "general_movsrc_operand"
|
(define_predicate "general_movsrc_operand"
|
(match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
|
(match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
|
{
|
{
|
if (GET_CODE (op) == MEM)
|
if (GET_CODE (op) == MEM)
|
{
|
{
|
rtx inside = XEXP (op, 0);
|
rtx inside = XEXP (op, 0);
|
if (GET_CODE (inside) == CONST)
|
if (GET_CODE (inside) == CONST)
|
inside = XEXP (inside, 0);
|
inside = XEXP (inside, 0);
|
|
|
if (GET_CODE (inside) == LABEL_REF)
|
if (GET_CODE (inside) == LABEL_REF)
|
return 1;
|
return 1;
|
|
|
if (GET_CODE (inside) == PLUS
|
if (GET_CODE (inside) == PLUS
|
&& GET_CODE (XEXP (inside, 0)) == LABEL_REF
|
&& GET_CODE (XEXP (inside, 0)) == LABEL_REF
|
&& GET_CODE (XEXP (inside, 1)) == CONST_INT)
|
&& GET_CODE (XEXP (inside, 1)) == CONST_INT)
|
return 1;
|
return 1;
|
|
|
/* Only post inc allowed. */
|
/* Only post inc allowed. */
|
if (GET_CODE (inside) == PRE_DEC)
|
if (GET_CODE (inside) == PRE_DEC)
|
return 0;
|
return 0;
|
}
|
}
|
|
|
if ((mode == QImode || mode == HImode)
|
if ((mode == QImode || mode == HImode)
|
&& (GET_CODE (op) == SUBREG
|
&& (GET_CODE (op) == SUBREG
|
&& GET_CODE (XEXP (op, 0)) == REG
|
&& GET_CODE (XEXP (op, 0)) == REG
|
&& system_reg_operand (XEXP (op, 0), mode)))
|
&& system_reg_operand (XEXP (op, 0), mode)))
|
return 0;
|
return 0;
|
|
|
if (TARGET_SHMEDIA
|
if (TARGET_SHMEDIA
|
&& (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
|
&& (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
|
&& sh_rep_vec (op, mode))
|
&& sh_rep_vec (op, mode))
|
return 1;
|
return 1;
|
if (TARGET_SHMEDIA && 1
|
if (TARGET_SHMEDIA && 1
|
&& GET_CODE (op) == SUBREG && GET_MODE (op) == mode
|
&& GET_CODE (op) == SUBREG && GET_MODE (op) == mode
|
&& SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op))
|
&& SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op))
|
/* FIXME */ abort (); /* return 1; */
|
/* FIXME */ abort (); /* return 1; */
|
return general_operand (op, mode);
|
return general_operand (op, mode);
|
})
|
})
|
|
|
;; Returns 1 if OP can be a destination of a move. Same as
|
;; Returns 1 if OP can be a destination of a move. Same as
|
;; general_operand, but no preinc allowed.
|
;; general_operand, but no preinc allowed.
|
|
|
(define_predicate "general_movdst_operand"
|
(define_predicate "general_movdst_operand"
|
(match_code "subreg,reg,mem")
|
(match_code "subreg,reg,mem")
|
{
|
{
|
/* Only pre dec allowed. */
|
/* Only pre dec allowed. */
|
if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
|
if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
|
return 0;
|
return 0;
|
if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
|
if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
|
&& ! (high_life_started || reload_completed))
|
&& ! (high_life_started || reload_completed))
|
return 0;
|
return 0;
|
|
|
return general_operand (op, mode);
|
return general_operand (op, mode);
|
})
|
})
|
|
|
;; Returns 1 if OP is a MEM that can be source of a simple move operation.
|
;; Returns 1 if OP is a MEM that can be source of a simple move operation.
|
|
|
(define_predicate "unaligned_load_operand"
|
(define_predicate "unaligned_load_operand"
|
(match_code "mem")
|
(match_code "mem")
|
{
|
{
|
rtx inside;
|
rtx inside;
|
|
|
if (GET_CODE (op) != MEM || GET_MODE (op) != mode)
|
if (GET_CODE (op) != MEM || GET_MODE (op) != mode)
|
return 0;
|
return 0;
|
|
|
inside = XEXP (op, 0);
|
inside = XEXP (op, 0);
|
|
|
if (GET_CODE (inside) == POST_INC)
|
if (GET_CODE (inside) == POST_INC)
|
inside = XEXP (inside, 0);
|
inside = XEXP (inside, 0);
|
|
|
if (GET_CODE (inside) == REG)
|
if (GET_CODE (inside) == REG)
|
return 1;
|
return 1;
|
|
|
return 0;
|
return 0;
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "greater_comparison_operator"
|
(define_predicate "greater_comparison_operator"
|
(match_code "gt,ge,gtu,geu"))
|
(match_code "gt,ge,gtu,geu"))
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "inqhi_operand"
|
(define_predicate "inqhi_operand"
|
(match_code "truncate")
|
(match_code "truncate")
|
{
|
{
|
if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
|
if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
|
return 0;
|
return 0;
|
op = XEXP (op, 0);
|
op = XEXP (op, 0);
|
/* Can't use true_regnum here because copy_cost wants to know about
|
/* Can't use true_regnum here because copy_cost wants to know about
|
SECONDARY_INPUT_RELOAD_CLASS. */
|
SECONDARY_INPUT_RELOAD_CLASS. */
|
return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
|
return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_special_predicate "int_gpr_dest"
|
(define_special_predicate "int_gpr_dest"
|
(match_code "subreg,reg")
|
(match_code "subreg,reg")
|
{
|
{
|
enum machine_mode op_mode = GET_MODE (op);
|
enum machine_mode op_mode = GET_MODE (op);
|
|
|
if (GET_MODE_CLASS (op_mode) != MODE_INT
|
if (GET_MODE_CLASS (op_mode) != MODE_INT
|
|| GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
|
|| GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
|
return 0;
|
return 0;
|
if (! reload_completed)
|
if (! reload_completed)
|
return 0;
|
return 0;
|
return true_regnum (op) <= LAST_GENERAL_REG;
|
return true_regnum (op) <= LAST_GENERAL_REG;
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "less_comparison_operator"
|
(define_predicate "less_comparison_operator"
|
(match_code "lt,le,ltu,leu"))
|
(match_code "lt,le,ltu,leu"))
|
|
|
;; Returns 1 if OP is a valid source operand for a logical operation.
|
;; Returns 1 if OP is a valid source operand for a logical operation.
|
|
|
(define_predicate "logical_operand"
|
(define_predicate "logical_operand"
|
(match_code "subreg,reg,const_int")
|
(match_code "subreg,reg,const_int")
|
{
|
{
|
if (TARGET_SHMEDIA
|
if (TARGET_SHMEDIA
|
&& mode != DImode && GET_CODE (op) == SUBREG
|
&& mode != DImode && GET_CODE (op) == SUBREG
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
|
return 0;
|
return 0;
|
|
|
if (arith_reg_operand (op, mode))
|
if (arith_reg_operand (op, mode))
|
return 1;
|
return 1;
|
|
|
if (TARGET_SHMEDIA)
|
if (TARGET_SHMEDIA)
|
{
|
{
|
if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I10 (INTVAL (op)))
|
if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I10 (INTVAL (op)))
|
return 1;
|
return 1;
|
else
|
else
|
return 0;
|
return 0;
|
}
|
}
|
else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K08 (INTVAL (op)))
|
else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K08 (INTVAL (op)))
|
return 1;
|
return 1;
|
|
|
return 0;
|
return 0;
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "logical_operator"
|
(define_predicate "logical_operator"
|
(match_code "and,ior,xor"))
|
(match_code "and,ior,xor"))
|
|
|
;; Like arith_reg_operand, but for register source operands of narrow
|
;; Like arith_reg_operand, but for register source operands of narrow
|
;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
|
;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
|
|
|
(define_predicate "logical_reg_operand"
|
(define_predicate "logical_reg_operand"
|
(match_code "subreg,reg")
|
(match_code "subreg,reg")
|
{
|
{
|
if (TARGET_SHMEDIA
|
if (TARGET_SHMEDIA
|
&& GET_CODE (op) == SUBREG
|
&& GET_CODE (op) == SUBREG
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4
|
&& mode != DImode)
|
&& mode != DImode)
|
return 0;
|
return 0;
|
return arith_reg_operand (op, mode);
|
return arith_reg_operand (op, mode);
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "mextr_bit_offset"
|
(define_predicate "mextr_bit_offset"
|
(match_code "const_int")
|
(match_code "const_int")
|
{
|
{
|
HOST_WIDE_INT i;
|
HOST_WIDE_INT i;
|
|
|
if (GET_CODE (op) != CONST_INT)
|
if (GET_CODE (op) != CONST_INT)
|
return 0;
|
return 0;
|
i = INTVAL (op);
|
i = INTVAL (op);
|
return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
|
return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "minuend_operand"
|
(define_predicate "minuend_operand"
|
(match_code "subreg,reg,truncate,const_int")
|
(match_code "subreg,reg,truncate,const_int")
|
{
|
{
|
return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
|
return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "noncommutative_float_operator"
|
(define_predicate "noncommutative_float_operator"
|
(and (match_code "minus,div")
|
(and (match_code "minus,div")
|
(match_test "GET_MODE (op) == mode")))
|
(match_test "GET_MODE (op) == mode")))
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "sh_const_vec"
|
(define_predicate "sh_const_vec"
|
(match_code "const_vector")
|
(match_code "const_vector")
|
{
|
{
|
int i;
|
int i;
|
|
|
if (GET_CODE (op) != CONST_VECTOR
|
if (GET_CODE (op) != CONST_VECTOR
|
|| (GET_MODE (op) != mode && mode != VOIDmode))
|
|| (GET_MODE (op) != mode && mode != VOIDmode))
|
return 0;
|
return 0;
|
i = XVECLEN (op, 0) - 1;
|
i = XVECLEN (op, 0) - 1;
|
for (; i >= 0; i--)
|
for (; i >= 0; i--)
|
if (GET_CODE (XVECEXP (op, 0, i)) != CONST_INT)
|
if (GET_CODE (XVECEXP (op, 0, i)) != CONST_INT)
|
return 0;
|
return 0;
|
return 1;
|
return 1;
|
})
|
})
|
|
|
;; Determine if OP is a constant vector matching MODE with only one
|
;; Determine if OP is a constant vector matching MODE with only one
|
;; element that is not a sign extension. Two byte-sized elements
|
;; element that is not a sign extension. Two byte-sized elements
|
;; count as one.
|
;; count as one.
|
|
|
(define_predicate "sh_1el_vec"
|
(define_predicate "sh_1el_vec"
|
(match_code "const_vector")
|
(match_code "const_vector")
|
{
|
{
|
int unit_size;
|
int unit_size;
|
int i, last, least, sign_ix;
|
int i, last, least, sign_ix;
|
rtx sign;
|
rtx sign;
|
|
|
if (GET_CODE (op) != CONST_VECTOR
|
if (GET_CODE (op) != CONST_VECTOR
|
|| (GET_MODE (op) != mode && mode != VOIDmode))
|
|| (GET_MODE (op) != mode && mode != VOIDmode))
|
return 0;
|
return 0;
|
/* Determine numbers of last and of least significant elements. */
|
/* Determine numbers of last and of least significant elements. */
|
last = XVECLEN (op, 0) - 1;
|
last = XVECLEN (op, 0) - 1;
|
least = TARGET_LITTLE_ENDIAN ? 0 : last;
|
least = TARGET_LITTLE_ENDIAN ? 0 : last;
|
if (GET_CODE (XVECEXP (op, 0, least)) != CONST_INT)
|
if (GET_CODE (XVECEXP (op, 0, least)) != CONST_INT)
|
return 0;
|
return 0;
|
sign_ix = least;
|
sign_ix = least;
|
if (GET_MODE_UNIT_SIZE (mode) == 1)
|
if (GET_MODE_UNIT_SIZE (mode) == 1)
|
sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
|
sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
|
if (GET_CODE (XVECEXP (op, 0, sign_ix)) != CONST_INT)
|
if (GET_CODE (XVECEXP (op, 0, sign_ix)) != CONST_INT)
|
return 0;
|
return 0;
|
unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
|
unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
|
sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
|
sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
|
? constm1_rtx : const0_rtx);
|
? constm1_rtx : const0_rtx);
|
i = XVECLEN (op, 0) - 1;
|
i = XVECLEN (op, 0) - 1;
|
do
|
do
|
if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
|
if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
|
return 0;
|
return 0;
|
while (--i);
|
while (--i);
|
return 1;
|
return 1;
|
})
|
})
|
|
|
;; Like register_operand, but take into account that SHMEDIA can use
|
;; Like register_operand, but take into account that SHMEDIA can use
|
;; the constant zero like a general register.
|
;; the constant zero like a general register.
|
|
|
(define_predicate "sh_register_operand"
|
(define_predicate "sh_register_operand"
|
(match_code "reg,subreg,const_int,const_double")
|
(match_code "reg,subreg,const_int,const_double")
|
{
|
{
|
if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
|
if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
|
return 1;
|
return 1;
|
return register_operand (op, mode);
|
return register_operand (op, mode);
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "sh_rep_vec"
|
(define_predicate "sh_rep_vec"
|
(match_code "const_vector,parallel")
|
(match_code "const_vector,parallel")
|
{
|
{
|
int i;
|
int i;
|
rtx x, y;
|
rtx x, y;
|
|
|
if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
|
if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
|
|| (GET_MODE (op) != mode && mode != VOIDmode))
|
|| (GET_MODE (op) != mode && mode != VOIDmode))
|
return 0;
|
return 0;
|
i = XVECLEN (op, 0) - 2;
|
i = XVECLEN (op, 0) - 2;
|
x = XVECEXP (op, 0, i + 1);
|
x = XVECEXP (op, 0, i + 1);
|
if (GET_MODE_UNIT_SIZE (mode) == 1)
|
if (GET_MODE_UNIT_SIZE (mode) == 1)
|
{
|
{
|
y = XVECEXP (op, 0, i);
|
y = XVECEXP (op, 0, i);
|
for (i -= 2; i >= 0; i -= 2)
|
for (i -= 2; i >= 0; i -= 2)
|
if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
|
if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
|
|| ! rtx_equal_p (XVECEXP (op, 0, i), y))
|
|| ! rtx_equal_p (XVECEXP (op, 0, i), y))
|
return 0;
|
return 0;
|
}
|
}
|
else
|
else
|
for (; i >= 0; i--)
|
for (; i >= 0; i--)
|
if (XVECEXP (op, 0, i) != x)
|
if (XVECEXP (op, 0, i) != x)
|
return 0;
|
return 0;
|
return 1;
|
return 1;
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "shift_count_operand"
|
(define_predicate "shift_count_operand"
|
(match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend")
|
(match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend")
|
{
|
{
|
return (CONSTANT_P (op)
|
return (CONSTANT_P (op)
|
? (GET_CODE (op) == CONST_INT
|
? (GET_CODE (op) == CONST_INT
|
? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
|
? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
|
: nonmemory_operand (op, mode))
|
: nonmemory_operand (op, mode))
|
: shift_count_reg_operand (op, mode));
|
: shift_count_reg_operand (op, mode));
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "shift_count_reg_operand"
|
(define_predicate "shift_count_reg_operand"
|
(match_code "subreg,reg,zero_extend,sign_extend")
|
(match_code "subreg,reg,zero_extend,sign_extend")
|
{
|
{
|
if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
|
if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
|
|| (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0))
|
|| (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0))
|
&& (mode == VOIDmode || mode == GET_MODE (op))
|
&& (mode == VOIDmode || mode == GET_MODE (op))
|
&& GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
|
&& GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
|
&& GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT)
|
&& GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT)
|
{
|
{
|
mode = VOIDmode;
|
mode = VOIDmode;
|
do
|
do
|
op = XEXP (op, 0);
|
op = XEXP (op, 0);
|
while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
|
while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
|
|| GET_CODE (op) == TRUNCATE)
|
|| GET_CODE (op) == TRUNCATE)
|
&& GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
|
&& GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
|
&& GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT);
|
&& GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT);
|
|
|
}
|
}
|
return arith_reg_operand (op, mode);
|
return arith_reg_operand (op, mode);
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "shift_operator"
|
(define_predicate "shift_operator"
|
(match_code "ashift,ashiftrt,lshiftrt"))
|
(match_code "ashift,ashiftrt,lshiftrt"))
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "symbol_ref_operand"
|
(define_predicate "symbol_ref_operand"
|
(match_code "symbol_ref"))
|
(match_code "symbol_ref"))
|
|
|
;; Same as target_reg_operand, except that label_refs and symbol_refs
|
;; Same as target_reg_operand, except that label_refs and symbol_refs
|
;; are accepted before reload.
|
;; are accepted before reload.
|
|
|
(define_special_predicate "target_operand"
|
(define_special_predicate "target_operand"
|
(match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
|
(match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
|
{
|
{
|
if (mode != VOIDmode && mode != Pmode)
|
if (mode != VOIDmode && mode != Pmode)
|
return 0;
|
return 0;
|
|
|
if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode)
|
if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode)
|
&& EXTRA_CONSTRAINT_Csy (op))
|
&& EXTRA_CONSTRAINT_Csy (op))
|
return ! reload_completed;
|
return ! reload_completed;
|
|
|
return target_reg_operand (op, mode);
|
return target_reg_operand (op, mode);
|
})
|
})
|
|
|
;; Accept pseudos and branch target registers.
|
;; Accept pseudos and branch target registers.
|
|
|
(define_special_predicate "target_reg_operand"
|
(define_special_predicate "target_reg_operand"
|
(match_code "subreg,reg")
|
(match_code "subreg,reg")
|
{
|
{
|
if (mode == VOIDmode
|
if (mode == VOIDmode
|
? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode
|
? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode
|
: mode != GET_MODE (op))
|
: mode != GET_MODE (op))
|
return 0;
|
return 0;
|
|
|
if (GET_CODE (op) == SUBREG)
|
if (GET_CODE (op) == SUBREG)
|
op = XEXP (op, 0);
|
op = XEXP (op, 0);
|
|
|
if (GET_CODE (op) != REG)
|
if (GET_CODE (op) != REG)
|
return 0;
|
return 0;
|
|
|
/* We must protect ourselves from matching pseudos that are virtual
|
/* We must protect ourselves from matching pseudos that are virtual
|
register, because they will eventually be replaced with hardware
|
register, because they will eventually be replaced with hardware
|
registers that aren't branch-target registers. */
|
registers that aren't branch-target registers. */
|
if (REGNO (op) > LAST_VIRTUAL_REGISTER
|
if (REGNO (op) > LAST_VIRTUAL_REGISTER
|
|| TARGET_REGISTER_P (REGNO (op)))
|
|| TARGET_REGISTER_P (REGNO (op)))
|
return 1;
|
return 1;
|
|
|
return 0;
|
return 0;
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_special_predicate "trunc_hi_operand"
|
(define_special_predicate "trunc_hi_operand"
|
(match_code "subreg,reg,truncate")
|
(match_code "subreg,reg,truncate")
|
{
|
{
|
enum machine_mode op_mode = GET_MODE (op);
|
enum machine_mode op_mode = GET_MODE (op);
|
|
|
if (op_mode != SImode && op_mode != DImode
|
if (op_mode != SImode && op_mode != DImode
|
&& op_mode != V4HImode && op_mode != V2SImode)
|
&& op_mode != V4HImode && op_mode != V2SImode)
|
return 0;
|
return 0;
|
return extend_reg_operand (op, mode);
|
return extend_reg_operand (op, mode);
|
})
|
})
|
|
|
;; Return 1 of OP is an address suitable for an unaligned access instruction.
|
;; Return 1 of OP is an address suitable for an unaligned access instruction.
|
|
|
(define_special_predicate "ua_address_operand"
|
(define_special_predicate "ua_address_operand"
|
(match_code "subreg,reg,plus")
|
(match_code "subreg,reg,plus")
|
{
|
{
|
if (GET_CODE (op) == PLUS
|
if (GET_CODE (op) == PLUS
|
&& (GET_CODE (XEXP (op, 1)) != CONST_INT
|
&& (GET_CODE (XEXP (op, 1)) != CONST_INT
|
|| ! CONST_OK_FOR_I06 (INTVAL (XEXP (op, 1)))))
|
|| ! CONST_OK_FOR_I06 (INTVAL (XEXP (op, 1)))))
|
return 0;
|
return 0;
|
return address_operand (op, QImode);
|
return address_operand (op, QImode);
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "ua_offset"
|
(define_predicate "ua_offset"
|
(match_code "const_int")
|
(match_code "const_int")
|
{
|
{
|
return GET_CODE (op) == CONST_INT && CONST_OK_FOR_I06 (INTVAL (op));
|
return GET_CODE (op) == CONST_INT && CONST_OK_FOR_I06 (INTVAL (op));
|
})
|
})
|
|
|
;; TODO: Add a comment here.
|
;; TODO: Add a comment here.
|
|
|
(define_predicate "unary_float_operator"
|
(define_predicate "unary_float_operator"
|
(and (match_code "abs,neg,sqrt")
|
(and (match_code "abs,neg,sqrt")
|
(match_test "GET_MODE (op) == mode")))
|
(match_test "GET_MODE (op) == mode")))
|
|
|
;; Return 1 if OP is a valid source operand for xor.
|
;; Return 1 if OP is a valid source operand for xor.
|
|
|
(define_predicate "xor_operand"
|
(define_predicate "xor_operand"
|
(match_code "subreg,reg,const_int")
|
(match_code "subreg,reg,const_int")
|
{
|
{
|
if (GET_CODE (op) == CONST_INT)
|
if (GET_CODE (op) == CONST_INT)
|
return (TARGET_SHMEDIA
|
return (TARGET_SHMEDIA
|
? (CONST_OK_FOR_I06 (INTVAL (op))
|
? (CONST_OK_FOR_I06 (INTVAL (op))
|
|| (no_new_pseudos && INTVAL (op) == 0xff))
|
|| (no_new_pseudos && INTVAL (op) == 0xff))
|
: CONST_OK_FOR_K08 (INTVAL (op)));
|
: CONST_OK_FOR_K08 (INTVAL (op)));
|
if (TARGET_SHMEDIA
|
if (TARGET_SHMEDIA
|
&& mode != DImode && GET_CODE (op) == SUBREG
|
&& mode != DImode && GET_CODE (op) == SUBREG
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
|
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
|
return 0;
|
return 0;
|
return arith_reg_operand (op, mode);
|
return arith_reg_operand (op, mode);
|
})
|
})
|
|
|
