;; XSTORMY16 Machine description template
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;; XSTORMY16 Machine description template
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;; Copyright (C) 1997, 1998, 1999, 2001, 2002, 2003, 2004, 2005, 2007
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;; Copyright (C) 1997, 1998, 1999, 2001, 2002, 2003, 2004, 2005, 2007
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;; Free Software Foundation, Inc.
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;; Free Software Foundation, Inc.
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;; Contributed by Red Hat, Inc.
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;; Contributed by Red Hat, Inc.
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;; This file is part of GCC.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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;; Constraints
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;; Constraints
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;; a $0
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;; a $0
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;; b $1
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;; b $1
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;; c $2
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;; c $2
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;; d $8
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;; d $8
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;; e $0..$7
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;; e $0..$7
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;; t $0..$1
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;; t $0..$1
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;; y Carry
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;; y Carry
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;; z $8..$9
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;; z $8..$9
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;; I 0..3
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;; I 0..3
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;; J 2**N mask
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;; J 2**N mask
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;; K 2**N antimask
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;; K 2**N antimask
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;; L 0..255
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;; L 0..255
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;; M -255..0
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;; M -255..0
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;; N -3..0
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;; N -3..0
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;; O 1..4
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;; O 1..4
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;; P -4..-1
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;; P -4..-1
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;; Q post-inc mem (push)
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;; Q post-inc mem (push)
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;; R pre-dec mem (pop)
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;; R pre-dec mem (pop)
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;; S immediate mem
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;; S immediate mem
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;; T Rx
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;; T Rx
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;; U -inf..1 or 16..inf
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;; U -inf..1 or 16..inf
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;; Z 0
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;; Z 0
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;; ::::::::::::::::::::
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;; ::::::::::::::::::::
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;; ::
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;; ::
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;; :: Attributes
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;; :: Attributes
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;; ::
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;; ::
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;; ::::::::::::::::::::
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;; ::::::::::::::::::::
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; Categorize branches for the conditional in the length attribute.
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; Categorize branches for the conditional in the length attribute.
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(define_attr "branch_class" "notdirectbranch,br12,bcc12,bcc8p2,bcc8p4"
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(define_attr "branch_class" "notdirectbranch,br12,bcc12,bcc8p2,bcc8p4"
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(const_string "notdirectbranch"))
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(const_string "notdirectbranch"))
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; The length of an instruction, used for branch shortening.
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; The length of an instruction, used for branch shortening.
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(define_attr "length" ""
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(define_attr "length" ""
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(cond
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(cond
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[(eq_attr "branch_class" "br12")
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[(eq_attr "branch_class" "br12")
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(if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -2046))
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(if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -2046))
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(lt (minus (match_dup 0) (pc)) (const_int 2048)))
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(lt (minus (match_dup 0) (pc)) (const_int 2048)))
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(const_int 2)
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(const_int 2)
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(const_int 4))
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(const_int 4))
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(eq_attr "branch_class" "bcc12")
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(eq_attr "branch_class" "bcc12")
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(if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -2044))
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(if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -2044))
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(lt (minus (match_dup 0) (pc)) (const_int 2048)))
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(lt (minus (match_dup 0) (pc)) (const_int 2048)))
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(const_int 4)
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(const_int 4)
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(const_int 8))
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(const_int 8))
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(eq_attr "branch_class" "bcc8p2")
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(eq_attr "branch_class" "bcc8p2")
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(if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -124))
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(if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -124))
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(lt (minus (match_dup 0) (pc)) (const_int 128)))
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(lt (minus (match_dup 0) (pc)) (const_int 128)))
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(const_int 4)
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(const_int 4)
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(const_int 8))
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(const_int 8))
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(eq_attr "branch_class" "bcc8p4")
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(eq_attr "branch_class" "bcc8p4")
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(if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -122))
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(if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -122))
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(lt (minus (match_dup 0) (pc)) (const_int 128)))
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(lt (minus (match_dup 0) (pc)) (const_int 128)))
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(const_int 6)
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(const_int 6)
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(const_int 10))]
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(const_int 10))]
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(const_int 2)))
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(const_int 2)))
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; The operand which determines the setting of Rpsw.
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; The operand which determines the setting of Rpsw.
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; The numbers indicate the operand number,
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; The numbers indicate the operand number,
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; 'clobber' indicates it is changed in some unspecified way
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; 'clobber' indicates it is changed in some unspecified way
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; 'nop' means it is not changed.
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; 'nop' means it is not changed.
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(define_attr "psw_operand" "clobber,nop,0,1,2,3,4" (const_string "0"))
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(define_attr "psw_operand" "clobber,nop,0,1,2,3,4" (const_string "0"))
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(define_asm_attributes [(set_attr "length" "4")
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(define_asm_attributes [(set_attr "length" "4")
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(set_attr "psw_operand" "clobber")])
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(set_attr "psw_operand" "clobber")])
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(include "predicates.md")
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(include "predicates.md")
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;; ::::::::::::::::::::
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;; ::::::::::::::::::::
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;; ::
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;; ::
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;; :: Moves
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;; :: Moves
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;; ::
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;; ::
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;; ::::::::::::::::::::
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;; ::::::::::::::::::::
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;; push/pop qi and hi are here as separate insns rather than part of
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;; push/pop qi and hi are here as separate insns rather than part of
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;; the movqi/hi patterns because we need to ensure that reload isn't
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;; the movqi/hi patterns because we need to ensure that reload isn't
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;; passed anything it can't cope with. Without these patterns, we
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;; passed anything it can't cope with. Without these patterns, we
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;; might end up with
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;; might end up with
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;; (set (mem (post_inc (sp))) mem (post_inc (reg)))
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;; (set (mem (post_inc (sp))) mem (post_inc (reg)))
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;; If, in this example, reg needs reloading, reload will read reg from
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;; If, in this example, reg needs reloading, reload will read reg from
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;; the stack , adjust sp, and store reg back at what is now the wrong
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;; the stack , adjust sp, and store reg back at what is now the wrong
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;; offset. By using separate patterns for push and pop we ensure that
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;; offset. By using separate patterns for push and pop we ensure that
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;; insns like this one are never generated.
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;; insns like this one are never generated.
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(define_insn "pushqi1"
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(define_insn "pushqi1"
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[(set (mem:QI (post_inc (reg:HI 15)))
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[(set (mem:QI (post_inc (reg:HI 15)))
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(match_operand:QI 0 "register_operand" "r"))]
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(match_operand:QI 0 "register_operand" "r"))]
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""
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""
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"push %0"
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"push %0"
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[(set_attr "psw_operand" "nop")
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[(set_attr "psw_operand" "nop")
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(set_attr "length" "2")])
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(set_attr "length" "2")])
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(define_insn "popqi1"
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(define_insn "popqi1"
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[(set (match_operand:QI 0 "register_operand" "=r")
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[(set (match_operand:QI 0 "register_operand" "=r")
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(mem:QI (pre_dec (reg:HI 15))))]
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(mem:QI (pre_dec (reg:HI 15))))]
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""
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""
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"pop %0"
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"pop %0"
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[(set_attr "psw_operand" "nop")
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[(set_attr "psw_operand" "nop")
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(set_attr "length" "2")])
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(set_attr "length" "2")])
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(define_expand "movqi"
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(define_expand "movqi"
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[(set (match_operand:QI 0 "nonimmediate_nonstack_operand" "")
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[(set (match_operand:QI 0 "nonimmediate_nonstack_operand" "")
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(match_operand:QI 1 "general_operand" ""))]
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(match_operand:QI 1 "general_operand" ""))]
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""
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""
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"{ xstormy16_expand_move (QImode, operands[0], operands[1]); DONE; }")
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"{ xstormy16_expand_move (QImode, operands[0], operands[1]); DONE; }")
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(define_insn "movqi_internal"
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(define_insn "movqi_internal"
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[(set (match_operand:QI 0 "nonimmediate_nonstack_operand" "=r,m,e,e,T,r,S,W,r")
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[(set (match_operand:QI 0 "nonimmediate_nonstack_operand" "=r,m,e,e,T,r,S,W,r")
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(match_operand:QI 1 "general_operand" "r,e,m,i,i,i,i,ir,W"))]
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(match_operand:QI 1 "general_operand" "r,e,m,i,i,i,i,ir,W"))]
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""
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""
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"@
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"@
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mov %0,%1
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mov %0,%1
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mov.b %0,%1
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mov.b %0,%1
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mov.b %0,%1
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mov.b %0,%1
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mov %0,%1
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mov %0,%1
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mov Rx,%1
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mov Rx,%1
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mov %0,%1
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mov %0,%1
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mov.b %0,%1
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mov.b %0,%1
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mov.b %0,%1
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mov.b %0,%1
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mov.b %0,%1"
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mov.b %0,%1"
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[(set_attr_alternative "length"
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[(set_attr_alternative "length"
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[(const_int 2)
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[(const_int 2)
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(if_then_else (match_operand:QI 0 "short_memory_operand" "")
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(if_then_else (match_operand:QI 0 "short_memory_operand" "")
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(const_int 2)
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(const_int 2)
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(const_int 4))
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(const_int 4))
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(if_then_else (match_operand:QI 1 "short_memory_operand" "")
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(if_then_else (match_operand:QI 1 "short_memory_operand" "")
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(const_int 2)
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(const_int 2)
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(const_int 4))
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(const_int 4))
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(const_int 2)
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(const_int 2)
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(const_int 2)
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(const_int 2)
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(const_int 4)
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(const_int 4)
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(const_int 4)
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(const_int 4)
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(const_int 2)
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(const_int 2)
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(const_int 2)])
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(const_int 2)])
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(set_attr "psw_operand" "0,0,0,0,nop,0,nop,0,0")])
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(set_attr "psw_operand" "0,0,0,0,nop,0,nop,0,0")])
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(define_insn "pushhi1"
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(define_insn "pushhi1"
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[(set (mem:HI (post_inc (reg:HI 15)))
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[(set (mem:HI (post_inc (reg:HI 15)))
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(match_operand:HI 0 "register_operand" "r"))]
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(match_operand:HI 0 "register_operand" "r"))]
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""
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""
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"push %0"
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"push %0"
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[(set_attr "psw_operand" "nop")
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[(set_attr "psw_operand" "nop")
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(set_attr "length" "2")])
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(set_attr "length" "2")])
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(define_insn "pophi1"
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(define_insn "pophi1"
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[(set (match_operand:HI 0 "register_operand" "=r")
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[(set (match_operand:HI 0 "register_operand" "=r")
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(mem:HI (pre_dec (reg:HI 15))))]
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(mem:HI (pre_dec (reg:HI 15))))]
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""
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""
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"pop %0"
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"pop %0"
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[(set_attr "psw_operand" "nop")
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[(set_attr "psw_operand" "nop")
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(set_attr "length" "2")])
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(set_attr "length" "2")])
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(define_expand "movhi"
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(define_expand "movhi"
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[(set (match_operand:HI 0 "nonimmediate_nonstack_operand" "")
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[(set (match_operand:HI 0 "nonimmediate_nonstack_operand" "")
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(match_operand:HI 1 "xs_hi_general_operand" ""))]
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(match_operand:HI 1 "xs_hi_general_operand" ""))]
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""
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""
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"{ xstormy16_expand_move (HImode, operands[0], operands[1]); DONE; }")
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"{ xstormy16_expand_move (HImode, operands[0], operands[1]); DONE; }")
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(define_insn "movhi_internal"
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(define_insn "movhi_internal"
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[(set (match_operand:HI 0 "nonimmediate_nonstack_operand" "=r,m,e,e,T,r,S,W,r")
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[(set (match_operand:HI 0 "nonimmediate_nonstack_operand" "=r,m,e,e,T,r,S,W,r")
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(match_operand:HI 1 "xs_hi_general_operand" "r,e,m,L,L,i,i,ir,W"))]
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(match_operand:HI 1 "xs_hi_general_operand" "r,e,m,L,L,i,i,ir,W"))]
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""
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""
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"@
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"@
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mov %0,%1
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mov %0,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w Rx,%1
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mov.w Rx,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w %0,%1
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mov.w %0,%1"
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mov.w %0,%1"
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[(set_attr_alternative "length"
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[(set_attr_alternative "length"
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[(const_int 2)
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[(const_int 2)
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(if_then_else (match_operand:QI 0 "short_memory_operand" "")
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(if_then_else (match_operand:QI 0 "short_memory_operand" "")
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(const_int 2)
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(const_int 2)
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(const_int 4))
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(const_int 4))
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(if_then_else (match_operand:QI 1 "short_memory_operand" "")
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(if_then_else (match_operand:QI 1 "short_memory_operand" "")
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(const_int 2)
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(const_int 2)
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(const_int 4))
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(const_int 4))
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(const_int 2)
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(const_int 2)
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(const_int 2)
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(const_int 2)
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(const_int 4)
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(const_int 4)
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(const_int 4)
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(const_int 4)
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(const_int 4)
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(const_int 4)
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(const_int 4)])
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(const_int 4)])
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(set_attr "psw_operand" "0,0,0,0,nop,0,nop,0,0")])
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(set_attr "psw_operand" "0,0,0,0,nop,0,nop,0,0")])
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(define_expand "movsi"
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(define_expand "movsi"
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(match_operand:SI 1 "general_operand" ""))]
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(match_operand:SI 1 "general_operand" ""))]
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""
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""
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"{ xstormy16_expand_move (SImode, operands[0], operands[1]); DONE; }")
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"{ xstormy16_expand_move (SImode, operands[0], operands[1]); DONE; }")
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(define_insn_and_split "*movsi_internal"
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(define_insn_and_split "*movsi_internal"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,Q,r,m,e,&e,e,r,S")
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,Q,r,m,e,&e,e,r,S")
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(match_operand:SI 1 "general_operand" "r,r,R,e,o, V,L,i,i"))]
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(match_operand:SI 1 "general_operand" "r,r,R,e,o, V,L,i,i"))]
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""
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""
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(pc)]
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[(pc)]
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"{ xstormy16_split_move (SImode, operands[0], operands[1]); DONE; }"
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"{ xstormy16_split_move (SImode, operands[0], operands[1]); DONE; }"
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[(set_attr_alternative "length"
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[(set_attr_alternative "length"
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[(const_int 4)
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[(const_int 4)
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(const_int 4)
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(const_int 4)
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(const_int 4)
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(const_int 4)
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(if_then_else (match_operand:QI 0 "short_memory_operand" "")
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(if_then_else (match_operand:QI 0 "short_memory_operand" "")
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(const_int 6)
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(const_int 6)
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(const_int 8))
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(const_int 8))
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(if_then_else (match_operand:QI 1 "short_memory_operand" "")
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(if_then_else (match_operand:QI 1 "short_memory_operand" "")
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(const_int 6)
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(const_int 6)
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(const_int 8))
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(const_int 8))
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(if_then_else (match_operand:QI 1 "short_memory_operand" "")
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(if_then_else (match_operand:QI 1 "short_memory_operand" "")
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(const_int 6)
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(const_int 6)
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(const_int 8))
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(const_int 8))
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(const_int 4)
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(const_int 4)
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(const_int 8)
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(const_int 8)
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(const_int 8)])])
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(const_int 8)])])
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;; ::::::::::::::::::::
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;; ::::::::::::::::::::
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;; ::
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;; ::
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;; :: Conversions
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;; :: Conversions
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;; ::
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;; ::
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;; ::::::::::::::::::::
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;; ::::::::::::::::::::
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(define_insn "extendqihi2"
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(define_insn "extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=r")
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[(set (match_operand:HI 0 "register_operand" "=r")
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(sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
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(sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
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""
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""
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"cbw %0")
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"cbw %0")
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(define_insn "zero_extendqihi2"
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(define_insn "zero_extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=e,r")
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[(set (match_operand:HI 0 "register_operand" "=e,r")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,0")))]
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,0")))]
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""
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""
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"@
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"@
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mov.b %0, %1
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mov.b %0, %1
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shl %0,#8\n\tshr %0,#8"
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shl %0,#8\n\tshr %0,#8"
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[(set_attr "psw_operand" "nop,0")
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[(set_attr "psw_operand" "nop,0")
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(set_attr_alternative "length"
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(set_attr_alternative "length"
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[(const_int 2)
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[(const_int 2)
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(const_int 4)])])
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(const_int 4)])])
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;; ::::::::::::::::::::
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;; ::::::::::::::::::::
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;; ::
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;; ::
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;; :: Bit field extraction
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;; :: Bit field extraction
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;; ::
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;; ::
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;; ::::::::::::::::::::
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;; ::::::::::::::::::::
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;; Extract an unsigned bit field
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;; Extract an unsigned bit field
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;(define_insn "extzv"
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;(define_insn "extzv"
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; [(set (match_operand:SI 0 "register_operand" "=r")
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; [(set (match_operand:SI 0 "register_operand" "=r")
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; (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
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; (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
|
; (match_operand:SI 2 "const_int_operand" "n")
|
; (match_operand:SI 2 "const_int_operand" "n")
|
; (match_operand:SI 3 "const_int_operand" "n")))]
|
; (match_operand:SI 3 "const_int_operand" "n")))]
|
; ""
|
; ""
|
; "extzv %0,%1,%2,%3"
|
; "extzv %0,%1,%2,%3"
|
; [(set_attr "length" "4")])
|
; [(set_attr "length" "4")])
|
|
|
;; Insert a bit field
|
;; Insert a bit field
|
;(define_insn "insv"
|
;(define_insn "insv"
|
; [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
|
; [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
|
; (match_operand:SI 1 "const_int_operand" "n")
|
; (match_operand:SI 1 "const_int_operand" "n")
|
; (match_operand:SI 2 "const_int_operand" "n"))
|
; (match_operand:SI 2 "const_int_operand" "n"))
|
; (match_operand:SI 3 "nonmemory_operand" "ri"))]
|
; (match_operand:SI 3 "nonmemory_operand" "ri"))]
|
; ""
|
; ""
|
; "insv %0,%1,%2,%3"
|
; "insv %0,%1,%2,%3"
|
; [(set_attr "length" "4")])
|
; [(set_attr "length" "4")])
|
|
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: 16 bit Integer arithmetic
|
;; :: 16 bit Integer arithmetic
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
;; Addition
|
;; Addition
|
; Operand 3 is marked earlyclobber because that helps reload
|
; Operand 3 is marked earlyclobber because that helps reload
|
; to generate better code---this pattern will never need the
|
; to generate better code---this pattern will never need the
|
; carry register as an input, and some output reloads or input
|
; carry register as an input, and some output reloads or input
|
; reloads might need to use it. In fact, without the '&' reload
|
; reloads might need to use it. In fact, without the '&' reload
|
; will fail in some cases.
|
; will fail in some cases.
|
; Note that the 'Z' constraint matches "add $reg,0", which reload
|
; Note that the 'Z' constraint matches "add $reg,0", which reload
|
; will occasionally emit. We avoid the "add $reg,imm" match because
|
; will occasionally emit. We avoid the "add $reg,imm" match because
|
; it clobbers the carry.
|
; it clobbers the carry.
|
(define_insn "addhi3"
|
(define_insn "addhi3"
|
[(set (match_operand:HI 0 "register_operand" "=r,r,r,T,T,r,r,r")
|
[(set (match_operand:HI 0 "register_operand" "=r,r,r,T,T,r,r,r")
|
(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,0,0")
|
(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,0,0")
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "O,P,Z,L,M,Ir,N,i")))
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "O,P,Z,L,M,Ir,N,i")))
|
(clobber (match_scratch:BI 3 "=X,X,X,&y,&y,&y,&y,&y"))]
|
(clobber (match_scratch:BI 3 "=X,X,X,&y,&y,&y,&y,&y"))]
|
""
|
""
|
"@
|
"@
|
inc %0,%o2
|
inc %0,%o2
|
dec %0,%O2
|
dec %0,%O2
|
;
|
;
|
add Rx,%2
|
add Rx,%2
|
sub Rx,#%n2
|
sub Rx,#%n2
|
add %0,%2
|
add %0,%2
|
sub %0,#%n2
|
sub %0,#%n2
|
add %0,%2"
|
add %0,%2"
|
[(set_attr "length" "2,2,0,2,2,2,2,4")])
|
[(set_attr "length" "2,2,0,2,2,2,2,4")])
|
|
|
; Reload can generate addition operations. The SECONDARY_RELOAD_CLASS
|
; Reload can generate addition operations. The SECONDARY_RELOAD_CLASS
|
; macro causes it to allocate the carry register; this pattern
|
; macro causes it to allocate the carry register; this pattern
|
; shows it how to place the register in RTL to make the addition work.
|
; shows it how to place the register in RTL to make the addition work.
|
(define_expand "reload_inhi"
|
(define_expand "reload_inhi"
|
[(parallel [(set (match_operand:HI 0 "register_operand" "=r")
|
[(parallel [(set (match_operand:HI 0 "register_operand" "=r")
|
(match_operand:HI 1 "xstormy16_carry_plus_operand" ""))
|
(match_operand:HI 1 "xstormy16_carry_plus_operand" ""))
|
(clobber (match_operand:BI 2 "" "=&y"))])]
|
(clobber (match_operand:BI 2 "" "=&y"))])]
|
""
|
""
|
"if (! rtx_equal_p (operands[0], XEXP (operands[1], 0)))
|
"if (! rtx_equal_p (operands[0], XEXP (operands[1], 0)))
|
{
|
{
|
emit_insn (gen_rtx_SET (VOIDmode, operands[0], XEXP (operands[1], 0)));
|
emit_insn (gen_rtx_SET (VOIDmode, operands[0], XEXP (operands[1], 0)));
|
operands[1] = gen_rtx_PLUS (GET_MODE (operands[1]), operands[0],
|
operands[1] = gen_rtx_PLUS (GET_MODE (operands[1]), operands[0],
|
XEXP (operands[1], 1));
|
XEXP (operands[1], 1));
|
}
|
}
|
")
|
")
|
|
|
(define_insn "addchi4"
|
(define_insn "addchi4"
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
|
(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
|
(set (match_operand:BI 3 "register_operand" "=y,y,y")
|
(set (match_operand:BI 3 "register_operand" "=y,y,y")
|
(truncate:BI (lshiftrt:SI (plus:SI (zero_extend:SI (match_dup 1))
|
(truncate:BI (lshiftrt:SI (plus:SI (zero_extend:SI (match_dup 1))
|
(zero_extend:SI (match_dup 2)))
|
(zero_extend:SI (match_dup 2)))
|
(const_int 16))))]
|
(const_int 16))))]
|
""
|
""
|
"@
|
"@
|
add Rx,%2
|
add Rx,%2
|
add %0,%2
|
add %0,%2
|
add %0,%2"
|
add %0,%2"
|
[(set_attr "length" "2,2,4")])
|
[(set_attr "length" "2,2,4")])
|
|
|
(define_insn "addchi5"
|
(define_insn "addchi5"
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
(plus:HI (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
|
(plus:HI (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
|
(zero_extend:HI (match_operand:BI 3
|
(zero_extend:HI (match_operand:BI 3
|
"register_operand"
|
"register_operand"
|
"y,y,y")))
|
"y,y,y")))
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
|
(set (match_operand:BI 4 "register_operand" "=y,y,y")
|
(set (match_operand:BI 4 "register_operand" "=y,y,y")
|
(truncate:BI (lshiftrt:SI (plus:SI (plus:SI
|
(truncate:BI (lshiftrt:SI (plus:SI (plus:SI
|
(zero_extend:SI (match_dup 1))
|
(zero_extend:SI (match_dup 1))
|
(zero_extend:SI (match_dup 3)))
|
(zero_extend:SI (match_dup 3)))
|
(zero_extend:SI (match_dup 2)))
|
(zero_extend:SI (match_dup 2)))
|
(const_int 16))))]
|
(const_int 16))))]
|
""
|
""
|
"@
|
"@
|
adc Rx,%2
|
adc Rx,%2
|
adc %0,%2
|
adc %0,%2
|
adc %0,%2"
|
adc %0,%2"
|
[(set_attr "length" "2,2,4")])
|
[(set_attr "length" "2,2,4")])
|
|
|
;; Subtraction
|
;; Subtraction
|
; Operand 3 is marked earlyclobber because that helps reload
|
; Operand 3 is marked earlyclobber because that helps reload
|
; to generate better code---this pattern will never need the
|
; to generate better code---this pattern will never need the
|
; carry register as an input, and some output reloads or input
|
; carry register as an input, and some output reloads or input
|
; reloads might need to use it. In fact, without the '&' reload
|
; reloads might need to use it. In fact, without the '&' reload
|
; will fail in some cases.
|
; will fail in some cases.
|
(define_insn "subhi3"
|
(define_insn "subhi3"
|
[(set (match_operand:HI 0 "register_operand" "=r,r,T,T,r,r,r")
|
[(set (match_operand:HI 0 "register_operand" "=r,r,T,T,r,r,r")
|
(minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,0,0")
|
(minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,0,0")
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "O,P,L,M,rI,M,i")))
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "O,P,L,M,rI,M,i")))
|
(clobber (match_scratch:BI 3 "=X,X,&y,&y,&y,&y,&y"))]
|
(clobber (match_scratch:BI 3 "=X,X,&y,&y,&y,&y,&y"))]
|
""
|
""
|
"@
|
"@
|
dec %0,%o2
|
dec %0,%o2
|
inc %0,%O2
|
inc %0,%O2
|
sub Rx,%2
|
sub Rx,%2
|
add Rx,#%n2
|
add Rx,#%n2
|
sub %0,%2
|
sub %0,%2
|
add %0,#%n2
|
add %0,#%n2
|
sub %0,%2"
|
sub %0,%2"
|
[(set_attr "length" "2,2,2,2,2,2,4")])
|
[(set_attr "length" "2,2,2,2,2,2,4")])
|
|
|
(define_insn "subchi4"
|
(define_insn "subchi4"
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
(minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
|
(minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
|
(set (match_operand:BI 3 "register_operand" "=y,y,y")
|
(set (match_operand:BI 3 "register_operand" "=y,y,y")
|
(truncate:BI (lshiftrt:SI (minus:SI (zero_extend:SI (match_dup 1))
|
(truncate:BI (lshiftrt:SI (minus:SI (zero_extend:SI (match_dup 1))
|
(zero_extend:SI (match_dup 2)))
|
(zero_extend:SI (match_dup 2)))
|
(const_int 16))))]
|
(const_int 16))))]
|
""
|
""
|
"@
|
"@
|
sub Rx,%2
|
sub Rx,%2
|
sub %0,%2
|
sub %0,%2
|
sub %0,%2"
|
sub %0,%2"
|
[(set_attr "length" "2,2,4")])
|
[(set_attr "length" "2,2,4")])
|
|
|
(define_insn "subchi5"
|
(define_insn "subchi5"
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
(minus:HI (minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
|
(minus:HI (minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
|
(zero_extend:HI (match_operand:BI 3
|
(zero_extend:HI (match_operand:BI 3
|
"register_operand"
|
"register_operand"
|
"y,y,y")))
|
"y,y,y")))
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
|
(match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i")))
|
(set (match_operand:BI 4 "register_operand" "=y,y,y")
|
(set (match_operand:BI 4 "register_operand" "=y,y,y")
|
(truncate:BI (lshiftrt:SI (minus:SI (minus:SI
|
(truncate:BI (lshiftrt:SI (minus:SI (minus:SI
|
(zero_extend:SI (match_dup 1))
|
(zero_extend:SI (match_dup 1))
|
(zero_extend:SI (match_dup 3)))
|
(zero_extend:SI (match_dup 3)))
|
(zero_extend:SI (match_dup 2)))
|
(zero_extend:SI (match_dup 2)))
|
(const_int 16))))]
|
(const_int 16))))]
|
""
|
""
|
"@
|
"@
|
sbc Rx,%2
|
sbc Rx,%2
|
sbc %0,%2
|
sbc %0,%2
|
sbc %0,%2"
|
sbc %0,%2"
|
[(set_attr "length" "2,2,4")])
|
[(set_attr "length" "2,2,4")])
|
|
|
; Basic multiplication
|
; Basic multiplication
|
(define_insn "mulhi3"
|
(define_insn "mulhi3"
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
(mult:HI (match_operand:HI 1 "register_operand" "%a")
|
(mult:HI (match_operand:HI 1 "register_operand" "%a")
|
(match_operand:HI 2 "register_operand" "c")))
|
(match_operand:HI 2 "register_operand" "c")))
|
(clobber (match_scratch:HI 3 "=b"))
|
(clobber (match_scratch:HI 3 "=b"))
|
]
|
]
|
""
|
""
|
"mul"
|
"mul"
|
[(set_attr "psw_operand" "nop")])
|
[(set_attr "psw_operand" "nop")])
|
|
|
;; Unsigned multiplication producing 64 bit results from 32 bit inputs
|
;; Unsigned multiplication producing 64 bit results from 32 bit inputs
|
; The constraint on operand 0 is 't' because it is actually two regs
|
; The constraint on operand 0 is 't' because it is actually two regs
|
; long, and both regs must match the constraint.
|
; long, and both regs must match the constraint.
|
(define_insn "umulhisi3"
|
(define_insn "umulhisi3"
|
[(set (match_operand:SI 0 "register_operand" "=t")
|
[(set (match_operand:SI 0 "register_operand" "=t")
|
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%a"))
|
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%a"))
|
(zero_extend:SI (match_operand:HI 2 "register_operand" "c"))))
|
(zero_extend:SI (match_operand:HI 2 "register_operand" "c"))))
|
]
|
]
|
""
|
""
|
"mul"
|
"mul"
|
[(set_attr "psw_operand" "nop")])
|
[(set_attr "psw_operand" "nop")])
|
|
|
;; Unsigned division giving both quotient and remainder
|
;; Unsigned division giving both quotient and remainder
|
(define_insn "udivmodhi4"
|
(define_insn "udivmodhi4"
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
(udiv:HI (match_operand:HI 1 "register_operand" "a")
|
(udiv:HI (match_operand:HI 1 "register_operand" "a")
|
(match_operand:HI 2 "register_operand" "c")))
|
(match_operand:HI 2 "register_operand" "c")))
|
(set (match_operand:HI 3 "register_operand" "=b")
|
(set (match_operand:HI 3 "register_operand" "=b")
|
(umod:HI (match_dup 1)
|
(umod:HI (match_dup 1)
|
(match_dup 2)))]
|
(match_dup 2)))]
|
""
|
""
|
"div"
|
"div"
|
[(set_attr "psw_operand" "nop")])
|
[(set_attr "psw_operand" "nop")])
|
|
|
;; Signed division giving both quotient and remainder
|
;; Signed division giving both quotient and remainder
|
(define_insn "divmodhi4"
|
(define_insn "divmodhi4"
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
(div:HI (match_operand:HI 1 "register_operand" "a")
|
(div:HI (match_operand:HI 1 "register_operand" "a")
|
(match_operand:HI 2 "register_operand" "c")))
|
(match_operand:HI 2 "register_operand" "c")))
|
(set (match_operand:HI 3 "register_operand" "=b")
|
(set (match_operand:HI 3 "register_operand" "=b")
|
(mod:HI (match_dup 1)
|
(mod:HI (match_dup 1)
|
(match_dup 2)))]
|
(match_dup 2)))]
|
""
|
""
|
"sdiv"
|
"sdiv"
|
[(set_attr "psw_operand" "nop")])
|
[(set_attr "psw_operand" "nop")])
|
|
|
;; Signed 32/16 division
|
;; Signed 32/16 division
|
(define_insn "sdivlh"
|
(define_insn "sdivlh"
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
(div:HI (match_operand:SI 2 "register_operand" "t")
|
(div:HI (match_operand:SI 2 "register_operand" "t")
|
(match_operand:HI 3 "register_operand" "c")))
|
(match_operand:HI 3 "register_operand" "c")))
|
(set (match_operand:HI 1 "register_operand" "=b")
|
(set (match_operand:HI 1 "register_operand" "=b")
|
(mod:HI (match_dup 2)
|
(mod:HI (match_dup 2)
|
(match_dup 3)))]
|
(match_dup 3)))]
|
""
|
""
|
"sdivlh"
|
"sdivlh"
|
[(set_attr "psw_operand" "nop")])
|
[(set_attr "psw_operand" "nop")])
|
|
|
;; Unsigned 32/16 division
|
;; Unsigned 32/16 division
|
(define_insn "udivlh"
|
(define_insn "udivlh"
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
[(set (match_operand:HI 0 "register_operand" "=a")
|
(udiv:HI (match_operand:SI 2 "register_operand" "t")
|
(udiv:HI (match_operand:SI 2 "register_operand" "t")
|
(match_operand:HI 3 "register_operand" "c")))
|
(match_operand:HI 3 "register_operand" "c")))
|
(set (match_operand:HI 1 "register_operand" "=b")
|
(set (match_operand:HI 1 "register_operand" "=b")
|
(umod:HI (match_dup 2)
|
(umod:HI (match_dup 2)
|
(match_dup 3)))]
|
(match_dup 3)))]
|
""
|
""
|
"divlh"
|
"divlh"
|
[(set_attr "psw_operand" "nop")])
|
[(set_attr "psw_operand" "nop")])
|
|
|
;; Negation
|
;; Negation
|
|
|
(define_expand "neghi2"
|
(define_expand "neghi2"
|
[(set (match_operand:HI 0 "register_operand" "")
|
[(set (match_operand:HI 0 "register_operand" "")
|
(not:HI (match_operand:HI 1 "register_operand" "")))
|
(not:HI (match_operand:HI 1 "register_operand" "")))
|
(parallel [(set (match_dup 0) (plus:HI (match_dup 0) (const_int 1)))
|
(parallel [(set (match_dup 0) (plus:HI (match_dup 0) (const_int 1)))
|
(clobber (match_scratch:BI 3 ""))])]
|
(clobber (match_scratch:BI 3 ""))])]
|
""
|
""
|
"")
|
"")
|
|
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: 16 bit Integer Shifts and Rotates
|
;; :: 16 bit Integer Shifts and Rotates
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
;; Arithmetic Shift Left
|
;; Arithmetic Shift Left
|
(define_insn "ashlhi3"
|
(define_insn "ashlhi3"
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
(ashift:HI (match_operand:HI 1 "register_operand" "0")
|
(ashift:HI (match_operand:HI 1 "register_operand" "0")
|
(match_operand:HI 2 "nonmemory_operand" "ri")))
|
(match_operand:HI 2 "nonmemory_operand" "ri")))
|
(clobber (match_scratch:BI 3 "=y"))]
|
(clobber (match_scratch:BI 3 "=y"))]
|
""
|
""
|
"shl %0,%2")
|
"shl %0,%2")
|
|
|
;; Arithmetic Shift Right
|
;; Arithmetic Shift Right
|
(define_insn "ashrhi3"
|
(define_insn "ashrhi3"
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
|
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
|
(match_operand:HI 2 "nonmemory_operand" "ri")))
|
(match_operand:HI 2 "nonmemory_operand" "ri")))
|
(clobber (match_scratch:BI 3 "=y"))]
|
(clobber (match_scratch:BI 3 "=y"))]
|
""
|
""
|
"asr %0,%2")
|
"asr %0,%2")
|
|
|
;; Logical Shift Right
|
;; Logical Shift Right
|
(define_insn "lshrhi3"
|
(define_insn "lshrhi3"
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
|
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
|
(match_operand:HI 2 "nonmemory_operand" "ri")))
|
(match_operand:HI 2 "nonmemory_operand" "ri")))
|
(clobber (match_scratch:BI 3 "=y"))]
|
(clobber (match_scratch:BI 3 "=y"))]
|
""
|
""
|
"shr %0,%2")
|
"shr %0,%2")
|
|
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: 16 Bit Integer Logical operations
|
;; :: 16 Bit Integer Logical operations
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
;; Logical AND, 16 bit integers
|
;; Logical AND, 16 bit integers
|
(define_insn "andhi3"
|
(define_insn "andhi3"
|
[(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W")
|
[(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W")
|
(and:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0")
|
(and:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0")
|
(match_operand:HI 2 "nonmemory_operand" "L,r,K,i,K")))]
|
(match_operand:HI 2 "nonmemory_operand" "L,r,K,i,K")))]
|
""
|
""
|
"@
|
"@
|
and Rx,%2
|
and Rx,%2
|
and %0,%2
|
and %0,%2
|
clr1 %0,%B2
|
clr1 %0,%B2
|
and %0,%2
|
and %0,%2
|
#"
|
#"
|
[(set_attr "length" "2,2,2,4,2")])
|
[(set_attr "length" "2,2,2,4,2")])
|
|
|
(define_split
|
(define_split
|
[(set (match_operand:HI 0 "xstormy16_below100_operand" "")
|
[(set (match_operand:HI 0 "xstormy16_below100_operand" "")
|
(and:HI (match_operand:HI 1 "xstormy16_below100_operand" "")
|
(and:HI (match_operand:HI 1 "xstormy16_below100_operand" "")
|
(match_operand:HI 2 "xstormy16_onebit_clr_operand" "")))]
|
(match_operand:HI 2 "xstormy16_onebit_clr_operand" "")))]
|
""
|
""
|
[(set (match_dup 3)
|
[(set (match_dup 3)
|
(and:QI (match_dup 4)
|
(and:QI (match_dup 4)
|
(match_dup 5)))]
|
(match_dup 5)))]
|
"{ int s = ((INTVAL (operands[2]) & 0xff) == 0xff) ? 1 : 0;
|
"{ int s = ((INTVAL (operands[2]) & 0xff) == 0xff) ? 1 : 0;
|
operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, s);
|
operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, s);
|
operands[4] = simplify_gen_subreg (QImode, operands[1], HImode, s);
|
operands[4] = simplify_gen_subreg (QImode, operands[1], HImode, s);
|
operands[5] = simplify_gen_subreg (QImode, operands[2], HImode, s);
|
operands[5] = simplify_gen_subreg (QImode, operands[2], HImode, s);
|
operands[5] = GEN_INT (INTVAL (operands[5]) | ~(HOST_WIDE_INT)0xff);
|
operands[5] = GEN_INT (INTVAL (operands[5]) | ~(HOST_WIDE_INT)0xff);
|
}
|
}
|
")
|
")
|
|
|
;; Inclusive OR, 16 bit integers
|
;; Inclusive OR, 16 bit integers
|
(define_insn "iorhi3"
|
(define_insn "iorhi3"
|
[(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W")
|
[(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W")
|
(ior:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0")
|
(ior:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0")
|
(match_operand:HI 2 "nonmemory_operand" "L,r,J,i,J")))]
|
(match_operand:HI 2 "nonmemory_operand" "L,r,J,i,J")))]
|
""
|
""
|
"@
|
"@
|
or Rx,%2
|
or Rx,%2
|
or %0,%2
|
or %0,%2
|
set1 %0,%B2
|
set1 %0,%B2
|
or %0,%2
|
or %0,%2
|
#"
|
#"
|
[(set_attr "length" "2,2,2,4,2")])
|
[(set_attr "length" "2,2,2,4,2")])
|
|
|
(define_split
|
(define_split
|
[(set (match_operand:HI 0 "xstormy16_below100_operand" "")
|
[(set (match_operand:HI 0 "xstormy16_below100_operand" "")
|
(ior:HI (match_operand:HI 1 "xstormy16_below100_operand" "")
|
(ior:HI (match_operand:HI 1 "xstormy16_below100_operand" "")
|
(match_operand:HI 2 "xstormy16_onebit_set_operand" "")))]
|
(match_operand:HI 2 "xstormy16_onebit_set_operand" "")))]
|
""
|
""
|
[(set (match_dup 3)
|
[(set (match_dup 3)
|
(ior:QI (match_dup 4)
|
(ior:QI (match_dup 4)
|
(match_dup 5)))]
|
(match_dup 5)))]
|
"{ int s = ((INTVAL (operands[2]) & 0xff) == 0x00) ? 1 : 0;
|
"{ int s = ((INTVAL (operands[2]) & 0xff) == 0x00) ? 1 : 0;
|
operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, s);
|
operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, s);
|
operands[4] = simplify_gen_subreg (QImode, operands[1], HImode, s);
|
operands[4] = simplify_gen_subreg (QImode, operands[1], HImode, s);
|
operands[5] = simplify_gen_subreg (QImode, operands[2], HImode, s);
|
operands[5] = simplify_gen_subreg (QImode, operands[2], HImode, s);
|
operands[5] = GEN_INT (INTVAL (operands[5]) & 0xff);
|
operands[5] = GEN_INT (INTVAL (operands[5]) & 0xff);
|
}
|
}
|
")
|
")
|
|
|
;; Exclusive OR, 16 bit integers
|
;; Exclusive OR, 16 bit integers
|
(define_insn "xorhi3"
|
(define_insn "xorhi3"
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
(xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
|
(xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
|
(match_operand:HI 2 "nonmemory_operand" "L,r,i")))]
|
(match_operand:HI 2 "nonmemory_operand" "L,r,i")))]
|
""
|
""
|
"@
|
"@
|
xor Rx,%2
|
xor Rx,%2
|
xor %0,%2
|
xor %0,%2
|
xor %0,%2"
|
xor %0,%2"
|
[(set_attr "length" "2,2,4")])
|
[(set_attr "length" "2,2,4")])
|
|
|
;; One's complement, 16 bit integers
|
;; One's complement, 16 bit integers
|
(define_insn "one_cmplhi2"
|
(define_insn "one_cmplhi2"
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
(not:HI (match_operand:HI 1 "register_operand" "0")))]
|
(not:HI (match_operand:HI 1 "register_operand" "0")))]
|
""
|
""
|
"not %0")
|
"not %0")
|
|
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: 32 bit Integer arithmetic
|
;; :: 32 bit Integer arithmetic
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
;; Addition
|
;; Addition
|
(define_insn_and_split "addsi3"
|
(define_insn_and_split "addsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(plus:SI (match_operand:SI 1 "register_operand" "%0")
|
(plus:SI (match_operand:SI 1 "register_operand" "%0")
|
(match_operand:SI 2 "nonmemory_operand" "ri")))
|
(match_operand:SI 2 "nonmemory_operand" "ri")))
|
(clobber (match_scratch:BI 3 "=y"))]
|
(clobber (match_scratch:BI 3 "=y"))]
|
""
|
""
|
"#"
|
"#"
|
"reload_completed"
|
"reload_completed"
|
[(pc)]
|
[(pc)]
|
"{ xstormy16_expand_arith (SImode, PLUS, operands[0], operands[1],
|
"{ xstormy16_expand_arith (SImode, PLUS, operands[0], operands[1],
|
operands[2], operands[3]); DONE; } "
|
operands[2], operands[3]); DONE; } "
|
[(set_attr "length" "4")])
|
[(set_attr "length" "4")])
|
|
|
;; Subtraction
|
;; Subtraction
|
(define_insn_and_split "subsi3"
|
(define_insn_and_split "subsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(minus:SI (match_operand:SI 1 "register_operand" "0")
|
(minus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "nonmemory_operand" "ri")))
|
(match_operand:SI 2 "nonmemory_operand" "ri")))
|
(clobber (match_scratch:BI 3 "=y"))]
|
(clobber (match_scratch:BI 3 "=y"))]
|
""
|
""
|
"#"
|
"#"
|
"reload_completed"
|
"reload_completed"
|
[(pc)]
|
[(pc)]
|
"{ xstormy16_expand_arith (SImode, MINUS, operands[0], operands[1],
|
"{ xstormy16_expand_arith (SImode, MINUS, operands[0], operands[1],
|
operands[2], operands[3]); DONE; } "
|
operands[2], operands[3]); DONE; } "
|
[(set_attr "length" "4")])
|
[(set_attr "length" "4")])
|
|
|
(define_expand "negsi2"
|
(define_expand "negsi2"
|
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
(neg:SI (match_operand:SI 1 "register_operand" "")))
|
(neg:SI (match_operand:SI 1 "register_operand" "")))
|
(clobber (match_scratch:BI 2 ""))])]
|
(clobber (match_scratch:BI 2 ""))])]
|
""
|
""
|
"{ operands[2] = gen_reg_rtx (HImode);
|
"{ operands[2] = gen_reg_rtx (HImode);
|
operands[3] = gen_reg_rtx (BImode); }")
|
operands[3] = gen_reg_rtx (BImode); }")
|
|
|
(define_insn_and_split "*negsi2_internal"
|
(define_insn_and_split "*negsi2_internal"
|
[(set (match_operand:SI 0 "register_operand" "=&r")
|
[(set (match_operand:SI 0 "register_operand" "=&r")
|
(neg:SI (match_operand:SI 1 "register_operand" "r")))
|
(neg:SI (match_operand:SI 1 "register_operand" "r")))
|
(clobber (match_scratch:BI 2 "=y"))]
|
(clobber (match_scratch:BI 2 "=y"))]
|
""
|
""
|
"#"
|
"#"
|
"reload_completed"
|
"reload_completed"
|
[(pc)]
|
[(pc)]
|
"{ xstormy16_expand_arith (SImode, NEG, operands[0], operands[0],
|
"{ xstormy16_expand_arith (SImode, NEG, operands[0], operands[0],
|
operands[1], operands[2]); DONE; }")
|
operands[1], operands[2]); DONE; }")
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: 32 bit Integer Shifts and Rotates
|
;; :: 32 bit Integer Shifts and Rotates
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
;; Arithmetic Shift Left
|
;; Arithmetic Shift Left
|
(define_expand "ashlsi3"
|
(define_expand "ashlsi3"
|
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
(ashift:SI (match_operand:SI 1 "register_operand" "")
|
(ashift:SI (match_operand:SI 1 "register_operand" "")
|
(match_operand:SI 2 "const_int_operand" "")))
|
(match_operand:SI 2 "const_int_operand" "")))
|
(clobber (match_dup 3))
|
(clobber (match_dup 3))
|
(clobber (match_dup 4))])]
|
(clobber (match_dup 4))])]
|
""
|
""
|
" if (! const_int_operand (operands[2], SImode)) FAIL;
|
" if (! const_int_operand (operands[2], SImode)) FAIL;
|
operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
|
operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
|
|
|
;; Arithmetic Shift Right
|
;; Arithmetic Shift Right
|
(define_expand "ashrsi3"
|
(define_expand "ashrsi3"
|
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
|
(match_operand:SI 2 "const_int_operand" "")))
|
(match_operand:SI 2 "const_int_operand" "")))
|
(clobber (match_dup 3))
|
(clobber (match_dup 3))
|
(clobber (match_dup 4))])]
|
(clobber (match_dup 4))])]
|
""
|
""
|
" if (! const_int_operand (operands[2], SImode)) FAIL;
|
" if (! const_int_operand (operands[2], SImode)) FAIL;
|
operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
|
operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
|
|
|
;; Logical Shift Right
|
;; Logical Shift Right
|
(define_expand "lshrsi3"
|
(define_expand "lshrsi3"
|
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
|
(match_operand:SI 2 "const_int_operand" "")))
|
(match_operand:SI 2 "const_int_operand" "")))
|
(clobber (match_dup 3))
|
(clobber (match_dup 3))
|
(clobber (match_dup 4))])]
|
(clobber (match_dup 4))])]
|
""
|
""
|
" if (! const_int_operand (operands[2], SImode)) FAIL;
|
" if (! const_int_operand (operands[2], SImode)) FAIL;
|
operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
|
operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")
|
|
|
(define_insn "*shiftsi"
|
(define_insn "*shiftsi"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(match_operator:SI 5 "shift_operator"
|
(match_operator:SI 5 "shift_operator"
|
[(match_operand:SI 1 "register_operand" "0,0")
|
[(match_operand:SI 1 "register_operand" "0,0")
|
(match_operand:SI 2 "const_int_operand" "U,n")]))
|
(match_operand:SI 2 "const_int_operand" "U,n")]))
|
(clobber (match_operand:BI 3 "register_operand" "=y,y"))
|
(clobber (match_operand:BI 3 "register_operand" "=y,y"))
|
(clobber (match_operand:HI 4 "" "=X,r"))]
|
(clobber (match_operand:HI 4 "" "=X,r"))]
|
""
|
""
|
"* return xstormy16_output_shift (SImode, GET_CODE (operands[5]),
|
"* return xstormy16_output_shift (SImode, GET_CODE (operands[5]),
|
operands[0], operands[2], operands[4]);"
|
operands[0], operands[2], operands[4]);"
|
[(set_attr "length" "6,10")
|
[(set_attr "length" "6,10")
|
(set_attr "psw_operand" "clobber,clobber")])
|
(set_attr "psw_operand" "clobber,clobber")])
|
|
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: Comparisons
|
;; :: Comparisons
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
;; Note, we store the operands in the comparison insns, and use them later
|
;; Note, we store the operands in the comparison insns, and use them later
|
;; when generating the branch or scc operation.
|
;; when generating the branch or scc operation.
|
|
|
;; First the routines called by the machine independent part of the compiler
|
;; First the routines called by the machine independent part of the compiler
|
(define_expand "cmphi"
|
(define_expand "cmphi"
|
[(set (cc0)
|
[(set (cc0)
|
(compare (match_operand:HI 0 "register_operand" "")
|
(compare (match_operand:HI 0 "register_operand" "")
|
(match_operand:HI 1 "nonmemory_operand" "")))]
|
(match_operand:HI 1 "nonmemory_operand" "")))]
|
""
|
""
|
"
|
"
|
{
|
{
|
xstormy16_compare_op0 = operands[0];
|
xstormy16_compare_op0 = operands[0];
|
xstormy16_compare_op1 = operands[1];
|
xstormy16_compare_op1 = operands[1];
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
; There are no real SImode comparisons, but some can be emulated
|
; There are no real SImode comparisons, but some can be emulated
|
; by performing a SImode subtract and looking at the condition flags.
|
; by performing a SImode subtract and looking at the condition flags.
|
(define_expand "cmpsi"
|
(define_expand "cmpsi"
|
[(set (cc0)
|
[(set (cc0)
|
(compare (match_operand:SI 0 "register_operand" "")
|
(compare (match_operand:SI 0 "register_operand" "")
|
(match_operand:SI 1 "nonmemory_operand" "")))]
|
(match_operand:SI 1 "nonmemory_operand" "")))]
|
""
|
""
|
"
|
"
|
{
|
{
|
xstormy16_compare_op0 = operands[0];
|
xstormy16_compare_op0 = operands[0];
|
xstormy16_compare_op1 = operands[1];
|
xstormy16_compare_op1 = operands[1];
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: Branches
|
;; :: Branches
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
(define_expand "beq"
|
(define_expand "beq"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (EQ, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (EQ, operands[0]); DONE; }")
|
|
|
(define_expand "bne"
|
(define_expand "bne"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (NE, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (NE, operands[0]); DONE; }")
|
|
|
(define_expand "bge"
|
(define_expand "bge"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (GE, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (GE, operands[0]); DONE; }")
|
|
|
(define_expand "bgt"
|
(define_expand "bgt"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (GT, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (GT, operands[0]); DONE; }")
|
|
|
(define_expand "ble"
|
(define_expand "ble"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (LE, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (LE, operands[0]); DONE; }")
|
|
|
(define_expand "blt"
|
(define_expand "blt"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (LT, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (LT, operands[0]); DONE; }")
|
|
|
(define_expand "bgeu"
|
(define_expand "bgeu"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (GEU, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (GEU, operands[0]); DONE; }")
|
|
|
(define_expand "bgtu"
|
(define_expand "bgtu"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (GTU, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (GTU, operands[0]); DONE; }")
|
|
|
(define_expand "bleu"
|
(define_expand "bleu"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (LEU, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (LEU, operands[0]); DONE; }")
|
|
|
(define_expand "bltu"
|
(define_expand "bltu"
|
[(use (match_operand 0 "" ""))]
|
[(use (match_operand 0 "" ""))]
|
""
|
""
|
"{ xstormy16_emit_cbranch (LTU, operands[0]); DONE; }")
|
"{ xstormy16_emit_cbranch (LTU, operands[0]); DONE; }")
|
|
|
|
|
(define_insn "cbranchhi"
|
(define_insn "cbranchhi"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (match_operator:HI 1 "comparison_operator"
|
(if_then_else (match_operator:HI 1 "comparison_operator"
|
[(match_operand:HI 2 "nonmemory_operand"
|
[(match_operand:HI 2 "nonmemory_operand"
|
"r,e,L")
|
"r,e,L")
|
(match_operand:HI 3 "nonmemory_operand"
|
(match_operand:HI 3 "nonmemory_operand"
|
"r,L,e")])
|
"r,L,e")])
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
|
(clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
|
""
|
""
|
"*
|
"*
|
{
|
{
|
return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 0, insn);
|
return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 0, insn);
|
}"
|
}"
|
[(set_attr "branch_class" "bcc12")
|
[(set_attr "branch_class" "bcc12")
|
(set_attr "psw_operand" "0,0,1")])
|
(set_attr "psw_operand" "0,0,1")])
|
|
|
(define_insn "cbranchhi_neg"
|
(define_insn "cbranchhi_neg"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (match_operator:HI 1 "comparison_operator"
|
(if_then_else (match_operator:HI 1 "comparison_operator"
|
[(match_operand:HI 2 "nonmemory_operand"
|
[(match_operand:HI 2 "nonmemory_operand"
|
"r,e,L")
|
"r,e,L")
|
(match_operand:HI 3 "nonmemory_operand"
|
(match_operand:HI 3 "nonmemory_operand"
|
"r,L,e")])
|
"r,L,e")])
|
(pc)
|
(pc)
|
(label_ref (match_operand 0 "" ""))))
|
(label_ref (match_operand 0 "" ""))))
|
(clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
|
(clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
|
""
|
""
|
"*
|
"*
|
{
|
{
|
return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 1, insn);
|
return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 1, insn);
|
}"
|
}"
|
[(set_attr "branch_class" "bcc12")
|
[(set_attr "branch_class" "bcc12")
|
(set_attr "psw_operand" "0,0,1")])
|
(set_attr "psw_operand" "0,0,1")])
|
|
|
(define_insn "*eqbranchsi"
|
(define_insn "*eqbranchsi"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (match_operator:SI 1 "equality_operator"
|
(if_then_else (match_operator:SI 1 "equality_operator"
|
[(match_operand:SI 2 "register_operand"
|
[(match_operand:SI 2 "register_operand"
|
"r")
|
"r")
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
;; Although I would greatly like the 'match_dup' in the following line
|
;; Although I would greatly like the 'match_dup' in the following line
|
;; to actually be a register constraint, there is (at the time of writing) no
|
;; to actually be a register constraint, there is (at the time of writing) no
|
;; way for reload to insert an output reload on the edges out of a branch.
|
;; way for reload to insert an output reload on the edges out of a branch.
|
;; If reload is fixed to use insert_insn_on_edge, this can be changed.
|
;; If reload is fixed to use insert_insn_on_edge, this can be changed.
|
(clobber (match_dup 2))]
|
(clobber (match_dup 2))]
|
""
|
""
|
"*
|
"*
|
{
|
{
|
return xstormy16_output_cbranch_si (operands[1], \"%l0\", 0, insn);
|
return xstormy16_output_cbranch_si (operands[1], \"%l0\", 0, insn);
|
}"
|
}"
|
[(set_attr "branch_class" "bcc8p2")
|
[(set_attr "branch_class" "bcc8p2")
|
(set_attr "psw_operand" "clobber")])
|
(set_attr "psw_operand" "clobber")])
|
|
|
(define_insn_and_split "*ineqbranchsi"
|
(define_insn_and_split "*ineqbranchsi"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (match_operator:SI 1 "xstormy16_ineqsi_operator"
|
(if_then_else (match_operator:SI 1 "xstormy16_ineqsi_operator"
|
[(match_operand:SI 2 "register_operand"
|
[(match_operand:SI 2 "register_operand"
|
"r")
|
"r")
|
(match_operand:SI 3 "nonmemory_operand"
|
(match_operand:SI 3 "nonmemory_operand"
|
"ri")])
|
"ri")])
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
;; Although I would greatly like the 'match_dup' in the following line
|
;; Although I would greatly like the 'match_dup' in the following line
|
;; to actually be a register constraint, there is (at the time of writing) no
|
;; to actually be a register constraint, there is (at the time of writing) no
|
;; way for reload to insert an output reload on the edges out of a branch.
|
;; way for reload to insert an output reload on the edges out of a branch.
|
;; If reload is fixed to use insert_insn_on_edge, this can be changed,
|
;; If reload is fixed to use insert_insn_on_edge, this can be changed,
|
;; preferably to a 'minus' operand that explains the actual operation, like:
|
;; preferably to a 'minus' operand that explains the actual operation, like:
|
; (set (match_operand 5 "register_operand" "=2")
|
; (set (match_operand 5 "register_operand" "=2")
|
; (minus:SI (match_operand 6 "register_operand" "2")
|
; (minus:SI (match_operand 6 "register_operand" "2")
|
; (match_operand 7 "register_operand" "3")))
|
; (match_operand 7 "register_operand" "3")))
|
(clobber (match_dup 2))
|
(clobber (match_dup 2))
|
(clobber (match_operand:BI 4 "" "=&y"))]
|
(clobber (match_operand:BI 4 "" "=&y"))]
|
""
|
""
|
"#"
|
"#"
|
"reload_completed"
|
"reload_completed"
|
[(pc)]
|
[(pc)]
|
"{ xstormy16_split_cbranch (SImode, operands[0], operands[1], operands[2],
|
"{ xstormy16_split_cbranch (SImode, operands[0], operands[1], operands[2],
|
operands[4]); DONE; }"
|
operands[4]); DONE; }"
|
[(set_attr "length" "8")])
|
[(set_attr "length" "8")])
|
|
|
(define_insn "*ineqbranch_1"
|
(define_insn "*ineqbranch_1"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (match_operator:HI 5 "xstormy16_ineqsi_operator"
|
(if_then_else (match_operator:HI 5 "xstormy16_ineqsi_operator"
|
[(minus:HI (match_operand:HI 1 "register_operand"
|
[(minus:HI (match_operand:HI 1 "register_operand"
|
"T,r,r")
|
"T,r,r")
|
(zero_extend:HI (match_operand:BI 4
|
(zero_extend:HI (match_operand:BI 4
|
"register_operand"
|
"register_operand"
|
"y,y,y")))
|
"y,y,y")))
|
(match_operand:HI 3 "nonmemory_operand" "L,Ir,i")])
|
(match_operand:HI 3 "nonmemory_operand" "L,Ir,i")])
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(set (match_operand:HI 2 "register_operand" "=1,1,1")
|
(set (match_operand:HI 2 "register_operand" "=1,1,1")
|
(minus:HI (minus:HI (match_dup 1) (zero_extend:HI (match_dup 4)))
|
(minus:HI (minus:HI (match_dup 1) (zero_extend:HI (match_dup 4)))
|
(match_dup 3)))
|
(match_dup 3)))
|
(clobber (match_operand:BI 6 "" "=y,y,y"))]
|
(clobber (match_operand:BI 6 "" "=y,y,y"))]
|
""
|
""
|
"*
|
"*
|
{
|
{
|
return xstormy16_output_cbranch_si (operands[5], \"%l0\", 0, insn);
|
return xstormy16_output_cbranch_si (operands[5], \"%l0\", 0, insn);
|
}"
|
}"
|
[(set_attr "branch_class" "bcc8p2,bcc8p2,bcc8p4")
|
[(set_attr "branch_class" "bcc8p2,bcc8p2,bcc8p4")
|
(set_attr "psw_operand" "2,2,2")])
|
(set_attr "psw_operand" "2,2,2")])
|
|
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: Call and branch instructions
|
;; :: Call and branch instructions
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
;; Subroutine call instruction returning no value. Operand 0 is the function
|
;; Subroutine call instruction returning no value. Operand 0 is the function
|
;; to call; operand 1 is the number of bytes of arguments pushed (in mode
|
;; to call; operand 1 is the number of bytes of arguments pushed (in mode
|
;; `SImode', except it is normally a `const_int'); operand 2 is the number of
|
;; `SImode', except it is normally a `const_int'); operand 2 is the number of
|
;; registers used as operands.
|
;; registers used as operands.
|
|
|
;; On most machines, operand 2 is not actually stored into the RTL pattern. It
|
;; On most machines, operand 2 is not actually stored into the RTL pattern. It
|
;; is supplied for the sake of some RISC machines which need to put this
|
;; is supplied for the sake of some RISC machines which need to put this
|
;; information into the assembler code; they can put it in the RTL instead of
|
;; information into the assembler code; they can put it in the RTL instead of
|
;; operand 1.
|
;; operand 1.
|
|
|
(define_expand "call"
|
(define_expand "call"
|
[(call (match_operand:HI 0 "memory_operand" "m")
|
[(call (match_operand:HI 0 "memory_operand" "m")
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(use (match_operand 2 "immediate_operand" ""))]
|
(use (match_operand 2 "immediate_operand" ""))]
|
""
|
""
|
"xstormy16_expand_call (NULL_RTX, operands[0], operands[1]); DONE;")
|
"xstormy16_expand_call (NULL_RTX, operands[0], operands[1]); DONE;")
|
|
|
;; Subroutine call instruction returning a value. Operand 0 is the hard
|
;; Subroutine call instruction returning a value. Operand 0 is the hard
|
;; register in which the value is returned. There are three more operands, the
|
;; register in which the value is returned. There are three more operands, the
|
;; same as the three operands of the `call' instruction (but with numbers
|
;; same as the three operands of the `call' instruction (but with numbers
|
;; increased by one).
|
;; increased by one).
|
|
|
;; Subroutines that return `BLKmode' objects use the `call' insn.
|
;; Subroutines that return `BLKmode' objects use the `call' insn.
|
|
|
(define_expand "call_value"
|
(define_expand "call_value"
|
[(set (match_operand 0 "register_operand" "=r")
|
[(set (match_operand 0 "register_operand" "=r")
|
(call (match_operand:HI 1 "memory_operand" "m")
|
(call (match_operand:HI 1 "memory_operand" "m")
|
(match_operand:SI 2 "" "")))
|
(match_operand:SI 2 "" "")))
|
(use (match_operand 3 "immediate_operand" ""))]
|
(use (match_operand 3 "immediate_operand" ""))]
|
""
|
""
|
"xstormy16_expand_call (operands[0], operands[1], operands[2]); DONE;")
|
"xstormy16_expand_call (operands[0], operands[1], operands[2]); DONE;")
|
|
|
(define_insn "*call_internal"
|
(define_insn "*call_internal"
|
[(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r"))
|
[(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r"))
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(use (match_operand:HI 2 "nonmemory_operand" "X,z"))]
|
(use (match_operand:HI 2 "nonmemory_operand" "X,z"))]
|
""
|
""
|
"@
|
"@
|
callf %C0
|
callf %C0
|
call %2,%0"
|
call %2,%0"
|
[(set_attr "length" "4,2")
|
[(set_attr "length" "4,2")
|
(set_attr "psw_operand" "clobber")])
|
(set_attr "psw_operand" "clobber")])
|
|
|
(define_insn "*call_value_internal"
|
(define_insn "*call_value_internal"
|
[(set (match_operand 3 "register_operand" "=r,r")
|
[(set (match_operand 3 "register_operand" "=r,r")
|
(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r"))
|
(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r"))
|
(match_operand 1 "" "")))
|
(match_operand 1 "" "")))
|
(use (match_operand:HI 2 "nonmemory_operand" "X,z"))]
|
(use (match_operand:HI 2 "nonmemory_operand" "X,z"))]
|
""
|
""
|
"@
|
"@
|
callf %C0
|
callf %C0
|
call %2,%0"
|
call %2,%0"
|
[(set_attr "length" "4,2")
|
[(set_attr "length" "4,2")
|
(set_attr "psw_operand" "clobber")])
|
(set_attr "psw_operand" "clobber")])
|
|
|
;; Subroutine return
|
;; Subroutine return
|
(define_expand "return"
|
(define_expand "return"
|
[(return)]
|
[(return)]
|
"direct_return()"
|
"direct_return()"
|
"")
|
"")
|
|
|
(define_insn "return_internal"
|
(define_insn "return_internal"
|
[(return)]
|
[(return)]
|
""
|
""
|
"ret"
|
"ret"
|
[(set_attr "psw_operand" "nop")])
|
[(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "return_internal_interrupt"
|
(define_insn "return_internal_interrupt"
|
[(return)
|
[(return)
|
(unspec_volatile [(const_int 0)] 1)]
|
(unspec_volatile [(const_int 0)] 1)]
|
""
|
""
|
"iret"
|
"iret"
|
[(set_attr "psw_operand" "clobber")])
|
[(set_attr "psw_operand" "clobber")])
|
|
|
;; Normal unconditional jump
|
;; Normal unconditional jump
|
(define_insn "jump"
|
(define_insn "jump"
|
[(set (pc) (label_ref (match_operand 0 "" "")))]
|
[(set (pc) (label_ref (match_operand 0 "" "")))]
|
""
|
""
|
"*
|
"*
|
{
|
{
|
return xstormy16_output_cbranch_hi (NULL_RTX, \"%l0\", 0, insn);
|
return xstormy16_output_cbranch_hi (NULL_RTX, \"%l0\", 0, insn);
|
}"
|
}"
|
[(set_attr "branch_class" "br12")
|
[(set_attr "branch_class" "br12")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
;; Indirect jump through a register
|
;; Indirect jump through a register
|
(define_expand "indirect_jump"
|
(define_expand "indirect_jump"
|
[(set (match_dup 1) (const_int 0))
|
[(set (match_dup 1) (const_int 0))
|
(parallel [(set (pc) (match_operand:HI 0 "register_operand" "r"))
|
(parallel [(set (pc) (match_operand:HI 0 "register_operand" "r"))
|
(use (match_dup 1))])]
|
(use (match_dup 1))])]
|
""
|
""
|
"operands[1] = gen_reg_rtx (HImode);")
|
"operands[1] = gen_reg_rtx (HImode);")
|
|
|
(define_insn ""
|
(define_insn ""
|
[(set (pc) (match_operand:HI 0 "register_operand" "r"))
|
[(set (pc) (match_operand:HI 0 "register_operand" "r"))
|
(use (match_operand:HI 1 "register_operand" "z"))]
|
(use (match_operand:HI 1 "register_operand" "z"))]
|
""
|
""
|
"jmp %1,%0"
|
"jmp %1,%0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
;; Table-based switch statements.
|
;; Table-based switch statements.
|
(define_expand "casesi"
|
(define_expand "casesi"
|
[(use (match_operand:SI 0 "register_operand" ""))
|
[(use (match_operand:SI 0 "register_operand" ""))
|
(use (match_operand:SI 1 "immediate_operand" ""))
|
(use (match_operand:SI 1 "immediate_operand" ""))
|
(use (match_operand:SI 2 "immediate_operand" ""))
|
(use (match_operand:SI 2 "immediate_operand" ""))
|
(use (label_ref (match_operand 3 "" "")))
|
(use (label_ref (match_operand 3 "" "")))
|
(use (label_ref (match_operand 4 "" "")))]
|
(use (label_ref (match_operand 4 "" "")))]
|
""
|
""
|
"
|
"
|
{
|
{
|
xstormy16_expand_casesi (operands[0], operands[1], operands[2],
|
xstormy16_expand_casesi (operands[0], operands[1], operands[2],
|
operands[3], operands[4]);
|
operands[3], operands[4]);
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "tablejump_pcrel"
|
(define_insn "tablejump_pcrel"
|
[(set (pc) (mem:HI (plus:HI (pc)
|
[(set (pc) (mem:HI (plus:HI (pc)
|
(match_operand:HI 0 "register_operand" "r"))))
|
(match_operand:HI 0 "register_operand" "r"))))
|
(use (label_ref:SI (match_operand 1 "" "")))]
|
(use (label_ref:SI (match_operand 1 "" "")))]
|
""
|
""
|
"br %0"
|
"br %0"
|
[(set_attr "psw_operand" "nop")])
|
[(set_attr "psw_operand" "nop")])
|
|
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: Prologue and Epilogue instructions
|
;; :: Prologue and Epilogue instructions
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
;; Called after register allocation to add any instructions needed for
|
;; Called after register allocation to add any instructions needed for
|
;; the prologue. Using a prologue insn is favored compared to putting
|
;; the prologue. Using a prologue insn is favored compared to putting
|
;; all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro,
|
;; all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro,
|
;; since it allows the scheduler to intermix instructions with the
|
;; since it allows the scheduler to intermix instructions with the
|
;; saves of the caller saved registers. In some cases, it might be
|
;; saves of the caller saved registers. In some cases, it might be
|
;; necessary to emit a barrier instruction as the last insn to prevent
|
;; necessary to emit a barrier instruction as the last insn to prevent
|
;; such scheduling.
|
;; such scheduling.
|
(define_expand "prologue"
|
(define_expand "prologue"
|
[(const_int 1)]
|
[(const_int 1)]
|
""
|
""
|
"
|
"
|
{
|
{
|
xstormy16_expand_prologue ();
|
xstormy16_expand_prologue ();
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
;; Called after register allocation to add any instructions needed for
|
;; Called after register allocation to add any instructions needed for
|
;; the epilogue. Using an epilogue insn is favored compared to putting
|
;; the epilogue. Using an epilogue insn is favored compared to putting
|
;; all of the instructions in the TARGET_ASM_FUNCTION_EPILOGUE macro,
|
;; all of the instructions in the TARGET_ASM_FUNCTION_EPILOGUE macro,
|
;; since it allows the scheduler to intermix instructions with the
|
;; since it allows the scheduler to intermix instructions with the
|
;; restores of the caller saved registers. In some cases, it might be
|
;; restores of the caller saved registers. In some cases, it might be
|
;; necessary to emit a barrier instruction as the first insn to
|
;; necessary to emit a barrier instruction as the first insn to
|
;; prevent such scheduling.
|
;; prevent such scheduling.
|
(define_expand "epilogue"
|
(define_expand "epilogue"
|
[(const_int 2)]
|
[(const_int 2)]
|
""
|
""
|
"
|
"
|
{
|
{
|
xstormy16_expand_epilogue ();
|
xstormy16_expand_epilogue ();
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
|
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
;; ::
|
;; ::
|
;; :: Miscellaneous instructions
|
;; :: Miscellaneous instructions
|
;; ::
|
;; ::
|
;; ::::::::::::::::::::
|
;; ::::::::::::::::::::
|
|
|
;; No operation, needed in case the user uses -g but not -O.
|
;; No operation, needed in case the user uses -g but not -O.
|
(define_insn "nop"
|
(define_insn "nop"
|
[(const_int 0)]
|
[(const_int 0)]
|
""
|
""
|
"nop"
|
"nop"
|
[(set_attr "psw_operand" "nop")])
|
[(set_attr "psw_operand" "nop")])
|
|
|
;; Pseudo instruction that prevents the scheduler from moving code above this
|
;; Pseudo instruction that prevents the scheduler from moving code above this
|
;; point.
|
;; point.
|
(define_insn "blockage"
|
(define_insn "blockage"
|
[(unspec_volatile [(const_int 0)] 0)]
|
[(unspec_volatile [(const_int 0)] 0)]
|
""
|
""
|
""
|
""
|
[(set_attr "length" "0")
|
[(set_attr "length" "0")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
;;---------------------------------------------------------------------------
|
;;---------------------------------------------------------------------------
|
|
|
(define_expand "iorqi3"
|
(define_expand "iorqi3"
|
[(match_operand:QI 0 "xstormy16_below100_or_register" "")
|
[(match_operand:QI 0 "xstormy16_below100_or_register" "")
|
(match_operand:QI 1 "xstormy16_below100_or_register" "")
|
(match_operand:QI 1 "xstormy16_below100_or_register" "")
|
(match_operand:QI 2 "nonmemory_operand" "")]
|
(match_operand:QI 2 "nonmemory_operand" "")]
|
""
|
""
|
"
|
"
|
{
|
{
|
xstormy16_expand_iorqi3 (operands);
|
xstormy16_expand_iorqi3 (operands);
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "iorqi3_internal"
|
(define_insn "iorqi3_internal"
|
[(set (match_operand:QI 0 "xstormy16_below100_or_register" "=Wr")
|
[(set (match_operand:QI 0 "xstormy16_below100_or_register" "=Wr")
|
(ior:QI (match_operand:QI 1 "xstormy16_below100_or_register" "0")
|
(ior:QI (match_operand:QI 1 "xstormy16_below100_or_register" "0")
|
(match_operand:QI 2 "xstormy16_onebit_set_operand" "i")))]
|
(match_operand:QI 2 "xstormy16_onebit_set_operand" "i")))]
|
""
|
""
|
"set1 %0,%B2"
|
"set1 %0,%B2"
|
[(set_attr "length" "2")
|
[(set_attr "length" "2")
|
(set_attr "psw_operand" "0")])
|
(set_attr "psw_operand" "0")])
|
|
|
(define_peephole2
|
(define_peephole2
|
[(set (match_operand:QI 0 "register_operand" "")
|
[(set (match_operand:QI 0 "register_operand" "")
|
(match_operand:QI 1 "xstormy16_below100_operand" ""))
|
(match_operand:QI 1 "xstormy16_below100_operand" ""))
|
(set (match_operand:HI 2 "register_operand" "")
|
(set (match_operand:HI 2 "register_operand" "")
|
(ior:HI (match_operand:HI 3 "register_operand" "")
|
(ior:HI (match_operand:HI 3 "register_operand" "")
|
(match_operand:QI 4 "xstormy16_onebit_set_operand" "")))
|
(match_operand:QI 4 "xstormy16_onebit_set_operand" "")))
|
(set (match_operand:QI 5 "xstormy16_below100_operand" "")
|
(set (match_operand:QI 5 "xstormy16_below100_operand" "")
|
(match_operand:QI 6 "register_operand" ""))
|
(match_operand:QI 6 "register_operand" ""))
|
]
|
]
|
"REGNO (operands[0]) == REGNO (operands[2])
|
"REGNO (operands[0]) == REGNO (operands[2])
|
&& REGNO (operands[0]) == REGNO (operands[3])
|
&& REGNO (operands[0]) == REGNO (operands[3])
|
&& REGNO (operands[0]) == REGNO (operands[6])
|
&& REGNO (operands[0]) == REGNO (operands[6])
|
&& rtx_equal_p (operands[1], operands[5])"
|
&& rtx_equal_p (operands[1], operands[5])"
|
[(set (match_dup 1)
|
[(set (match_dup 1)
|
(ior:QI (match_dup 1)
|
(ior:QI (match_dup 1)
|
(match_dup 4)))
|
(match_dup 4)))
|
]
|
]
|
"")
|
"")
|
|
|
|
|
(define_expand "andqi3"
|
(define_expand "andqi3"
|
[(match_operand:QI 0 "xstormy16_below100_or_register" "")
|
[(match_operand:QI 0 "xstormy16_below100_or_register" "")
|
(match_operand:QI 1 "xstormy16_below100_or_register" "")
|
(match_operand:QI 1 "xstormy16_below100_or_register" "")
|
(match_operand:QI 2 "nonmemory_operand" "")]
|
(match_operand:QI 2 "nonmemory_operand" "")]
|
""
|
""
|
"
|
"
|
{
|
{
|
xstormy16_expand_andqi3 (operands);
|
xstormy16_expand_andqi3 (operands);
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "andqi3_internal"
|
(define_insn "andqi3_internal"
|
[(set (match_operand:QI 0 "xstormy16_below100_or_register" "=Wr")
|
[(set (match_operand:QI 0 "xstormy16_below100_or_register" "=Wr")
|
(and:QI (match_operand:QI 1 "xstormy16_below100_or_register" "0")
|
(and:QI (match_operand:QI 1 "xstormy16_below100_or_register" "0")
|
(match_operand:QI 2 "xstormy16_onebit_clr_operand" "i")))]
|
(match_operand:QI 2 "xstormy16_onebit_clr_operand" "i")))]
|
""
|
""
|
"clr1 %0,%B2"
|
"clr1 %0,%B2"
|
[(set_attr "length" "2")
|
[(set_attr "length" "2")
|
(set_attr "psw_operand" "0")])
|
(set_attr "psw_operand" "0")])
|
|
|
(define_peephole2
|
(define_peephole2
|
[(set (match_operand:HI 0 "register_operand" "")
|
[(set (match_operand:HI 0 "register_operand" "")
|
(and:HI (match_operand:HI 1 "register_operand" "")
|
(and:HI (match_operand:HI 1 "register_operand" "")
|
(match_operand 2 "immediate_operand" "")))
|
(match_operand 2 "immediate_operand" "")))
|
(set (match_operand:HI 3 "register_operand" "")
|
(set (match_operand:HI 3 "register_operand" "")
|
(zero_extend:HI (match_operand:QI 4 "register_operand" "")));
|
(zero_extend:HI (match_operand:QI 4 "register_operand" "")));
|
]
|
]
|
"REGNO (operands[0]) == REGNO (operands[1])
|
"REGNO (operands[0]) == REGNO (operands[1])
|
&& REGNO (operands[0]) == REGNO (operands[3])
|
&& REGNO (operands[0]) == REGNO (operands[3])
|
&& REGNO (operands[0]) == REGNO (operands[4])"
|
&& REGNO (operands[0]) == REGNO (operands[4])"
|
[(set (match_dup 0)
|
[(set (match_dup 0)
|
(and:HI (match_dup 1)
|
(and:HI (match_dup 1)
|
(match_dup 5)))
|
(match_dup 5)))
|
]
|
]
|
"operands[5] = GEN_INT (INTVAL (operands[2]) & 0xff);")
|
"operands[5] = GEN_INT (INTVAL (operands[2]) & 0xff);")
|
|
|
(define_peephole2
|
(define_peephole2
|
[(set (match_operand:QI 0 "register_operand" "")
|
[(set (match_operand:QI 0 "register_operand" "")
|
(match_operand:QI 1 "xstormy16_below100_operand" ""))
|
(match_operand:QI 1 "xstormy16_below100_operand" ""))
|
(set (match_operand:HI 2 "register_operand" "")
|
(set (match_operand:HI 2 "register_operand" "")
|
(and:HI (match_operand:HI 3 "register_operand" "")
|
(and:HI (match_operand:HI 3 "register_operand" "")
|
(match_operand:QI 4 "xstormy16_onebit_clr_operand" "")))
|
(match_operand:QI 4 "xstormy16_onebit_clr_operand" "")))
|
(set (match_operand:QI 5 "xstormy16_below100_operand" "")
|
(set (match_operand:QI 5 "xstormy16_below100_operand" "")
|
(match_operand:QI 6 "register_operand" ""))
|
(match_operand:QI 6 "register_operand" ""))
|
]
|
]
|
"REGNO (operands[0]) == REGNO (operands[2])
|
"REGNO (operands[0]) == REGNO (operands[2])
|
&& REGNO (operands[0]) == REGNO (operands[3])
|
&& REGNO (operands[0]) == REGNO (operands[3])
|
&& REGNO (operands[0]) == REGNO (operands[6])
|
&& REGNO (operands[0]) == REGNO (operands[6])
|
&& rtx_equal_p (operands[1], operands[5])"
|
&& rtx_equal_p (operands[1], operands[5])"
|
[(set (match_dup 1)
|
[(set (match_dup 1)
|
(and:QI (match_dup 1)
|
(and:QI (match_dup 1)
|
(match_dup 4)))
|
(match_dup 4)))
|
]
|
]
|
"")
|
"")
|
|
|
;; GCC uses different techniques to optimize MSB and LSB accesses, so
|
;; GCC uses different techniques to optimize MSB and LSB accesses, so
|
;; we have to code those separately.
|
;; we have to code those separately.
|
|
|
(define_insn "*bclrx"
|
(define_insn "*bclrx"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (eq:HI (and:QI (match_operand:QI 1 "xstormy16_below100_operand" "W")
|
(if_then_else (eq:HI (and:QI (match_operand:QI 1 "xstormy16_below100_operand" "W")
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 3 "" "=y"))]
|
(clobber (match_operand:BI 3 "" "=y"))]
|
""
|
""
|
"bn %1,%B2,%l0"
|
"bn %1,%B2,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "*bclrx2"
|
(define_insn "*bclrx2"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (zero_extract:HI
|
(if_then_else (zero_extract:HI
|
(xor:HI (subreg:HI
|
(xor:HI (subreg:HI
|
(match_operand:QI 1 "xstormy16_below100_operand" "W") 0)
|
(match_operand:QI 1 "xstormy16_below100_operand" "W") 0)
|
(match_operand:HI 2 "xstormy16_onebit_set_operand" "J"))
|
(match_operand:HI 2 "xstormy16_onebit_set_operand" "J"))
|
(const_int 1)
|
(const_int 1)
|
(match_operand:HI 3 "immediate_operand" "i"))
|
(match_operand:HI 3 "immediate_operand" "i"))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 4 "" "=y"))]
|
(clobber (match_operand:BI 4 "" "=y"))]
|
""
|
""
|
"bn %1,%B2,%l0"
|
"bn %1,%B2,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "*bclrx3"
|
(define_insn "*bclrx3"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (eq:HI (and:HI (zero_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
|
(if_then_else (eq:HI (and:HI (zero_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 3 "" "=y"))]
|
(clobber (match_operand:BI 3 "" "=y"))]
|
""
|
""
|
"bn %1,%B2,%l0"
|
"bn %1,%B2,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "*bclr7"
|
(define_insn "*bclr7"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (xor:HI (lshiftrt:HI (subreg:HI
|
(if_then_else (xor:HI (lshiftrt:HI (subreg:HI
|
(match_operand:QI 1 "xstormy16_below100_operand" "W") 0)
|
(match_operand:QI 1 "xstormy16_below100_operand" "W") 0)
|
(const_int 7))
|
(const_int 7))
|
(const_int 1))
|
(const_int 1))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 2 "" "=y"))]
|
(clobber (match_operand:BI 2 "" "=y"))]
|
""
|
""
|
"bn %1,#7,%l0"
|
"bn %1,#7,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "*bclr15"
|
(define_insn "*bclr15"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (ge:HI (sign_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
|
(if_then_else (ge:HI (sign_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 2 "" "=y"))]
|
(clobber (match_operand:BI 2 "" "=y"))]
|
""
|
""
|
"bn %1,#7,%l0"
|
"bn %1,#7,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "*bsetx"
|
(define_insn "*bsetx"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (ne:HI (and:QI (match_operand:QI 1 "xstormy16_below100_operand" "W")
|
(if_then_else (ne:HI (and:QI (match_operand:QI 1 "xstormy16_below100_operand" "W")
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 3 "" "=y"))]
|
(clobber (match_operand:BI 3 "" "=y"))]
|
""
|
""
|
"bp %1,%B2,%l0"
|
"bp %1,%B2,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "*bsetx2"
|
(define_insn "*bsetx2"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (zero_extract:HI (match_operand:QI 1 "xstormy16_below100_operand" "W")
|
(if_then_else (zero_extract:HI (match_operand:QI 1 "xstormy16_below100_operand" "W")
|
(const_int 1)
|
(const_int 1)
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 3 "" "=y"))]
|
(clobber (match_operand:BI 3 "" "=y"))]
|
""
|
""
|
"bp %1,%b2,%l0"
|
"bp %1,%b2,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "*bsetx3"
|
(define_insn "*bsetx3"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (ne:HI (and:HI (zero_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
|
(if_then_else (ne:HI (and:HI (zero_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(match_operand:HI 2 "immediate_operand" "i"))
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 3 "" "=y"))]
|
(clobber (match_operand:BI 3 "" "=y"))]
|
""
|
""
|
"bp %1,%B2,%l0"
|
"bp %1,%B2,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "*bset7"
|
(define_insn "*bset7"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (lshiftrt:HI (subreg:HI (match_operand:QI 1 "xstormy16_below100_operand" "W") 0)
|
(if_then_else (lshiftrt:HI (subreg:HI (match_operand:QI 1 "xstormy16_below100_operand" "W") 0)
|
(const_int 7))
|
(const_int 7))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 2 "" "=y"))]
|
(clobber (match_operand:BI 2 "" "=y"))]
|
""
|
""
|
"bp %1,#7,%l0"
|
"bp %1,#7,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
(define_insn "*bset15"
|
(define_insn "*bset15"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (lt:HI (sign_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
|
(if_then_else (lt:HI (sign_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W"))
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (match_operand:BI 2 "" "=y"))]
|
(clobber (match_operand:BI 2 "" "=y"))]
|
""
|
""
|
"bp %1,#7,%l0"
|
"bp %1,#7,%l0"
|
[(set_attr "length" "4")
|
[(set_attr "length" "4")
|
(set_attr "psw_operand" "nop")])
|
(set_attr "psw_operand" "nop")])
|
|
|
