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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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Rev 149 |
Rev 154 |
/* PR target/11965 */
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/* PR target/11965 */
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/* Originator: <jk@tools.de> */
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/* Originator: <jk@tools.de> */
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/* { dg-do run { target sparc*-*-* } } */
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/* { dg-do run { target sparc*-*-* } } */
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/* { dg-options "-O -mcpu=ultrasparc" } */
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/* { dg-options "-O -mcpu=ultrasparc" } */
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/* This used to fail on 32-bit Ultrasparc because GCC emitted
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/* This used to fail on 32-bit Ultrasparc because GCC emitted
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an invalid shift instruction. */
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an invalid shift instruction. */
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static inline unsigned int shift(int n, unsigned int value)
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static inline unsigned int shift(int n, unsigned int value)
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{
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{
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return value << n;
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return value << n;
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}
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}
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unsigned int val = 1;
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unsigned int val = 1;
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int main(void)
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int main(void)
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{
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{
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int i;
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int i;
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for (i = 0; i < 4; i++)
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for (i = 0; i < 4; i++)
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val = shift(32, val);
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val = shift(32, val);
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return 0;
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return 0;
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}
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}
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