/* Opcode table for the TI MSP430 microcontrollers
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/* Opcode table for the TI MSP430 microcontrollers
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Copyright 2002, 2004 Free Software Foundation, Inc.
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Copyright 2002, 2004 Free Software Foundation, Inc.
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Contributed by Dmitry Diky <diwil@mail.ru>
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Contributed by Dmitry Diky <diwil@mail.ru>
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef __MSP430_H_
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#ifndef __MSP430_H_
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#define __MSP430_H_
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#define __MSP430_H_
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struct msp430_operand_s
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struct msp430_operand_s
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{
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{
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int ol; /* Operand length words. */
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int ol; /* Operand length words. */
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int am; /* Addr mode. */
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int am; /* Addr mode. */
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int reg; /* Register. */
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int reg; /* Register. */
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int mode; /* Pperand mode. */
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int mode; /* Pperand mode. */
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#define OP_REG 0
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#define OP_REG 0
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#define OP_EXP 1
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#define OP_EXP 1
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#ifndef DASM_SECTION
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#ifndef DASM_SECTION
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expressionS exp;
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expressionS exp;
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#endif
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#endif
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};
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};
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#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */
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#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */
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struct msp430_opcode_s
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struct msp430_opcode_s
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{
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{
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char *name;
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char *name;
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int fmt;
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int fmt;
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int insn_opnumb;
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int insn_opnumb;
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int bin_opcode;
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int bin_opcode;
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int bin_mask;
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int bin_mask;
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};
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};
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#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask }
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#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask }
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static struct msp430_opcode_s msp430_opcodes[] =
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static struct msp430_opcode_s msp430_opcodes[] =
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{
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{
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MSP_INSN (and, 1, 2, 0xf000, 0xf000),
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MSP_INSN (and, 1, 2, 0xf000, 0xf000),
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MSP_INSN (inv, 0, 1, 0xe330, 0xfff0),
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MSP_INSN (inv, 0, 1, 0xe330, 0xfff0),
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MSP_INSN (xor, 1, 2, 0xe000, 0xf000),
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MSP_INSN (xor, 1, 2, 0xe000, 0xf000),
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MSP_INSN (setz, 0, 0, 0xd322, 0xffff),
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MSP_INSN (setz, 0, 0, 0xd322, 0xffff),
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MSP_INSN (setc, 0, 0, 0xd312, 0xffff),
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MSP_INSN (setc, 0, 0, 0xd312, 0xffff),
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MSP_INSN (eint, 0, 0, 0xd232, 0xffff),
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MSP_INSN (eint, 0, 0, 0xd232, 0xffff),
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MSP_INSN (setn, 0, 0, 0xd222, 0xffff),
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MSP_INSN (setn, 0, 0, 0xd222, 0xffff),
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MSP_INSN (bis, 1, 2, 0xd000, 0xf000),
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MSP_INSN (bis, 1, 2, 0xd000, 0xf000),
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MSP_INSN (clrz, 0, 0, 0xc322, 0xffff),
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MSP_INSN (clrz, 0, 0, 0xc322, 0xffff),
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MSP_INSN (clrc, 0, 0, 0xc312, 0xffff),
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MSP_INSN (clrc, 0, 0, 0xc312, 0xffff),
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MSP_INSN (dint, 0, 0, 0xc232, 0xffff),
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MSP_INSN (dint, 0, 0, 0xc232, 0xffff),
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MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),
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MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),
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MSP_INSN (bic, 1, 2, 0xc000, 0xf000),
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MSP_INSN (bic, 1, 2, 0xc000, 0xf000),
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MSP_INSN (bit, 1, 2, 0xb000, 0xf000),
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MSP_INSN (bit, 1, 2, 0xb000, 0xf000),
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MSP_INSN (dadc, 0, 1, 0xa300, 0xff30),
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MSP_INSN (dadc, 0, 1, 0xa300, 0xff30),
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MSP_INSN (dadd, 1, 2, 0xa000, 0xf000),
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MSP_INSN (dadd, 1, 2, 0xa000, 0xf000),
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MSP_INSN (tst, 0, 1, 0x9300, 0xff30),
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MSP_INSN (tst, 0, 1, 0x9300, 0xff30),
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MSP_INSN (cmp, 1, 2, 0x9000, 0xf000),
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MSP_INSN (cmp, 1, 2, 0x9000, 0xf000),
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MSP_INSN (decd, 0, 1, 0x8320, 0xff30),
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MSP_INSN (decd, 0, 1, 0x8320, 0xff30),
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MSP_INSN (dec, 0, 1, 0x8310, 0xff30),
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MSP_INSN (dec, 0, 1, 0x8310, 0xff30),
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MSP_INSN (sub, 1, 2, 0x8000, 0xf000),
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MSP_INSN (sub, 1, 2, 0x8000, 0xf000),
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MSP_INSN (sbc, 0, 1, 0x7300, 0xff30),
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MSP_INSN (sbc, 0, 1, 0x7300, 0xff30),
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MSP_INSN (subc, 1, 2, 0x7000, 0xf000),
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MSP_INSN (subc, 1, 2, 0x7000, 0xf000),
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MSP_INSN (adc, 0, 1, 0x6300, 0xff30),
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MSP_INSN (adc, 0, 1, 0x6300, 0xff30),
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MSP_INSN (rlc, 0, 2, 0x6000, 0xf000),
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MSP_INSN (rlc, 0, 2, 0x6000, 0xf000),
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MSP_INSN (addc, 1, 2, 0x6000, 0xf000),
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MSP_INSN (addc, 1, 2, 0x6000, 0xf000),
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MSP_INSN (incd, 0, 1, 0x5320, 0xff30),
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MSP_INSN (incd, 0, 1, 0x5320, 0xff30),
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MSP_INSN (inc, 0, 1, 0x5310, 0xff30),
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MSP_INSN (inc, 0, 1, 0x5310, 0xff30),
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MSP_INSN (rla, 0, 2, 0x5000, 0xf000),
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MSP_INSN (rla, 0, 2, 0x5000, 0xf000),
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MSP_INSN (add, 1, 2, 0x5000, 0xf000),
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MSP_INSN (add, 1, 2, 0x5000, 0xf000),
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MSP_INSN (nop, 0, 0, 0x4303, 0xffff),
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MSP_INSN (nop, 0, 0, 0x4303, 0xffff),
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MSP_INSN (clr, 0, 1, 0x4300, 0xff30),
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MSP_INSN (clr, 0, 1, 0x4300, 0xff30),
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MSP_INSN (ret, 0, 0, 0x4130, 0xff30),
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MSP_INSN (ret, 0, 0, 0x4130, 0xff30),
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MSP_INSN (pop, 0, 1, 0x4130, 0xff30),
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MSP_INSN (pop, 0, 1, 0x4130, 0xff30),
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MSP_INSN (br, 0, 3, 0x4000, 0xf000),
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MSP_INSN (br, 0, 3, 0x4000, 0xf000),
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MSP_INSN (mov, 1, 2, 0x4000, 0xf000),
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MSP_INSN (mov, 1, 2, 0x4000, 0xf000),
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MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00),
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MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00),
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MSP_INSN (jl, 3, 1, 0x3800, 0xfc00),
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MSP_INSN (jl, 3, 1, 0x3800, 0xfc00),
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MSP_INSN (jge, 3, 1, 0x3400, 0xfc00),
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MSP_INSN (jge, 3, 1, 0x3400, 0xfc00),
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MSP_INSN (jn, 3, 1, 0x3000, 0xfc00),
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MSP_INSN (jn, 3, 1, 0x3000, 0xfc00),
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MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00),
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MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00),
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MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00),
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MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00),
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MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00),
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MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00),
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MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00),
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MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00),
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MSP_INSN (jz, 3, 1, 0x2400, 0xfc00),
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MSP_INSN (jz, 3, 1, 0x2400, 0xfc00),
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MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00),
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MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00),
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MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00),
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MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00),
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MSP_INSN (jne, 3, 1, 0x2000, 0xfc00),
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MSP_INSN (jne, 3, 1, 0x2000, 0xfc00),
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MSP_INSN (reti, 2, 0, 0x1300, 0xffc0),
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MSP_INSN (reti, 2, 0, 0x1300, 0xffc0),
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MSP_INSN (call, 2, 1, 0x1280, 0xffc0),
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MSP_INSN (call, 2, 1, 0x1280, 0xffc0),
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MSP_INSN (push, 2, 1, 0x1200, 0xff80),
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MSP_INSN (push, 2, 1, 0x1200, 0xff80),
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MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0),
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MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0),
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MSP_INSN (rra, 2, 1, 0x1100, 0xff80),
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MSP_INSN (rra, 2, 1, 0x1100, 0xff80),
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MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0),
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MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0),
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MSP_INSN (rrc, 2, 1, 0x1000, 0xff80),
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MSP_INSN (rrc, 2, 1, 0x1000, 0xff80),
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/* Simple polymorphs. */
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/* Simple polymorphs. */
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MSP_INSN (beq, 4, 0, 0, 0xffff),
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MSP_INSN (beq, 4, 0, 0, 0xffff),
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MSP_INSN (bne, 4, 1, 0, 0xffff),
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MSP_INSN (bne, 4, 1, 0, 0xffff),
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MSP_INSN (blt, 4, 2, 0, 0xffff),
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MSP_INSN (blt, 4, 2, 0, 0xffff),
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MSP_INSN (bltu, 4, 3, 0, 0xffff),
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MSP_INSN (bltu, 4, 3, 0, 0xffff),
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MSP_INSN (bge, 4, 4, 0, 0xffff),
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MSP_INSN (bge, 4, 4, 0, 0xffff),
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MSP_INSN (bgeu, 4, 5, 0, 0xffff),
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MSP_INSN (bgeu, 4, 5, 0, 0xffff),
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MSP_INSN (bltn, 4, 6, 0, 0xffff),
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MSP_INSN (bltn, 4, 6, 0, 0xffff),
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MSP_INSN (jump, 4, 7, 0, 0xffff),
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MSP_INSN (jump, 4, 7, 0, 0xffff),
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/* Long polymorphs. */
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/* Long polymorphs. */
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MSP_INSN (bgt, 5, 0, 0, 0xffff),
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MSP_INSN (bgt, 5, 0, 0, 0xffff),
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MSP_INSN (bgtu, 5, 1, 0, 0xffff),
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MSP_INSN (bgtu, 5, 1, 0, 0xffff),
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MSP_INSN (bleu, 5, 2, 0, 0xffff),
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MSP_INSN (bleu, 5, 2, 0, 0xffff),
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MSP_INSN (ble, 5, 3, 0, 0xffff),
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MSP_INSN (ble, 5, 3, 0, 0xffff),
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/* End of instruction set. */
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/* End of instruction set. */
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{ NULL, 0, 0, 0, 0 }
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{ NULL, 0, 0, 0, 0 }
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};
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};
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#endif
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#endif
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