/* Simulator parallel routines for CGEN simulators (and maybe others).
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/* Simulator parallel routines for CGEN simulators (and maybe others).
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Copyright (C) 1999, 2000, 2007, 2008 Free Software Foundation, Inc.
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Copyright (C) 1999, 2000, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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Contributed by Cygnus Solutions.
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This file is part of the GNU instruction set simulator.
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This file is part of the GNU instruction set simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "sim-main.h"
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#include "sim-main.h"
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#include "cgen-mem.h"
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#include "cgen-mem.h"
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#include "cgen-par.h"
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#include "cgen-par.h"
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/* Functions required by the cgen interface. These functions add various
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/* Functions required by the cgen interface. These functions add various
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kinds of writes to the write queue. */
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kinds of writes to the write queue. */
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void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value)
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void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_BI_WRITE;
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element->kind = CGEN_BI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.bi_write.target = target;
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element->kinds.bi_write.target = target;
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element->kinds.bi_write.value = value;
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element->kinds.bi_write.value = value;
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}
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}
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void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value)
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void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_QI_WRITE;
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element->kind = CGEN_QI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.qi_write.target = target;
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element->kinds.qi_write.target = target;
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element->kinds.qi_write.value = value;
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element->kinds.qi_write.value = value;
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}
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}
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void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value)
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void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_SI_WRITE;
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element->kind = CGEN_SI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.si_write.target = target;
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element->kinds.si_write.target = target;
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element->kinds.si_write.value = value;
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element->kinds.si_write.value = value;
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}
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}
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void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value)
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void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_SF_WRITE;
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element->kind = CGEN_SF_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.sf_write.target = target;
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element->kinds.sf_write.target = target;
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element->kinds.sf_write.value = value;
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element->kinds.sf_write.value = value;
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}
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}
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void sim_queue_pc_write (SIM_CPU *cpu, USI value)
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void sim_queue_pc_write (SIM_CPU *cpu, USI value)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_PC_WRITE;
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element->kind = CGEN_PC_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.pc_write.value = value;
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element->kinds.pc_write.value = value;
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}
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}
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void sim_queue_fn_hi_write (
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void sim_queue_fn_hi_write (
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SIM_CPU *cpu,
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, UHI),
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void (*write_function)(SIM_CPU *cpu, UINT, UHI),
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UINT regno,
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UINT regno,
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UHI value
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UHI value
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)
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)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_HI_WRITE;
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element->kind = CGEN_FN_HI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_hi_write.function = write_function;
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element->kinds.fn_hi_write.function = write_function;
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element->kinds.fn_hi_write.regno = regno;
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element->kinds.fn_hi_write.regno = regno;
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element->kinds.fn_hi_write.value = value;
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element->kinds.fn_hi_write.value = value;
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}
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}
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void sim_queue_fn_si_write (
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void sim_queue_fn_si_write (
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SIM_CPU *cpu,
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, USI),
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void (*write_function)(SIM_CPU *cpu, UINT, USI),
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UINT regno,
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UINT regno,
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USI value
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USI value
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)
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)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_SI_WRITE;
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element->kind = CGEN_FN_SI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_si_write.function = write_function;
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element->kinds.fn_si_write.function = write_function;
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element->kinds.fn_si_write.regno = regno;
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element->kinds.fn_si_write.regno = regno;
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element->kinds.fn_si_write.value = value;
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element->kinds.fn_si_write.value = value;
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}
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}
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void sim_queue_fn_sf_write (
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void sim_queue_fn_sf_write (
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SIM_CPU *cpu,
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, SF),
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void (*write_function)(SIM_CPU *cpu, UINT, SF),
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UINT regno,
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UINT regno,
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SF value
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SF value
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)
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)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_SF_WRITE;
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element->kind = CGEN_FN_SF_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_sf_write.function = write_function;
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element->kinds.fn_sf_write.function = write_function;
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element->kinds.fn_sf_write.regno = regno;
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element->kinds.fn_sf_write.regno = regno;
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element->kinds.fn_sf_write.value = value;
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element->kinds.fn_sf_write.value = value;
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}
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}
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void sim_queue_fn_di_write (
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void sim_queue_fn_di_write (
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SIM_CPU *cpu,
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, DI),
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void (*write_function)(SIM_CPU *cpu, UINT, DI),
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UINT regno,
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UINT regno,
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DI value
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DI value
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)
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)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_DI_WRITE;
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element->kind = CGEN_FN_DI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_di_write.function = write_function;
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element->kinds.fn_di_write.function = write_function;
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element->kinds.fn_di_write.regno = regno;
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element->kinds.fn_di_write.regno = regno;
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element->kinds.fn_di_write.value = value;
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element->kinds.fn_di_write.value = value;
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}
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}
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void sim_queue_fn_xi_write (
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void sim_queue_fn_xi_write (
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SIM_CPU *cpu,
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, SI *),
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void (*write_function)(SIM_CPU *cpu, UINT, SI *),
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UINT regno,
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UINT regno,
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SI *value
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SI *value
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)
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)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_XI_WRITE;
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element->kind = CGEN_FN_XI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_xi_write.function = write_function;
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element->kinds.fn_xi_write.function = write_function;
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element->kinds.fn_xi_write.regno = regno;
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element->kinds.fn_xi_write.regno = regno;
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element->kinds.fn_xi_write.value[0] = value[0];
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element->kinds.fn_xi_write.value[0] = value[0];
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element->kinds.fn_xi_write.value[1] = value[1];
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element->kinds.fn_xi_write.value[1] = value[1];
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element->kinds.fn_xi_write.value[2] = value[2];
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element->kinds.fn_xi_write.value[2] = value[2];
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element->kinds.fn_xi_write.value[3] = value[3];
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element->kinds.fn_xi_write.value[3] = value[3];
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}
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}
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void sim_queue_fn_df_write (
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void sim_queue_fn_df_write (
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SIM_CPU *cpu,
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, DF),
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void (*write_function)(SIM_CPU *cpu, UINT, DF),
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UINT regno,
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UINT regno,
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DF value
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DF value
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)
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)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_DF_WRITE;
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element->kind = CGEN_FN_DF_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_df_write.function = write_function;
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element->kinds.fn_df_write.function = write_function;
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element->kinds.fn_df_write.regno = regno;
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element->kinds.fn_df_write.regno = regno;
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element->kinds.fn_df_write.value = value;
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element->kinds.fn_df_write.value = value;
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}
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}
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void sim_queue_fn_pc_write (
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void sim_queue_fn_pc_write (
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SIM_CPU *cpu,
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, USI),
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void (*write_function)(SIM_CPU *cpu, USI),
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USI value
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USI value
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)
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)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_PC_WRITE;
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element->kind = CGEN_FN_PC_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_pc_write.function = write_function;
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element->kinds.fn_pc_write.function = write_function;
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element->kinds.fn_pc_write.value = value;
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element->kinds.fn_pc_write.value = value;
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}
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}
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void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value)
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void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_QI_WRITE;
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element->kind = CGEN_MEM_QI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_qi_write.address = address;
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element->kinds.mem_qi_write.address = address;
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element->kinds.mem_qi_write.value = value;
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element->kinds.mem_qi_write.value = value;
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}
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}
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void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value)
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void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_HI_WRITE;
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element->kind = CGEN_MEM_HI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_hi_write.address = address;
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element->kinds.mem_hi_write.address = address;
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element->kinds.mem_hi_write.value = value;
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element->kinds.mem_hi_write.value = value;
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}
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}
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void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value)
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void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_SI_WRITE;
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element->kind = CGEN_MEM_SI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_si_write.address = address;
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element->kinds.mem_si_write.address = address;
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element->kinds.mem_si_write.value = value;
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element->kinds.mem_si_write.value = value;
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}
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}
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void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value)
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void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value)
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{
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_DI_WRITE;
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element->kind = CGEN_MEM_DI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_di_write.address = address;
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element->kinds.mem_di_write.address = address;
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element->kinds.mem_di_write.value = value;
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element->kinds.mem_di_write.value = value;
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}
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}
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|
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void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value)
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void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value)
|
{
|
{
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_DF_WRITE;
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element->kind = CGEN_MEM_DF_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_df_write.address = address;
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element->kinds.mem_df_write.address = address;
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element->kinds.mem_df_write.value = value;
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element->kinds.mem_df_write.value = value;
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}
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}
|
|
|
void sim_queue_mem_xi_write (SIM_CPU *cpu, SI address, SI *value)
|
void sim_queue_mem_xi_write (SIM_CPU *cpu, SI address, SI *value)
|
{
|
{
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
element->kind = CGEN_MEM_XI_WRITE;
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element->kind = CGEN_MEM_XI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->insn_address = CPU_PC_GET (cpu);
|
element->kinds.mem_xi_write.address = address;
|
element->kinds.mem_xi_write.address = address;
|
element->kinds.mem_xi_write.value[0] = value[0];
|
element->kinds.mem_xi_write.value[0] = value[0];
|
element->kinds.mem_xi_write.value[1] = value[1];
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element->kinds.mem_xi_write.value[1] = value[1];
|
element->kinds.mem_xi_write.value[2] = value[2];
|
element->kinds.mem_xi_write.value[2] = value[2];
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element->kinds.mem_xi_write.value[3] = value[3];
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element->kinds.mem_xi_write.value[3] = value[3];
|
}
|
}
|
|
|
void sim_queue_fn_mem_qi_write (
|
void sim_queue_fn_mem_qi_write (
|
SIM_CPU *cpu,
|
SIM_CPU *cpu,
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, QI),
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, QI),
|
SI address,
|
SI address,
|
QI value
|
QI value
|
)
|
)
|
{
|
{
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
element->kind = CGEN_FN_MEM_QI_WRITE;
|
element->kind = CGEN_FN_MEM_QI_WRITE;
|
element->insn_address = CPU_PC_GET (cpu);
|
element->insn_address = CPU_PC_GET (cpu);
|
element->kinds.fn_mem_qi_write.function = write_function;
|
element->kinds.fn_mem_qi_write.function = write_function;
|
element->kinds.fn_mem_qi_write.address = address;
|
element->kinds.fn_mem_qi_write.address = address;
|
element->kinds.fn_mem_qi_write.value = value;
|
element->kinds.fn_mem_qi_write.value = value;
|
}
|
}
|
|
|
void sim_queue_fn_mem_hi_write (
|
void sim_queue_fn_mem_hi_write (
|
SIM_CPU *cpu,
|
SIM_CPU *cpu,
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, HI),
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, HI),
|
SI address,
|
SI address,
|
HI value
|
HI value
|
)
|
)
|
{
|
{
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
element->kind = CGEN_FN_MEM_HI_WRITE;
|
element->kind = CGEN_FN_MEM_HI_WRITE;
|
element->insn_address = CPU_PC_GET (cpu);
|
element->insn_address = CPU_PC_GET (cpu);
|
element->kinds.fn_mem_hi_write.function = write_function;
|
element->kinds.fn_mem_hi_write.function = write_function;
|
element->kinds.fn_mem_hi_write.address = address;
|
element->kinds.fn_mem_hi_write.address = address;
|
element->kinds.fn_mem_hi_write.value = value;
|
element->kinds.fn_mem_hi_write.value = value;
|
}
|
}
|
|
|
void sim_queue_fn_mem_si_write (
|
void sim_queue_fn_mem_si_write (
|
SIM_CPU *cpu,
|
SIM_CPU *cpu,
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI),
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI),
|
SI address,
|
SI address,
|
SI value
|
SI value
|
)
|
)
|
{
|
{
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
element->kind = CGEN_FN_MEM_SI_WRITE;
|
element->kind = CGEN_FN_MEM_SI_WRITE;
|
element->insn_address = CPU_PC_GET (cpu);
|
element->insn_address = CPU_PC_GET (cpu);
|
element->kinds.fn_mem_si_write.function = write_function;
|
element->kinds.fn_mem_si_write.function = write_function;
|
element->kinds.fn_mem_si_write.address = address;
|
element->kinds.fn_mem_si_write.address = address;
|
element->kinds.fn_mem_si_write.value = value;
|
element->kinds.fn_mem_si_write.value = value;
|
}
|
}
|
|
|
void sim_queue_fn_mem_di_write (
|
void sim_queue_fn_mem_di_write (
|
SIM_CPU *cpu,
|
SIM_CPU *cpu,
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, DI),
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, DI),
|
SI address,
|
SI address,
|
DI value
|
DI value
|
)
|
)
|
{
|
{
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
element->kind = CGEN_FN_MEM_DI_WRITE;
|
element->kind = CGEN_FN_MEM_DI_WRITE;
|
element->insn_address = CPU_PC_GET (cpu);
|
element->insn_address = CPU_PC_GET (cpu);
|
element->kinds.fn_mem_di_write.function = write_function;
|
element->kinds.fn_mem_di_write.function = write_function;
|
element->kinds.fn_mem_di_write.address = address;
|
element->kinds.fn_mem_di_write.address = address;
|
element->kinds.fn_mem_di_write.value = value;
|
element->kinds.fn_mem_di_write.value = value;
|
}
|
}
|
|
|
void sim_queue_fn_mem_df_write (
|
void sim_queue_fn_mem_df_write (
|
SIM_CPU *cpu,
|
SIM_CPU *cpu,
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, DF),
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, DF),
|
SI address,
|
SI address,
|
DF value
|
DF value
|
)
|
)
|
{
|
{
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
element->kind = CGEN_FN_MEM_DF_WRITE;
|
element->kind = CGEN_FN_MEM_DF_WRITE;
|
element->insn_address = CPU_PC_GET (cpu);
|
element->insn_address = CPU_PC_GET (cpu);
|
element->kinds.fn_mem_df_write.function = write_function;
|
element->kinds.fn_mem_df_write.function = write_function;
|
element->kinds.fn_mem_df_write.address = address;
|
element->kinds.fn_mem_df_write.address = address;
|
element->kinds.fn_mem_df_write.value = value;
|
element->kinds.fn_mem_df_write.value = value;
|
}
|
}
|
|
|
void sim_queue_fn_mem_xi_write (
|
void sim_queue_fn_mem_xi_write (
|
SIM_CPU *cpu,
|
SIM_CPU *cpu,
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI *),
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI *),
|
SI address,
|
SI address,
|
SI *value
|
SI *value
|
)
|
)
|
{
|
{
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
element->kind = CGEN_FN_MEM_XI_WRITE;
|
element->kind = CGEN_FN_MEM_XI_WRITE;
|
element->insn_address = CPU_PC_GET (cpu);
|
element->insn_address = CPU_PC_GET (cpu);
|
element->kinds.fn_mem_xi_write.function = write_function;
|
element->kinds.fn_mem_xi_write.function = write_function;
|
element->kinds.fn_mem_xi_write.address = address;
|
element->kinds.fn_mem_xi_write.address = address;
|
element->kinds.fn_mem_xi_write.value[0] = value[0];
|
element->kinds.fn_mem_xi_write.value[0] = value[0];
|
element->kinds.fn_mem_xi_write.value[1] = value[1];
|
element->kinds.fn_mem_xi_write.value[1] = value[1];
|
element->kinds.fn_mem_xi_write.value[2] = value[2];
|
element->kinds.fn_mem_xi_write.value[2] = value[2];
|
element->kinds.fn_mem_xi_write.value[3] = value[3];
|
element->kinds.fn_mem_xi_write.value[3] = value[3];
|
}
|
}
|
|
|
/* Execute a write stored on the write queue. */
|
/* Execute a write stored on the write queue. */
|
void
|
void
|
cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item)
|
cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item)
|
{
|
{
|
IADDR pc;
|
IADDR pc;
|
switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
|
switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
|
{
|
{
|
case CGEN_BI_WRITE:
|
case CGEN_BI_WRITE:
|
*item->kinds.bi_write.target = item->kinds.bi_write.value;
|
*item->kinds.bi_write.target = item->kinds.bi_write.value;
|
break;
|
break;
|
case CGEN_QI_WRITE:
|
case CGEN_QI_WRITE:
|
*item->kinds.qi_write.target = item->kinds.qi_write.value;
|
*item->kinds.qi_write.target = item->kinds.qi_write.value;
|
break;
|
break;
|
case CGEN_SI_WRITE:
|
case CGEN_SI_WRITE:
|
*item->kinds.si_write.target = item->kinds.si_write.value;
|
*item->kinds.si_write.target = item->kinds.si_write.value;
|
break;
|
break;
|
case CGEN_SF_WRITE:
|
case CGEN_SF_WRITE:
|
*item->kinds.sf_write.target = item->kinds.sf_write.value;
|
*item->kinds.sf_write.target = item->kinds.sf_write.value;
|
break;
|
break;
|
case CGEN_PC_WRITE:
|
case CGEN_PC_WRITE:
|
CPU_PC_SET (cpu, item->kinds.pc_write.value);
|
CPU_PC_SET (cpu, item->kinds.pc_write.value);
|
break;
|
break;
|
case CGEN_FN_HI_WRITE:
|
case CGEN_FN_HI_WRITE:
|
item->kinds.fn_hi_write.function (cpu,
|
item->kinds.fn_hi_write.function (cpu,
|
item->kinds.fn_hi_write.regno,
|
item->kinds.fn_hi_write.regno,
|
item->kinds.fn_hi_write.value);
|
item->kinds.fn_hi_write.value);
|
break;
|
break;
|
case CGEN_FN_SI_WRITE:
|
case CGEN_FN_SI_WRITE:
|
item->kinds.fn_si_write.function (cpu,
|
item->kinds.fn_si_write.function (cpu,
|
item->kinds.fn_si_write.regno,
|
item->kinds.fn_si_write.regno,
|
item->kinds.fn_si_write.value);
|
item->kinds.fn_si_write.value);
|
break;
|
break;
|
case CGEN_FN_SF_WRITE:
|
case CGEN_FN_SF_WRITE:
|
item->kinds.fn_sf_write.function (cpu,
|
item->kinds.fn_sf_write.function (cpu,
|
item->kinds.fn_sf_write.regno,
|
item->kinds.fn_sf_write.regno,
|
item->kinds.fn_sf_write.value);
|
item->kinds.fn_sf_write.value);
|
break;
|
break;
|
case CGEN_FN_DI_WRITE:
|
case CGEN_FN_DI_WRITE:
|
item->kinds.fn_di_write.function (cpu,
|
item->kinds.fn_di_write.function (cpu,
|
item->kinds.fn_di_write.regno,
|
item->kinds.fn_di_write.regno,
|
item->kinds.fn_di_write.value);
|
item->kinds.fn_di_write.value);
|
break;
|
break;
|
case CGEN_FN_DF_WRITE:
|
case CGEN_FN_DF_WRITE:
|
item->kinds.fn_df_write.function (cpu,
|
item->kinds.fn_df_write.function (cpu,
|
item->kinds.fn_df_write.regno,
|
item->kinds.fn_df_write.regno,
|
item->kinds.fn_df_write.value);
|
item->kinds.fn_df_write.value);
|
break;
|
break;
|
case CGEN_FN_XI_WRITE:
|
case CGEN_FN_XI_WRITE:
|
item->kinds.fn_xi_write.function (cpu,
|
item->kinds.fn_xi_write.function (cpu,
|
item->kinds.fn_xi_write.regno,
|
item->kinds.fn_xi_write.regno,
|
item->kinds.fn_xi_write.value);
|
item->kinds.fn_xi_write.value);
|
break;
|
break;
|
case CGEN_FN_PC_WRITE:
|
case CGEN_FN_PC_WRITE:
|
item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value);
|
item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value);
|
break;
|
break;
|
case CGEN_MEM_QI_WRITE:
|
case CGEN_MEM_QI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address,
|
SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address,
|
item->kinds.mem_qi_write.value);
|
item->kinds.mem_qi_write.value);
|
break;
|
break;
|
case CGEN_MEM_HI_WRITE:
|
case CGEN_MEM_HI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address,
|
SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address,
|
item->kinds.mem_hi_write.value);
|
item->kinds.mem_hi_write.value);
|
break;
|
break;
|
case CGEN_MEM_SI_WRITE:
|
case CGEN_MEM_SI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
SETMEMSI (cpu, pc, item->kinds.mem_si_write.address,
|
SETMEMSI (cpu, pc, item->kinds.mem_si_write.address,
|
item->kinds.mem_si_write.value);
|
item->kinds.mem_si_write.value);
|
break;
|
break;
|
case CGEN_MEM_DI_WRITE:
|
case CGEN_MEM_DI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
SETMEMDI (cpu, pc, item->kinds.mem_di_write.address,
|
SETMEMDI (cpu, pc, item->kinds.mem_di_write.address,
|
item->kinds.mem_di_write.value);
|
item->kinds.mem_di_write.value);
|
break;
|
break;
|
case CGEN_MEM_DF_WRITE:
|
case CGEN_MEM_DF_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
SETMEMDF (cpu, pc, item->kinds.mem_df_write.address,
|
SETMEMDF (cpu, pc, item->kinds.mem_df_write.address,
|
item->kinds.mem_df_write.value);
|
item->kinds.mem_df_write.value);
|
break;
|
break;
|
case CGEN_MEM_XI_WRITE:
|
case CGEN_MEM_XI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address,
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address,
|
item->kinds.mem_xi_write.value[0]);
|
item->kinds.mem_xi_write.value[0]);
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 4,
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 4,
|
item->kinds.mem_xi_write.value[1]);
|
item->kinds.mem_xi_write.value[1]);
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 8,
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 8,
|
item->kinds.mem_xi_write.value[2]);
|
item->kinds.mem_xi_write.value[2]);
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 12,
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 12,
|
item->kinds.mem_xi_write.value[3]);
|
item->kinds.mem_xi_write.value[3]);
|
break;
|
break;
|
case CGEN_FN_MEM_QI_WRITE:
|
case CGEN_FN_MEM_QI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
item->kinds.fn_mem_qi_write.function (cpu, pc,
|
item->kinds.fn_mem_qi_write.function (cpu, pc,
|
item->kinds.fn_mem_qi_write.address,
|
item->kinds.fn_mem_qi_write.address,
|
item->kinds.fn_mem_qi_write.value);
|
item->kinds.fn_mem_qi_write.value);
|
break;
|
break;
|
case CGEN_FN_MEM_HI_WRITE:
|
case CGEN_FN_MEM_HI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
item->kinds.fn_mem_hi_write.function (cpu, pc,
|
item->kinds.fn_mem_hi_write.function (cpu, pc,
|
item->kinds.fn_mem_hi_write.address,
|
item->kinds.fn_mem_hi_write.address,
|
item->kinds.fn_mem_hi_write.value);
|
item->kinds.fn_mem_hi_write.value);
|
break;
|
break;
|
case CGEN_FN_MEM_SI_WRITE:
|
case CGEN_FN_MEM_SI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
item->kinds.fn_mem_si_write.function (cpu, pc,
|
item->kinds.fn_mem_si_write.function (cpu, pc,
|
item->kinds.fn_mem_si_write.address,
|
item->kinds.fn_mem_si_write.address,
|
item->kinds.fn_mem_si_write.value);
|
item->kinds.fn_mem_si_write.value);
|
break;
|
break;
|
case CGEN_FN_MEM_DI_WRITE:
|
case CGEN_FN_MEM_DI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
item->kinds.fn_mem_di_write.function (cpu, pc,
|
item->kinds.fn_mem_di_write.function (cpu, pc,
|
item->kinds.fn_mem_di_write.address,
|
item->kinds.fn_mem_di_write.address,
|
item->kinds.fn_mem_di_write.value);
|
item->kinds.fn_mem_di_write.value);
|
break;
|
break;
|
case CGEN_FN_MEM_DF_WRITE:
|
case CGEN_FN_MEM_DF_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
item->kinds.fn_mem_df_write.function (cpu, pc,
|
item->kinds.fn_mem_df_write.function (cpu, pc,
|
item->kinds.fn_mem_df_write.address,
|
item->kinds.fn_mem_df_write.address,
|
item->kinds.fn_mem_df_write.value);
|
item->kinds.fn_mem_df_write.value);
|
break;
|
break;
|
case CGEN_FN_MEM_XI_WRITE:
|
case CGEN_FN_MEM_XI_WRITE:
|
pc = item->insn_address;
|
pc = item->insn_address;
|
item->kinds.fn_mem_xi_write.function (cpu, pc,
|
item->kinds.fn_mem_xi_write.function (cpu, pc,
|
item->kinds.fn_mem_xi_write.address,
|
item->kinds.fn_mem_xi_write.address,
|
item->kinds.fn_mem_xi_write.value);
|
item->kinds.fn_mem_xi_write.value);
|
break;
|
break;
|
default:
|
default:
|
abort ();
|
abort ();
|
break; /* FIXME: for now....print message later. */
|
break; /* FIXME: for now....print message later. */
|
}
|
}
|
}
|
}
|
|
|
/* Utilities for the write queue. */
|
/* Utilities for the write queue. */
|
CGEN_WRITE_QUEUE_ELEMENT *
|
CGEN_WRITE_QUEUE_ELEMENT *
|
cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q)
|
cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q)
|
{
|
{
|
abort (); /* FIXME: for now....print message later. */
|
abort (); /* FIXME: for now....print message later. */
|
return 0;
|
return 0;
|
}
|
}
|
|
|
